URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [i386/] [pr36246.c] - Blame information for rev 328

Go to most recent revision | Details | Compare with Previous | View Log


/* { dg-do compile } */
/* { dg-require-effective-target lp64 } */
/* { dg-options "-O2 -fomit-frame-pointer -mtune=generic" } */
 
typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
typedef int __v4si __attribute__ ((__vector_size__ (16)));
 
__m128i
_mm_set_epi32 (int __q3, int __q2, int __q1, int __q0)
{
  return (__m128i)(__v4si){ __q0, __q1, __q2, __q3 };
}
 
/* { dg-final { scan-assembler-not "movq" } } */

Line No.	Rev	Author	Line
1	318	jeremybenn	`/* { dg-do compile } */`
2			`/* { dg-require-effective-target lp64 } */`
3			`/* { dg-options "-O2 -fomit-frame-pointer -mtune=generic" } */`
4
5			`typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));`
6			`typedef int __v4si __attribute__ ((__vector_size__ (16)));`
7
8			`__m128i`
9			`_mm_set_epi32 (int __q3, int __q2, int __q1, int __q0)`
10			`{`
11			`return (__m128i)(__v4si){ __q0, __q1, __q2, __q3 };`
12			`}`
13
14			`/* { dg-final { scan-assembler-not "movq" } } */`

Browse

Tools

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [i386/] [pr36246.c] - Blame information for rev 328