OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [i386/] [pr38931.c] - Blame information for rev 318

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 318 jeremybenn
/* { dg-do compile } */
2
/* { dg-options "-O2 -msse" } */
3
/* { dg-require-effective-target sse } */
4
 
5
typedef int __m64 __attribute__ ((__vector_size__ (8)));
6
 
7
extern __m64 foo () ;
8
 
9
void bar (const int input_bpl, const unsigned char *input,
10
          unsigned char *output, unsigned long x1)
11
{
12
  unsigned char *pix_end_ptr = output + x1 * 4;
13
  __m64 m_original = { 0, 0 };
14
  __m64 m_base_addr = __builtin_ia32_vec_init_v2si (0, input_bpl);
15
  __m64 m_addr = __builtin_ia32_paddd (m_original, m_base_addr);
16
  __m64 *a0 = (__m64 *) input;
17
 
18
  for (; output < pix_end_ptr; output += 4)
19
    {
20
      a0 = (__m64 *) (input + __builtin_ia32_vec_ext_v2si (m_addr, 0));
21
      m_addr = foo ();
22
      __builtin_prefetch (a0, 0);
23
    }
24
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.