URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [i386/] [rotate-1.c] - Blame information for rev 318

Details | Compare with Previous | View Log


/* Verify that rolb instruction is emitted on IA-32/x86-64.  */
/* { dg-do compile } */
/* { dg-options "-O2" } */
 
void foo (unsigned char *);
 
int
main (void)
{
  unsigned char c = 0;
  foo (&c);
  c = c >> 1 | c << 7;
  return c;
}
 
/* { dg-final { scan-assembler "rolb" } } */

Line No.	Rev	Author	Line
1	318	jeremybenn	`/* Verify that rolb instruction is emitted on IA-32/x86-64. */`
2			`/* { dg-do compile } */`
3			`/* { dg-options "-O2" } */`
4
5			`void foo (unsigned char *);`
6
7			`int`
8			`main (void)`
9			`{`
10			`unsigned char c = 0;`
11			`foo (&c);`
12			`c = c >> 1 \| c << 7;`
13			`return c;`
14			`}`
15
16			`/* { dg-final { scan-assembler "rolb" } } */`

Browse

Tools

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [i386/] [rotate-1.c] - Blame information for rev 318