OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [i386/] [signbit-3.c] - Blame information for rev 318

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 318 jeremybenn
/* PR optimization/8746 */
2
/* { dg-do run } */
3
/* { dg-require-effective-target ilp32 } */
4
/* { dg-options "-O1 -mtune=i586" } */
5
 
6
extern void abort (void);
7
 
8
volatile int j;
9
 
10
void f0() { j=0; }
11
void f1() { j=1; }
12
 
13
int foo(int x)
14
{
15
  if ((short int)(x&0x8000) > (short int)0)
16
  {
17
    f0();
18
    return 0;
19
  }
20
  else
21
  {
22
    f1();
23
    return 1;
24
  }
25
}
26
 
27
int main(void)
28
{
29
  if (foo(0x8000) != 1)
30
    abort();
31
 
32
   return 0;
33
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.