OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [i386/] [sse2-paddusw-1.c] - Blame information for rev 318

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 318 jeremybenn
/* { dg-do run } */
2
/* { dg-options "-O2 -msse2" } */
3
/* { dg-require-effective-target sse2 } */
4
 
5
#ifndef CHECK_H
6
#define CHECK_H "sse2-check.h"
7
#endif
8
 
9
#ifndef TEST
10
#define TEST sse2_test
11
#endif
12
 
13
#include CHECK_H
14
 
15
#include <emmintrin.h>
16
 
17
static __m128i
18
__attribute__((noinline, unused))
19
test (__m128i s1, __m128i s2)
20
{
21
  return _mm_adds_epu16 (s1, s2);
22
}
23
 
24
static void
25
TEST (void)
26
{
27
  union128i_w u, s1, s2;
28
  short e[8];
29
  int i, tmp;
30
 
31
  s1.x = _mm_set_epi16 (10,20,30,90,80,40,100,15);
32
  s2.x = _mm_set_epi16 (11, 98, 76, 100, 34, 78, 39, 14);
33
  u.x = test (s1.x, s2.x);
34
 
35
  for (i = 0; i < 8; i++)
36
    {
37
      tmp = s1.a[i] + s2.a[i];
38
 
39
      if (tmp > 65535)
40
        tmp = -1;
41
 
42
      if (tmp < 0)
43
        tmp = 0;
44
 
45
      e[i] = tmp;
46
    }
47
 
48
  if (check_union128i_w (u, e))
49
    abort ();
50
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.