OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [i386/] [sse2-psraw-1.c] - Blame information for rev 318

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 318 jeremybenn
/* { dg-do run } */
2
/* { dg-options "-O2 -msse2" } */
3
/* { dg-require-effective-target sse2 } */
4
 
5
#ifndef CHECK_H
6
#define CHECK_H "sse2-check.h"
7
#endif
8
 
9
#ifndef TEST
10
#define TEST sse2_test
11
#endif
12
 
13
#define N 0xb
14
 
15
#include CHECK_H
16
 
17
#include <emmintrin.h>
18
 
19
static __m128i
20
__attribute__((noinline, unused))
21
test (__m128i s1)
22
{
23
  return _mm_srai_epi16 (s1, N);
24
}
25
 
26
static void
27
TEST (void)
28
{
29
  union128i_w u, s;
30
  short e[8] = {0};
31
  int i;
32
 
33
  s.x = _mm_set_epi16 (1, -2, 3, 4, -5, 6, 0x7000, 0x9000);
34
 
35
  u.x = test (s.x);
36
 
37
  if (N < 16)
38
    for (i = 0; i < 8; i++)
39
      e[i] = s.a[i] >> N;
40
 
41
  if (check_union128i_w (u, e))
42
    abort ();
43
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.