OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [i386/] [sse4_1-pmovsxbw.c] - Blame information for rev 318

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 318 jeremybenn
/* { dg-do run } */
2
/* { dg-require-effective-target sse4 } */
3
/* { dg-options "-O2 -msse4.1" } */
4
 
5
#ifndef CHECK_H
6
#define CHECK_H "sse4_1-check.h"
7
#endif
8
 
9
#ifndef TEST
10
#define TEST sse4_1_test
11
#endif
12
 
13
#include CHECK_H
14
 
15
#include <smmintrin.h>
16
 
17
#define NUM 128
18
 
19
static void
20
TEST (void)
21
{
22
  union
23
    {
24
      __m128i x[NUM / 8];
25
      short s[NUM];
26
      char c[NUM * 2];
27
    } dst, src;
28
  int i, sign = 1;
29
 
30
  for (i = 0; i < NUM; i++)
31
    {
32
      src.c[(i % 8) + (i / 8) * 16] = i * i * sign;
33
      sign = -sign;
34
    }
35
 
36
  for (i = 0; i < NUM; i += 8)
37
    dst.x [i / 8] = _mm_cvtepi8_epi16 (src.x [i / 8]);
38
 
39
  for (i = 0; i < NUM; i++)
40
    if (src.c[(i % 8) + (i / 8) * 16] != dst.s[i])
41
      abort ();
42
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.