URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [m68k/] [pr36133.c] - Blame information for rev 328

Go to most recent revision | Details | Compare with Previous | View Log


/* pr36133.c
 
   This test ensures that conditional branches can use the condition codes
   written by shift instructions, without the need for an extra TST.  */
 
/* { dg-do compile }  */
/* { dg-options "-O2" }  */
/* { dg-final { scan-assembler-not "tst" } } */
 
void
f (unsigned int a)
{
  if (a >> 4)
    asm volatile ("nop");
  asm volatile ("nop");
}

Line No.	Rev	Author	Line
1	320	jeremybenn	`/* pr36133.c`
2
3			`This test ensures that conditional branches can use the condition codes`
4			`written by shift instructions, without the need for an extra TST. */`
5
6			`/* { dg-do compile } */`
7			`/* { dg-options "-O2" } */`
8			`/* { dg-final { scan-assembler-not "tst" } } */`
9
10			`void`
11			`f (unsigned int a)`
12			`{`
13			`if (a >> 4)`
14			`asm volatile ("nop");`
15			`asm volatile ("nop");`
16			`}`

Browse

Tools

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [m68k/] [pr36133.c] - Blame information for rev 328