OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [mips/] [branch-13.c] - Blame information for rev 321

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 321 jeremybenn
/* { dg-options "-mabicalls -mshared -mabi=64" } */
2
/* { dg-final { scan-assembler "\tsd\t\\\$28," } } */
3
/* { dg-final { scan-assembler "\tld\t\\\$28," } } */
4
/* { dg-final { scan-assembler "\tdaddiu\t\\\$28,\\\$28,%lo\\(%neg\\(%gp_rel\\(foo\\)\\)\\)\n" } } */
5
/* { dg-final { scan-assembler "\tld\t\\\$1,%got_page\\(\[^)\]*\\)\\(\\\$28\\)\n" } } */
6
/* { dg-final { scan-assembler "\tdaddiu\t\\\$1,\\\$1,%got_ofst\\(\[^)\]*\\)\n" } } */
7
/* { dg-final { scan-assembler "\tjr\t\\\$1\n" } } */
8
 
9
#include "branch-helper.h"
10
 
11
NOMIPS16 void
12
foo (void (*bar) (void), volatile int *x)
13
{
14
  bar ();
15
  if (__builtin_expect (*x == 0, 1))
16
    OCCUPY_0x1fffc;
17
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.