OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [mips/] [code-readable-3.c] - Blame information for rev 328

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 321 jeremybenn 
/* { dg-options "(-mips16) -mcode-readable=no -mgp32 addressing=absolute" } */
2 
 
3 
MIPS16 int
4 
foo (int i)
5 
{
6 
  switch (i)
7 
    {
8 
    case 1: return 40;
9 
    case 2: return 11;
10 
    case 3: return 29;
11 
    case 4: return 10;
12 
    case 5: return 12;
13 
    case 6: return 35;
14 
    case 7: return 23;
15 
    default: return 0;
16 
    }
17 
}
18 
 
19 
extern int k[];
20 
 
21 
MIPS16 int *
22 
bar (void)
23 
{
24 
  return k;
25 
}
26 
 
27 
/* { dg-final { scan-assembler-not "\tla\t" } } */
28 
/* { dg-final { scan-assembler-not "\t\\.half\t" } } */
29 
/* { dg-final { scan-assembler "%hi\\(\[^)\]*L" } } */
30 
/* { dg-final { scan-assembler "%lo\\(\[^)\]*L" } } */
31 
 
32 
/* { dg-final { scan-assembler-not "\t\\.word\tk\n" } } */
33 
/* { dg-final { scan-assembler "%hi\\(k\\)" } } */
34 
/* { dg-final { scan-assembler "%lo\\(k\\)" } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.