URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [mips/] [dmult-1.c] - Blame information for rev 321

Details | Compare with Previous | View Log


/* { dg-options "forbid_cpu=octeon -mgp64" } */
/* { dg-final { scan-assembler "\tdmult\t" } } */
/* { dg-final { scan-assembler "\tmflo\t" } } */
/* { dg-final { scan-assembler-not "\tdmul\t" } } */
 
long long
f (long long a, long long b)
{
  return a * b;
}

Line No.	Rev	Author	Line
1	321	jeremybenn	`/* { dg-options "forbid_cpu=octeon -mgp64" } */`
2			`/* { dg-final { scan-assembler "\tdmult\t" } } */`
3			`/* { dg-final { scan-assembler "\tmflo\t" } } */`
4			`/* { dg-final { scan-assembler-not "\tdmul\t" } } */`
5
6			`long long`
7			`f (long long a, long long b)`
8			`{`
9			`return a * b;`
10			`}`

Browse

Tools

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [mips/] [dmult-1.c] - Blame information for rev 321