OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [mips/] [ext-1.c] - Blame information for rev 321

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 321 jeremybenn
/* { dg-do compile } */
2
/* { dg-options "-O isa_rev>=2 -mgp64" } */
3
/* { dg-final { scan-assembler "\tdext\t" } } */
4
/* { dg-final { scan-assembler-not "and" } } */
5
 
6
struct
7
{
8
  unsigned long long a:9;
9
  unsigned long long d:35;
10
  unsigned long long e:10;
11
  unsigned long long f:10;
12
} t;
13
 
14
NOMIPS16 unsigned long long
15
f (void)
16
{
17
   return t.d;
18
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.