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[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [mips/] [mips32-dspr2.c] - Blame information for rev 321

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1 321 jeremybenn
/* Test MIPS32 DSP REV 2 instructions */
2
/* { dg-do run } */
3
/* { dg-options "-mdspr2 -O2" } */
4
 
5
typedef signed char v4q7 __attribute__ ((vector_size(4)));
6
typedef signed char v4i8 __attribute__ ((vector_size(4)));
7
typedef short v2q15 __attribute__ ((vector_size(4)));
8
typedef short v2i16 __attribute__ ((vector_size(4)));
9
typedef int q31;
10
typedef int i32;
11
typedef unsigned int ui32;
12
typedef long long a64;
13
 
14
void abort (void);
15
 
16
NOMIPS16 void test_MIPS_DSPR2 (void);
17
 
18
int little_endian;
19
 
20
int main ()
21
{
22
  union { long long ll; int i[2]; } endianness_test;
23
  endianness_test.ll = 1;
24
  little_endian = endianness_test.i[0];
25
 
26
  test_MIPS_DSPR2 ();
27
 
28
  return 0;
29
}
30
 
31
NOMIPS16 void test_MIPS_DSPR2 ()
32
{
33
  v4q7 v4q7_a,v4q7_b,v4q7_c,v4q7_r,v4q7_s;
34
  v4i8 v4i8_a,v4i8_b,v4i8_c,v4i8_r,v4i8_s;
35
  v2q15 v2q15_a,v2q15_b,v2q15_c,v2q15_r,v2q15_s;
36
  v2i16 v2i16_a,v2i16_b,v2i16_c,v2i16_r,v2i16_s;
37
  q31 q31_a,q31_b,q31_c,q31_r,q31_s;
38
  i32 i32_a,i32_b,i32_c,i32_r,i32_s;
39
  ui32 ui32_a,ui32_b,ui32_c,ui32_r,ui32_s;
40
  a64 a64_a,a64_b,a64_c,a64_r,a64_s;
41
 
42
  int r,s;
43
 
44
  v4q7_a = (v4i8) {0x81, 0xff, 0x80, 0x23};
45
  v4q7_s = (v4i8) {0x7f, 0x01, 0x7f, 0x23};
46
  v4q7_r = __builtin_mips_absq_s_qb (v4q7_a);
47
  r = (int) v4q7_r;
48
  s = (int) v4q7_s;
49
  if (r != s)
50
    abort ();
51
 
52
  v2i16_a = (v2i16) {0xffff, 0x2468};
53
  v2i16_b = (v2i16) {0x1234, 0x1111};
54
  v2i16_s = (v2i16) {0x1233, 0x3579};
55
  v2i16_r = __builtin_mips_addu_ph (v2i16_a, v2i16_b);
56
  r = (int) v2i16_r;
57
  s = (int) v2i16_s;
58
  if (r != s)
59
    abort ();
60
 
61
  v2i16_a = (v2i16) {0xffff, 0x2468};
62
  v2i16_b = (v2i16) {0x1234, 0x1111};
63
  v2i16_s = (v2i16) {0xffff, 0x3579};
64
  v2i16_r = __builtin_mips_addu_s_ph (v2i16_a, v2i16_b);
65
  r = (int) v2i16_r;
66
  s = (int) v2i16_s;
67
  if (r != s)
68
    abort ();
69
 
70
  v4i8_a = (v4i8) {0x11, 0x22, 0x33, 0xff};
71
  v4i8_b = (v4i8) {0x11, 0x33, 0x99, 0xff};
72
  v4i8_s = (v4i8) {0x11, 0x2a, 0x66, 0xff};
73
  v4i8_r = __builtin_mips_adduh_qb (v4i8_a, v4i8_b);
74
  r = (int) v4i8_r;
75
  s = (int) v4i8_s;
76
  if (r != s)
77
    abort ();
78
 
79
  v4i8_a = (v4i8) {0x11, 0x22, 0x33, 0xff};
80
  v4i8_b = (v4i8) {0x11, 0x33, 0x99, 0xff};
81
  v4i8_s = (v4i8) {0x11, 0x2b, 0x66, 0xff};
82
  v4i8_r = __builtin_mips_adduh_r_qb (v4i8_a, v4i8_b);
83
  r = (int) v4i8_r;
84
  s = (int) v4i8_s;
85
  if (r != s)
86
    abort ();
87
 
88
  i32_a = 0x12345678;
89
  i32_b = 0x87654321;
90
  i32_s = 0x56784321;
91
  i32_r = __builtin_mips_append (i32_a, i32_b, 16);
92
  if (i32_r != i32_s)
93
    abort ();
94
 
95
  i32_a = 0x12345678;
96
  i32_b = 0x87654321;
97
  i32_s = 0x78876543;
98
  i32_r = __builtin_mips_balign (i32_a, i32_b, 3);
99
  if (i32_r != i32_s)
100
    abort ();
101
 
102
  __builtin_mips_wrdsp (0, 63);
103
  v4i8_a = (v4i8) {0x11, 0x22, 0x33, 0x44};
104
  v4i8_b = (v4i8) {0x11, 0x33, 0x33, 0x44};
105
  if (little_endian)
106
    i32_s = 0xd;
107
  else
108
    i32_s = 0xb;
109
  i32_r = __builtin_mips_cmpgdu_eq_qb (v4i8_a, v4i8_b);
110
  if (i32_r != i32_s)
111
    abort ();
112
  i32_r = __builtin_mips_rddsp (16);
113
  if (little_endian)
114
    i32_s = 0x0d000000;
115
  else
116
    i32_s = 0x0b000000;
117
  if (i32_r != i32_s)
118
    abort ();
119
 
120
  __builtin_mips_wrdsp (0, 63);
121
  v4i8_a = (v4i8) {0x11, 0x22, 0x33, 0x44};
122
  v4i8_b = (v4i8) {0x11, 0x33, 0x33, 0x44};
123
  if (little_endian)
124
    i32_s = 0x2;
125
  else
126
    i32_s = 0x4;
127
  i32_r = __builtin_mips_cmpgdu_lt_qb (v4i8_a, v4i8_b);
128
  if (i32_r != i32_s)
129
    abort ();
130
  i32_r = __builtin_mips_rddsp (16);
131
  if (little_endian)
132
    i32_s = 0x02000000;
133
  else
134
    i32_s = 0x04000000;
135
  if (i32_r != i32_s)
136
    abort ();
137
 
138
  __builtin_mips_wrdsp (0, 63);
139
  v4i8_a = (v4i8) {0x11, 0x22, 0x33, 0x54};
140
  v4i8_b = (v4i8) {0x11, 0x33, 0x33, 0x44};
141
  if (little_endian)
142
    i32_s = 0x7;
143
  else
144
    i32_s = 0xe;
145
  i32_r = __builtin_mips_cmpgdu_le_qb (v4i8_a, v4i8_b);
146
  if (i32_r != i32_s)
147
    abort ();
148
  i32_r = __builtin_mips_rddsp (16);
149
  if (little_endian)
150
    i32_s = 0x07000000;
151
  else
152
    i32_s = 0x0e000000;
153
  if (i32_r != i32_s)
154
    abort ();
155
 
156
#ifndef __mips64
157
  a64_a = 0x12345678;
158
  v2i16_b = (v2i16) {0xffff, 0x1555};
159
  v2i16_c = (v2i16) {0x1234, 0x3322};
160
  a64_s = 0x1677088e;
161
  a64_r = __builtin_mips_dpa_w_ph (a64_a, v2i16_b, v2i16_c);
162
  if (a64_r != a64_s)
163
    abort ();
164
#endif
165
 
166
#ifndef __mips64
167
  a64_a = 0x12345678;
168
  v2i16_b = (v2i16) {0xffff, 0x1555};
169
  v2i16_c = (v2i16) {0x1234, 0x3322};
170
  a64_s = 0x0df1a462;
171
  a64_r = __builtin_mips_dps_w_ph (a64_a, v2i16_b, v2i16_c);
172
  if (a64_r != a64_s)
173
    abort ();
174
#endif
175
 
176
#ifndef __mips64
177
  a64_a = 0x12345678;
178
  i32_b = 0x80000000;
179
  i32_c = 0x11112222;
180
  a64_s = 0xF7776EEF12345678LL;
181
  a64_r = __builtin_mips_madd (a64_a, i32_b, i32_c);
182
  if (a64_r != a64_s)
183
    abort ();
184
#endif
185
 
186
#ifndef __mips64
187
  a64_a = 0x12345678;
188
  ui32_b = 0x80000000;
189
  ui32_c = 0x11112222;
190
  a64_s = 0x0888911112345678LL;
191
  a64_r = __builtin_mips_maddu (a64_a, ui32_b, ui32_c);
192
  if (a64_r != a64_s)
193
    abort ();
194
#endif
195
 
196
#ifndef __mips64
197
  a64_a = 0x12345678;
198
  i32_b = 0x80000000;
199
  i32_c = 0x11112222;
200
  a64_s = 0x0888911112345678LL;
201
  a64_r = __builtin_mips_msub (a64_a, i32_b, i32_c);
202
  if (a64_r != a64_s)
203
    abort ();
204
#endif
205
 
206
#ifndef __mips64
207
  a64_a = 0x12345678;
208
  ui32_b = 0x80000000;
209
  ui32_c = 0x11112222;
210
  a64_s = 0xF7776EEF12345678LL;
211
  a64_r = __builtin_mips_msubu (a64_a, ui32_b, ui32_c);
212
  if (a64_r != a64_s)
213
    abort ();
214
#endif
215
 
216
  v2i16_a = (v2i16) {0xffff, 0x2468};
217
  v2i16_b = (v2i16) {0x1234, 0x1111};
218
  v2i16_s = (v2i16) {0xedcc, 0x52e8};
219
  v2i16_r = __builtin_mips_mul_ph (v2i16_a, v2i16_b);
220
  r = (int) v2i16_r;
221
  s = (int) v2i16_s;
222
  if (r != s)
223
    abort ();
224
 
225
  v2i16_a = (v2i16) {0x8000, 0x7fff};
226
  v2i16_b = (v2i16) {0x1234, 0x1111};
227
  v2i16_s = (v2i16) {0x8000, 0x7fff};
228
  v2i16_r = __builtin_mips_mul_s_ph (v2i16_a, v2i16_b);
229
  r = (int) v2i16_r;
230
  s = (int) v2i16_s;
231
  if (r != s)
232
    abort ();
233
 
234
  q31_a = 0x80000000;
235
  q31_b = 0x80000000;
236
  q31_s = 0x7fffffff;
237
  q31_r = __builtin_mips_mulq_rs_w (q31_a, q31_b);
238
  if (q31_r != q31_s)
239
    abort ();
240
 
241
  v2q15_a = (v2q15) {0xffff, 0x8000};
242
  v2q15_b = (v2q15) {0x1111, 0x8000};
243
  v2q15_s = (v2q15) {0xffff, 0x7fff};
244
  v2q15_r = __builtin_mips_mulq_s_ph (v2q15_a, v2q15_b);
245
  r = (int) v2q15_r;
246
  s = (int) v2q15_s;
247
  if (r != s)
248
    abort ();
249
 
250
  q31_a = 0x00000002;
251
  q31_b = 0x80000000;
252
  q31_s = 0xfffffffe;
253
  q31_r = __builtin_mips_mulq_s_w (q31_a, q31_b);
254
  if (q31_r != q31_s)
255
    abort ();
256
 
257
#ifndef __mips64
258
  a64_a = 0x19848419;
259
  v2i16_b = (v2i16) {0xffff, 0x8000};
260
  v2i16_c = (v2i16) {0x1111, 0x8000};
261
  if (little_endian)
262
    a64_s = 0x5984952a;
263
  else
264
    a64_s = 0xffffffffd9847308LL;
265
  a64_r = __builtin_mips_mulsa_w_ph (a64_a, v2i16_b, v2i16_c);
266
  if (a64_r != a64_s)
267
    abort ();
268
#endif
269
 
270
#ifndef __mips64
271
  i32_a = 0x80000000;
272
  i32_b = 0x11112222;
273
  a64_s = 0xF7776EEF00000000LL;
274
  a64_r = __builtin_mips_mult (i32_a, i32_b);
275
  if (a64_r != a64_s)
276
    abort ();
277
#endif
278
 
279
#ifndef __mips64
280
  ui32_a = 0x80000000;
281
  ui32_b = 0x11112222;
282
  a64_s = 0x888911100000000LL;
283
  a64_r = __builtin_mips_multu (ui32_a, ui32_b);
284
  if (a64_r != a64_s)
285
    abort ();
286
#endif
287
 
288
  v2i16_a = (v2i16) {0x1234, 0x5678};
289
  v2i16_b = (v2i16) {0x2233, 0x5566};
290
  if (little_endian)
291
    v4i8_s = (v4i8) {0x33, 0x66, 0x34, 0x78};
292
  else
293
    v4i8_s = (v4i8) {0x34, 0x78, 0x33, 0x66};
294
  v4i8_r = __builtin_mips_precr_qb_ph (v2i16_a, v2i16_b);
295
  r = (int) v4i8_r;
296
  s = (int) v4i8_s;
297
  if (r != s)
298
    abort ();
299
 
300
  i32_a = 0x12345678;
301
  i32_b = 0x33334444;
302
  if (little_endian)
303
    v2i16_s = (v2i16) {0x3444, 0x4567};
304
  else
305
    v2i16_s = (v2i16) {0x4567, 0x3444};
306
  v2i16_r = __builtin_mips_precr_sra_ph_w (i32_a, i32_b, 4);
307
  r = (int) v2i16_r;
308
  s = (int) v2i16_s;
309
  if (r != s)
310
    abort ();
311
 
312
  i32_a = 0x12345678;
313
  i32_b = 0x33334444;
314
  if (little_endian)
315
    v2i16_s = (v2i16) {0x3444, 0x4568};
316
  else
317
    v2i16_s = (v2i16) {0x4568, 0x3444};
318
  v2i16_r = __builtin_mips_precr_sra_r_ph_w (i32_a, i32_b, 4);
319
  r = (int) v2i16_r;
320
  s = (int) v2i16_s;
321
  if (r != s)
322
    abort ();
323
 
324
  i32_a = 0x12345678;
325
  i32_b = 0x87654321;
326
  i32_s = 0x43211234;
327
  i32_r = __builtin_mips_prepend (i32_a, i32_b, 16);
328
  if (i32_r != i32_s)
329
    abort ();
330
 
331
  v4i8_a = (v4i8) {0x12, 0x45, 0x77, 0x99};
332
  v4i8_s = (v4i8) {0x9, 0x22, 0x3b, 0xcc};
333
  v4i8_r = __builtin_mips_shra_qb (v4i8_a, 1);
334
  r = (int) v4i8_r;
335
  s = (int) v4i8_s;
336
  if (r != s)
337
    abort ();
338
 
339
  v4i8_a = (v4i8) {0x12, 0x45, 0x77, 0x99};
340
  v4i8_s = (v4i8) {0x9, 0x23, 0x3c, 0xcd};
341
  v4i8_r = __builtin_mips_shra_r_qb (v4i8_a, 1);
342
  r = (int) v4i8_r;
343
  s = (int) v4i8_s;
344
  if (r != s)
345
    abort ();
346
 
347
  i32_b = 1;
348
  v4i8_a = (v4i8) {0x12, 0x45, 0x77, 0x99};
349
  v4i8_s = (v4i8) {0x9, 0x22, 0x3b, 0xcc};
350
  v4i8_r = __builtin_mips_shra_qb (v4i8_a, i32_b);
351
  r = (int) v4i8_r;
352
  s = (int) v4i8_s;
353
  if (r != s)
354
    abort ();
355
 
356
  i32_b = 1;
357
  v4i8_a = (v4i8) {0x12, 0x45, 0x77, 0x99};
358
  v4i8_s = (v4i8) {0x9, 0x23, 0x3c, 0xcd};
359
  v4i8_r = __builtin_mips_shra_r_qb (v4i8_a, i32_b);
360
  r = (int) v4i8_r;
361
  s = (int) v4i8_s;
362
  if (r != s)
363
    abort ();
364
 
365
  v2i16_a = (v2i16) {0x1357, 0x2468};
366
  v2i16_s = (v2i16) {0x0135, 0x0246};
367
  v2i16_r = __builtin_mips_shrl_ph (v2i16_a, 4);
368
  r = (int) v2i16_r;
369
  s = (int) v2i16_s;
370
  if (r != s)
371
    abort ();
372
 
373
  i32_b = 8;
374
  v2i16_a = (v2i16) {0x1357, 0x2468};
375
  v2i16_s = (v2i16) {0x0013, 0x0024};
376
  v2i16_r = __builtin_mips_shrl_ph (v2i16_a, i32_b);
377
  r = (int) v2i16_r;
378
  s = (int) v2i16_s;
379
  if (r != s)
380
    abort ();
381
 
382
  v2i16_a = (v2i16) {0x1357, 0x4455};
383
  v2i16_b = (v2i16) {0x3333, 0x4444};
384
  v2i16_s = (v2i16) {0xe024, 0x0011};
385
  v2i16_r = __builtin_mips_subu_ph (v2i16_a, v2i16_b);
386
  r = (int) v2i16_r;
387
  s = (int) v2i16_s;
388
  if (r != s)
389
    abort ();
390
 
391
  v2i16_a = (v2i16) {0x1357, 0x4455};
392
  v2i16_b = (v2i16) {0x3333, 0x4444};
393
  v2i16_s = (v2i16) {0x0000, 0x0011};
394
  v2i16_r = __builtin_mips_subu_s_ph (v2i16_a, v2i16_b);
395
  r = (int) v2i16_r;
396
  s = (int) v2i16_s;
397
  if (r != s)
398
    abort ();
399
 
400
  v4i8_a = (v4i8) {0x33 ,0x44, 0x55, 0x66};
401
  v4i8_b = (v4i8) {0x99 ,0x15, 0x85, 0xff};
402
  v4i8_s = (v4i8) {0xcd ,0x17, 0xe8, 0xb3};
403
  v4i8_r = __builtin_mips_subuh_qb (v4i8_a, v4i8_b);
404
  r = (int) v4i8_r;
405
  s = (int) v4i8_s;
406
  if (r != s)
407
    abort ();
408
 
409
  v4i8_a = (v4i8) {0x33 ,0x44, 0x55, 0x66};
410
  v4i8_b = (v4i8) {0x99 ,0x15, 0x85, 0xff};
411
  v4i8_s = (v4i8) {0xcd ,0x18, 0xe8, 0xb4};
412
  v4i8_r = __builtin_mips_subuh_r_qb (v4i8_a, v4i8_b);
413
  r = (int) v4i8_r;
414
  s = (int) v4i8_s;
415
  if (r != s)
416
    abort ();
417
 
418
  v2q15_a = (v2q15) {0x3334, 0x4444};
419
  v2q15_b = (v2q15) {0x1111, 0x2222};
420
  v2q15_s = (v2q15) {0x2222, 0x3333};
421
  v2q15_r = __builtin_mips_addqh_ph (v2q15_a, v2q15_b);
422
  r = (int) v2q15_r;
423
  s = (int) v2q15_s;
424
  if (r != s)
425
    abort ();
426
 
427
  v2q15_a = (v2q15) {0x3334, 0x4444};
428
  v2q15_b = (v2q15) {0x1111, 0x2222};
429
  v2q15_s = (v2q15) {0x2223, 0x3333};
430
  v2q15_r = __builtin_mips_addqh_r_ph (v2q15_a, v2q15_b);
431
  r = (int) v2q15_r;
432
  s = (int) v2q15_s;
433
  if (r != s)
434
    abort ();
435
 
436
  q31_a = 0x11111112;
437
  q31_b = 0x99999999;
438
  q31_s = 0xd5555555;
439
  q31_r = __builtin_mips_addqh_w (q31_a, q31_b);
440
  if (q31_r != q31_s)
441
    abort ();
442
 
443
  q31_a = 0x11111112;
444
  q31_b = 0x99999999;
445
  q31_s = 0xd5555556;
446
  q31_r = __builtin_mips_addqh_r_w (q31_a, q31_b);
447
  if (q31_r != q31_s)
448
    abort ();
449
 
450
  v2q15_a = (v2q15) {0x3334, 0x4444};
451
  v2q15_b = (v2q15) {0x1111, 0x2222};
452
  v2q15_s = (v2q15) {0x1111, 0x1111};
453
  v2q15_r = __builtin_mips_subqh_ph (v2q15_a, v2q15_b);
454
  r = (int) v2q15_r;
455
  s = (int) v2q15_s;
456
  if (r != s)
457
    abort ();
458
 
459
  v2q15_a = (v2q15) {0x3334, 0x4444};
460
  v2q15_b = (v2q15) {0x1111, 0x2222};
461
  v2q15_s = (v2q15) {0x1112, 0x1111};
462
  v2q15_r = __builtin_mips_subqh_r_ph (v2q15_a, v2q15_b);
463
  r = (int) v2q15_r;
464
  s = (int) v2q15_s;
465
  if (r != s)
466
    abort ();
467
 
468
  q31_a = 0x11111112;
469
  q31_b = 0x99999999;
470
  q31_s = 0x3bbbbbbc;
471
  q31_r = __builtin_mips_subqh_w (q31_a, q31_b);
472
  if (q31_r != q31_s)
473
    abort ();
474
 
475
  q31_a = 0x11111112;
476
  q31_b = 0x99999999;
477
  q31_s = 0x3bbbbbbd;
478
  q31_r = __builtin_mips_subqh_r_w (q31_a, q31_b);
479
  if (q31_r != q31_s)
480
    abort ();
481
 
482
#ifndef __mips64
483
  a64_a = 0x1111222212345678LL;
484
  v2i16_b = (v2i16) {0x1, 0x2};
485
  v2i16_c = (v2i16) {0x3, 0x4};
486
  a64_s = 0x1111222212345682LL;
487
  a64_r = __builtin_mips_dpax_w_ph (a64_a, v2i16_b, v2i16_c);
488
  if (a64_r != a64_s)
489
    abort ();
490
#endif
491
 
492
#ifndef __mips64
493
  a64_a = 0x9999111112345678LL;
494
  v2i16_b = (v2i16) {0x1, 0x2};
495
  v2i16_c = (v2i16) {0x3, 0x4};
496
  a64_s = 0x999911111234566eLL;
497
  a64_r = __builtin_mips_dpsx_w_ph (a64_a, v2i16_b, v2i16_c);
498
  if (a64_r != a64_s)
499
    abort ();
500
#endif
501
 
502
#ifndef __mips64
503
  a64_a = 0x70000000;
504
  v2q15_b = (v2q15) {0x4000, 0x2000};
505
  v2q15_c = (v2q15) {0x2000, 0x4000};
506
  a64_s = 0x98000000;
507
  a64_r = __builtin_mips_dpaqx_s_w_ph (a64_a, v2q15_b, v2q15_c);
508
  if (a64_r != a64_s)
509
    abort ();
510
#endif
511
 
512
#ifndef __mips64
513
  a64_a = 0x70000000;
514
  v2q15_b = (v2q15) {0x4000, 0x2000};
515
  v2q15_c = (v2q15) {0x2000, 0x4000};
516
  a64_s = 0x7fffffff;
517
  a64_r = __builtin_mips_dpaqx_sa_w_ph (a64_a, v2q15_b, v2q15_c);
518
  if (a64_r != a64_s)
519
    abort ();
520
#endif
521
 
522
#ifndef __mips64
523
  a64_a = 0x70000000;
524
  v2q15_b = (v2q15) {0x4000, 0x2000};
525
  v2q15_c = (v2q15) {0x2000, 0x4000};
526
  a64_s = 0x48000000;
527
  a64_r = __builtin_mips_dpsqx_s_w_ph (a64_a, v2q15_b, v2q15_c);
528
  if (a64_r != a64_s)
529
    abort ();
530
#endif
531
 
532
#ifndef __mips64
533
  a64_a = 0xFFFFFFFF80000000LL;
534
  v2q15_b = (v2q15) {0x4000, 0x2000};
535
  v2q15_c = (v2q15) {0x2000, 0x4000};
536
  a64_s = 0xFFFFFFFF80000000LL;
537
  a64_r = __builtin_mips_dpsqx_sa_w_ph (a64_a, v2q15_b, v2q15_c);
538
  if (a64_r != a64_s)
539
    abort ();
540
#endif
541
}

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