OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [mips/] [mult-1.c] - Blame information for rev 321

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 321 jeremybenn
/* For SI->DI widening multiplication we should use DINS to combine the two
2
   halves.  For Octeon use DMUL with explicit widening.  */
3
/* { dg-options "-O -mgp64 isa_rev>=2 forbid_cpu=octeon" } */
4
/* { dg-final { scan-assembler "\tdins\t" } } */
5
/* { dg-final { scan-assembler-not "\tdsll\t" } } */
6
/* { dg-final { scan-assembler-not "\tdsrl\t" } } */
7
/* { dg-final { scan-assembler-not "\tor\t" } } */
8
 
9
NOMIPS16 unsigned long long
10
f (unsigned int i, unsigned int j)
11
{
12
  i++;
13
  return (unsigned long long) i * j;
14
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.