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[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [mips/] [r10k-cache-barrier-2.c] - Blame information for rev 321

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Line No. Rev Author Line
1 321 jeremybenn
/* { dg-options "-O2 -mabi=64 -mr10k-cache-barrier=store" } */
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/* Test that stores to constant cached addresses are protected
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   by cache barriers.  */
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#define TEST(ADDR)                                      \
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  NOMIPS16 void                                         \
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  test_##ADDR (int n)                                   \
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  {                                                     \
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    *(volatile int *) (0x##ADDR##UL) = 1;               \
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  }
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TEST (8ffffffffffffffc)
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TEST (9000010000000000)
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TEST (91fffffffffffffc)
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TEST (9200010000000000)
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TEST (93fffffffffffffc)
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TEST (9500010000000000)
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TEST (95fffffffffffffc)
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TEST (9600010000000000)
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TEST (b7fffffffffffffc)
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TEST (b800010000000000)
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TEST (b9fffffffffffffc)
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TEST (ba00010000000000)
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TEST (bbfffffffffffffc)
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TEST (bc00010000000000)
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TEST (bdfffffffffffffc)
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TEST (be00010000000000)
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TEST (ffffffff9ffffffc)
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TEST (ffffffffc0000000)
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/* { dg-final { scan-assembler-times "\tcache\t" 18 } } */

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