OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [mips/] [r10k-cache-barrier-3.c] - Blame information for rev 321

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 321 jeremybenn
/* { dg-options "-O2 -mr10k-cache-barrier=store -mno-abicalls" } */
2
 
3
/* Test that in-range stores to the frame are not protected by
4
   cache barriers.  */
5
 
6
void bar (int *x);
7
 
8
NOMIPS16 void
9
foo (int v)
10
{
11
  int x[0x100000];
12
  bar (x);
13
  x[0x20] = v;
14
  bar (x);
15
}
16
 
17
/* { dg-final { scan-assembler-not "\tcache\t" } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.