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[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [mips/] [r10k-cache-barrier-7.c] - Blame information for rev 321

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Line No. Rev Author Line
1 321 jeremybenn
/* { dg-options "-O2 -mr10k-cache-barrier=store -mno-abicalls" } */
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void bar1 (void);
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void bar2 (void);
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void bar3 (void);
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NOMIPS16 void
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foo (int *x, int sel, int n)
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{
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  if (sel)
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    {
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      bar1 ();
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      x[0] = 1;
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    }
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  else
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    {
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      bar2 ();
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      x[1] = 0;
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    }
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  /* If there is one copy of this code, reached by two unconditional edges,
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     then it shouldn't need a third cache barrier.  */
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  x[2] = 2;
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  while (n--)
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    bar3 ();
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}
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/* { dg-final { scan-assembler-times "\tcache\t" 2 } } */

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