OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [powerpc/] [altivec-18.c] - Blame information for rev 322

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 322 jeremybenn
/* { dg-do compile { target powerpc*-*-* } } */
2
/* { dg-require-effective-target powerpc_altivec_ok } */
3
/* { dg-options "-maltivec -mabi=altivec" } */
4
/* { dg-final { scan-assembler "vcmpgtub" { target *-*-linux* } } } */
5
/* { dg-final { scan-assembler "vcmpgtsb" { target *-*-darwin* } } } */
6
/* { dg-final { scan-assembler "vcmpgtsh" } } */
7
/* { dg-final { scan-assembler "vcmpgtsw" } } */
8
 
9
/* Verify a statement in the GCC Manual that vector type specifiers can
10
   omit "signed" or "unsigned".  The default is the default signedness
11
   of the base type, which differs depending on the ABI.  */
12
 
13
#include <altivec.h>
14
 
15
extern vector char vc1, vc2;
16
extern vector short vs1, vs2;
17
extern vector int vi1, vi2;
18
 
19
int signedness (void)
20
{
21
    return vec_all_le (vc1, vc2)
22
           && vec_all_le (vs1, vs2)
23
           && vec_all_le (vi1, vi2);
24
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.