OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [s390/] [pr36822.c] - Blame information for rev 324

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 324 jeremybenn
/* This used to ICE on s390 due to bug in the definition of the 'R'
2
   constraint which replaced the 'm' constraint (together with 'T')
3
   while adding z10 support.  */
4
 
5
/* { dg-do compile } */
6
/* { dg-options "-O" } */
7
 
8
int boo()
9
{
10
  struct {
11
    unsigned char pad[4096];
12
    unsigned long bar;
13
  } *foo;
14
  asm volatile( "" : "=m" (*(unsigned long long*)(foo->bar))
15
                : "a" (&foo->bar));
16
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.