OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [sparc/] [align.c] - Blame information for rev 326

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 326 jeremybenn
/* { dg-do compile } */
2
/* { dg-options "-mcpu=ultrasparc -mvis" } */
3
typedef long long int64_t;
4
typedef int vec32 __attribute__((vector_size(8)));
5
typedef short vec16 __attribute__((vector_size(8)));
6
typedef unsigned char vec8 __attribute__((vector_size(8)));
7
 
8
vec16 foo1 (vec16 a, vec16 b) {
9
  return __builtin_vis_faligndatav4hi (a, b);
10
}
11
 
12
vec32 foo2 (vec32 a, vec32 b) {
13
  return __builtin_vis_faligndatav2si (a, b);
14
}
15
 
16
vec8 foo3 (vec8 a, vec8 b) {
17
  return __builtin_vis_faligndatav8qi (a, b);
18
}
19
 
20
int64_t foo4 (int64_t a, int64_t b) {
21
  return __builtin_vis_faligndatadi (a, b);
22
}
23
 
24
unsigned char * foo5 (unsigned char *data) {
25
  return __builtin_vis_alignaddr (data, 0);
26
}
27
 
28
/* { dg-final { scan-assembler-times "faligndata" 4 } } */
29
/* { dg-final { scan-assembler "alignaddr.*%g0" } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.