OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [sparc/] [fand.c] - Blame information for rev 329

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 326 jeremybenn
/* { dg-do compile } */
2
/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
3
typedef char  vec8 __attribute__((vector_size(8)));
4
typedef short vec16 __attribute__((vector_size(8)));
5
typedef int   vec32 __attribute__((vector_size(8)));
6
 
7
extern vec8 foo1_8(void);
8
extern vec8 foo2_8(void);
9
 
10
vec8 fun8(void)
11
{
12
  return foo1_8 () & foo2_8 ();
13
}
14
 
15
#ifndef __LP64__
16
/* Test the 32-bit splitter. */
17
vec8 fun8_2(vec8 a, vec8 b)
18
{
19
  return a & b;
20
}
21
#endif
22
 
23
extern vec16 foo1_16(void);
24
extern vec16 foo2_16(void);
25
 
26
vec16 fun16(void)
27
{
28
  return foo1_16 () & foo2_16 ();
29
}
30
 
31
#ifndef __LP64__
32
/* Test the 32-bit splitter. */
33
vec16 fun16_2(vec16 a, vec16 b)
34
{
35
  return a & b;
36
}
37
#endif
38
 
39
extern vec32 foo1_32(void);
40
extern vec32 foo2_32(void);
41
 
42
vec32 fun32(void)
43
{
44
  return foo1_32 () & foo2_32 ();
45
}
46
 
47
#ifndef __LP64__
48
/* Test the 32-bit splitter. */
49
vec32 fun32_2(vec32 a, vec32 b)
50
{
51
  return a & b;
52
}
53
#endif
54
 
55
/* { dg-final { scan-assembler-times "fand\t%" 3 } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.