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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [sparc/] [fpadd32s.c] - Blame information for rev 326

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/* { dg-do compile } */
/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
typedef int vec32 __attribute__((vector_size(4)));
 
extern vec32 foo1(void);
extern vec32 foo2(void);
 
vec32 bar(void)
{
  return foo1 () + foo2 ();
}
 
/* { dg-final { scan-assembler "fpadd32s\t%" }  } */

Line No.	Rev	Author	Line
1	326	jeremybenn	`/* { dg-do compile } */`
2			`/* { dg-options "-O -mcpu=ultrasparc -mvis" } */`
3			`typedef int vec32 __attribute__((vector_size(4)));`
4
5			`extern vec32 foo1(void);`
6			`extern vec32 foo2(void);`
7
8			`vec32 bar(void)`
9			`{`
10			`return foo1 () + foo2 ();`
11			`}`
12
13			`/* { dg-final { scan-assembler "fpadd32s\t%" } } */`

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[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [sparc/] [fpadd32s.c] - Blame information for rev 326