OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [libgcc/] [config/] [lm32/] [t-lm32] - Blame information for rev 272

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 272 jeremybenn 
LIB2ADD += \
2 
        $(srcdir)/config/lm32/_ashlsi3.S \
3 
        $(srcdir)/config/lm32/_ashrsi3.S \
4 
        $(srcdir)/config/lm32/_lshrsi3.S \
5 
        $(srcdir)/config/lm32/_mulsi3.c \
6 
        $(srcdir)/config/lm32/_udivmodsi4.c \
7 
        $(srcdir)/config/lm32/_divsi3.c \
8 
        $(srcdir)/config/lm32/_modsi3.c \
9 
        $(srcdir)/config/lm32/_udivsi3.c \
10 
        $(srcdir)/config/lm32/_umodsi3.c

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.