OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [gdb/] [amd64-tdep.c] - Blame information for rev 294

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
/* Target-dependent code for AMD64.
2
 
3
   Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4
   Free Software Foundation, Inc.
5
 
6
   Contributed by Jiri Smid, SuSE Labs.
7
 
8
   This file is part of GDB.
9
 
10
   This program is free software; you can redistribute it and/or modify
11
   it under the terms of the GNU General Public License as published by
12
   the Free Software Foundation; either version 3 of the License, or
13
   (at your option) any later version.
14
 
15
   This program is distributed in the hope that it will be useful,
16
   but WITHOUT ANY WARRANTY; without even the implied warranty of
17
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18
   GNU General Public License for more details.
19
 
20
   You should have received a copy of the GNU General Public License
21
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
22
 
23
#include "defs.h"
24
#include "arch-utils.h"
25
#include "block.h"
26
#include "dummy-frame.h"
27
#include "frame.h"
28
#include "frame-base.h"
29
#include "frame-unwind.h"
30
#include "inferior.h"
31
#include "gdbcmd.h"
32
#include "gdbcore.h"
33
#include "objfiles.h"
34
#include "regcache.h"
35
#include "regset.h"
36
#include "symfile.h"
37
 
38
#include "gdb_assert.h"
39
 
40
#include "amd64-tdep.h"
41
#include "i387-tdep.h"
42
 
43
/* Note that the AMD64 architecture was previously known as x86-64.
44
   The latter is (forever) engraved into the canonical system name as
45
   returned by config.guess, and used as the name for the AMD64 port
46
   of GNU/Linux.  The BSD's have renamed their ports to amd64; they
47
   don't like to shout.  For GDB we prefer the amd64_-prefix over the
48
   x86_64_-prefix since it's so much easier to type.  */
49
 
50
/* Register information.  */
51
 
52
static const char *amd64_register_names[] =
53
{
54
  "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
55
 
56
  /* %r8 is indeed register number 8.  */
57
  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
58
  "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
59
 
60
  /* %st0 is register number 24.  */
61
  "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
62
  "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
63
 
64
  /* %xmm0 is register number 40.  */
65
  "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
66
  "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
67
  "mxcsr",
68
};
69
 
70
/* Total number of registers.  */
71
#define AMD64_NUM_REGS  ARRAY_SIZE (amd64_register_names)
72
 
73
/* Return the name of register REGNUM.  */
74
 
75
const char *
76
amd64_register_name (struct gdbarch *gdbarch, int regnum)
77
{
78
  if (regnum >= 0 && regnum < AMD64_NUM_REGS)
79
    return amd64_register_names[regnum];
80
 
81
  return NULL;
82
}
83
 
84
/* Return the GDB type object for the "standard" data type of data in
85
   register REGNUM. */
86
 
87
struct type *
88
amd64_register_type (struct gdbarch *gdbarch, int regnum)
89
{
90
  if (regnum >= AMD64_RAX_REGNUM && regnum <= AMD64_RDI_REGNUM)
91
    return builtin_type_int64;
92
  if (regnum == AMD64_RBP_REGNUM || regnum == AMD64_RSP_REGNUM)
93
    return builtin_type_void_data_ptr;
94
  if (regnum >= AMD64_R8_REGNUM && regnum <= AMD64_R15_REGNUM)
95
    return builtin_type_int64;
96
  if (regnum == AMD64_RIP_REGNUM)
97
    return builtin_type_void_func_ptr;
98
  if (regnum == AMD64_EFLAGS_REGNUM)
99
    return i386_eflags_type;
100
  if (regnum >= AMD64_CS_REGNUM && regnum <= AMD64_GS_REGNUM)
101
    return builtin_type_int32;
102
  if (regnum >= AMD64_ST0_REGNUM && regnum <= AMD64_ST0_REGNUM + 7)
103
    return builtin_type_i387_ext;
104
  if (regnum >= AMD64_FCTRL_REGNUM && regnum <= AMD64_FCTRL_REGNUM + 7)
105
    return builtin_type_int32;
106
  if (regnum >= AMD64_XMM0_REGNUM && regnum <= AMD64_XMM0_REGNUM + 15)
107
    return i386_sse_type (gdbarch);
108
  if (regnum == AMD64_MXCSR_REGNUM)
109
    return i386_mxcsr_type;
110
 
111
  internal_error (__FILE__, __LINE__, _("invalid regnum"));
112
}
113
 
114
/* DWARF Register Number Mapping as defined in the System V psABI,
115
   section 3.6.  */
116
 
117
static int amd64_dwarf_regmap[] =
118
{
119
  /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI.  */
120
  AMD64_RAX_REGNUM, AMD64_RDX_REGNUM,
121
  AMD64_RCX_REGNUM, AMD64_RBX_REGNUM,
122
  AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
123
 
124
  /* Frame Pointer Register RBP.  */
125
  AMD64_RBP_REGNUM,
126
 
127
  /* Stack Pointer Register RSP.  */
128
  AMD64_RSP_REGNUM,
129
 
130
  /* Extended Integer Registers 8 - 15.  */
131
  8, 9, 10, 11, 12, 13, 14, 15,
132
 
133
  /* Return Address RA.  Mapped to RIP.  */
134
  AMD64_RIP_REGNUM,
135
 
136
  /* SSE Registers 0 - 7.  */
137
  AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
138
  AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
139
  AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
140
  AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
141
 
142
  /* Extended SSE Registers 8 - 15.  */
143
  AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9,
144
  AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11,
145
  AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13,
146
  AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15,
147
 
148
  /* Floating Point Registers 0-7.  */
149
  AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1,
150
  AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3,
151
  AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5,
152
  AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7,
153
 
154
  /* Control and Status Flags Register.  */
155
  AMD64_EFLAGS_REGNUM,
156
 
157
  /* Selector Registers.  */
158
  AMD64_ES_REGNUM,
159
  AMD64_CS_REGNUM,
160
  AMD64_SS_REGNUM,
161
  AMD64_DS_REGNUM,
162
  AMD64_FS_REGNUM,
163
  AMD64_GS_REGNUM,
164
  -1,
165
  -1,
166
 
167
  /* Segment Base Address Registers.  */
168
  -1,
169
  -1,
170
  -1,
171
  -1,
172
 
173
  /* Special Selector Registers.  */
174
  -1,
175
  -1,
176
 
177
  /* Floating Point Control Registers.  */
178
  AMD64_MXCSR_REGNUM,
179
  AMD64_FCTRL_REGNUM,
180
  AMD64_FSTAT_REGNUM
181
};
182
 
183
static const int amd64_dwarf_regmap_len =
184
  (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0]));
185
 
186
/* Convert DWARF register number REG to the appropriate register
187
   number used by GDB.  */
188
 
189
static int
190
amd64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
191
{
192
  int regnum = -1;
193
 
194
  if (reg >= 0 && reg < amd64_dwarf_regmap_len)
195
    regnum = amd64_dwarf_regmap[reg];
196
 
197
  if (regnum == -1)
198
    warning (_("Unmapped DWARF Register #%d encountered."), reg);
199
 
200
  return regnum;
201
}
202
 
203
 
204
 
205
/* Register classes as defined in the psABI.  */
206
 
207
enum amd64_reg_class
208
{
209
  AMD64_INTEGER,
210
  AMD64_SSE,
211
  AMD64_SSEUP,
212
  AMD64_X87,
213
  AMD64_X87UP,
214
  AMD64_COMPLEX_X87,
215
  AMD64_NO_CLASS,
216
  AMD64_MEMORY
217
};
218
 
219
/* Return the union class of CLASS1 and CLASS2.  See the psABI for
220
   details.  */
221
 
222
static enum amd64_reg_class
223
amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2)
224
{
225
  /* Rule (a): If both classes are equal, this is the resulting class.  */
226
  if (class1 == class2)
227
    return class1;
228
 
229
  /* Rule (b): If one of the classes is NO_CLASS, the resulting class
230
     is the other class.  */
231
  if (class1 == AMD64_NO_CLASS)
232
    return class2;
233
  if (class2 == AMD64_NO_CLASS)
234
    return class1;
235
 
236
  /* Rule (c): If one of the classes is MEMORY, the result is MEMORY.  */
237
  if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY)
238
    return AMD64_MEMORY;
239
 
240
  /* Rule (d): If one of the classes is INTEGER, the result is INTEGER.  */
241
  if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER)
242
    return AMD64_INTEGER;
243
 
244
  /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
245
     MEMORY is used as class.  */
246
  if (class1 == AMD64_X87 || class1 == AMD64_X87UP
247
      || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87
248
      || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87)
249
    return AMD64_MEMORY;
250
 
251
  /* Rule (f): Otherwise class SSE is used.  */
252
  return AMD64_SSE;
253
}
254
 
255
static void amd64_classify (struct type *type, enum amd64_reg_class class[2]);
256
 
257
/* Return non-zero if TYPE is a non-POD structure or union type.  */
258
 
259
static int
260
amd64_non_pod_p (struct type *type)
261
{
262
  /* ??? A class with a base class certainly isn't POD, but does this
263
     catch all non-POD structure types?  */
264
  if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0)
265
    return 1;
266
 
267
  return 0;
268
}
269
 
270
/* Classify TYPE according to the rules for aggregate (structures and
271
   arrays) and union types, and store the result in CLASS.  */
272
 
273
static void
274
amd64_classify_aggregate (struct type *type, enum amd64_reg_class class[2])
275
{
276
  int len = TYPE_LENGTH (type);
277
 
278
  /* 1. If the size of an object is larger than two eightbytes, or in
279
        C++, is a non-POD structure or union type, or contains
280
        unaligned fields, it has class memory.  */
281
  if (len > 16 || amd64_non_pod_p (type))
282
    {
283
      class[0] = class[1] = AMD64_MEMORY;
284
      return;
285
    }
286
 
287
  /* 2. Both eightbytes get initialized to class NO_CLASS.  */
288
  class[0] = class[1] = AMD64_NO_CLASS;
289
 
290
  /* 3. Each field of an object is classified recursively so that
291
        always two fields are considered. The resulting class is
292
        calculated according to the classes of the fields in the
293
        eightbyte: */
294
 
295
  if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
296
    {
297
      struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type));
298
 
299
      /* All fields in an array have the same type.  */
300
      amd64_classify (subtype, class);
301
      if (len > 8 && class[1] == AMD64_NO_CLASS)
302
        class[1] = class[0];
303
    }
304
  else
305
    {
306
      int i;
307
 
308
      /* Structure or union.  */
309
      gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT
310
                  || TYPE_CODE (type) == TYPE_CODE_UNION);
311
 
312
      for (i = 0; i < TYPE_NFIELDS (type); i++)
313
        {
314
          struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i));
315
          int pos = TYPE_FIELD_BITPOS (type, i) / 64;
316
          enum amd64_reg_class subclass[2];
317
 
318
          /* Ignore static fields.  */
319
          if (TYPE_FIELD_STATIC (type, i))
320
            continue;
321
 
322
          gdb_assert (pos == 0 || pos == 1);
323
 
324
          amd64_classify (subtype, subclass);
325
          class[pos] = amd64_merge_classes (class[pos], subclass[0]);
326
          if (pos == 0)
327
            class[1] = amd64_merge_classes (class[1], subclass[1]);
328
        }
329
    }
330
 
331
  /* 4. Then a post merger cleanup is done:  */
332
 
333
  /* Rule (a): If one of the classes is MEMORY, the whole argument is
334
     passed in memory.  */
335
  if (class[0] == AMD64_MEMORY || class[1] == AMD64_MEMORY)
336
    class[0] = class[1] = AMD64_MEMORY;
337
 
338
  /* Rule (b): If SSEUP is not preceeded by SSE, it is converted to
339
     SSE.  */
340
  if (class[0] == AMD64_SSEUP)
341
    class[0] = AMD64_SSE;
342
  if (class[1] == AMD64_SSEUP && class[0] != AMD64_SSE)
343
    class[1] = AMD64_SSE;
344
}
345
 
346
/* Classify TYPE, and store the result in CLASS.  */
347
 
348
static void
349
amd64_classify (struct type *type, enum amd64_reg_class class[2])
350
{
351
  enum type_code code = TYPE_CODE (type);
352
  int len = TYPE_LENGTH (type);
353
 
354
  class[0] = class[1] = AMD64_NO_CLASS;
355
 
356
  /* Arguments of types (signed and unsigned) _Bool, char, short, int,
357
     long, long long, and pointers are in the INTEGER class.  Similarly,
358
     range types, used by languages such as Ada, are also in the INTEGER
359
     class.  */
360
  if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM
361
       || code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE
362
       || code == TYPE_CODE_CHAR
363
       || code == TYPE_CODE_PTR || code == TYPE_CODE_REF)
364
      && (len == 1 || len == 2 || len == 4 || len == 8))
365
    class[0] = AMD64_INTEGER;
366
 
367
  /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64
368
     are in class SSE.  */
369
  else if ((code == TYPE_CODE_FLT || code == TYPE_CODE_DECFLOAT)
370
           && (len == 4 || len == 8))
371
    /* FIXME: __m64 .  */
372
    class[0] = AMD64_SSE;
373
 
374
  /* Arguments of types __float128, _Decimal128 and __m128 are split into
375
     two halves.  The least significant ones belong to class SSE, the most
376
     significant one to class SSEUP.  */
377
  else if (code == TYPE_CODE_DECFLOAT && len == 16)
378
    /* FIXME: __float128, __m128.  */
379
    class[0] = AMD64_SSE, class[1] = AMD64_SSEUP;
380
 
381
  /* The 64-bit mantissa of arguments of type long double belongs to
382
     class X87, the 16-bit exponent plus 6 bytes of padding belongs to
383
     class X87UP.  */
384
  else if (code == TYPE_CODE_FLT && len == 16)
385
    /* Class X87 and X87UP.  */
386
    class[0] = AMD64_X87, class[1] = AMD64_X87UP;
387
 
388
  /* Aggregates.  */
389
  else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT
390
           || code == TYPE_CODE_UNION)
391
    amd64_classify_aggregate (type, class);
392
}
393
 
394
static enum return_value_convention
395
amd64_return_value (struct gdbarch *gdbarch, struct type *type,
396
                    struct regcache *regcache,
397
                    gdb_byte *readbuf, const gdb_byte *writebuf)
398
{
399
  enum amd64_reg_class class[2];
400
  int len = TYPE_LENGTH (type);
401
  static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM };
402
  static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM };
403
  int integer_reg = 0;
404
  int sse_reg = 0;
405
  int i;
406
 
407
  gdb_assert (!(readbuf && writebuf));
408
 
409
  /* 1. Classify the return type with the classification algorithm.  */
410
  amd64_classify (type, class);
411
 
412
  /* 2. If the type has class MEMORY, then the caller provides space
413
     for the return value and passes the address of this storage in
414
     %rdi as if it were the first argument to the function. In effect,
415
     this address becomes a hidden first argument.
416
 
417
     On return %rax will contain the address that has been passed in
418
     by the caller in %rdi.  */
419
  if (class[0] == AMD64_MEMORY)
420
    {
421
      /* As indicated by the comment above, the ABI guarantees that we
422
         can always find the return value just after the function has
423
         returned.  */
424
 
425
      if (readbuf)
426
        {
427
          ULONGEST addr;
428
 
429
          regcache_raw_read_unsigned (regcache, AMD64_RAX_REGNUM, &addr);
430
          read_memory (addr, readbuf, TYPE_LENGTH (type));
431
        }
432
 
433
      return RETURN_VALUE_ABI_RETURNS_ADDRESS;
434
    }
435
 
436
  gdb_assert (class[1] != AMD64_MEMORY);
437
  gdb_assert (len <= 16);
438
 
439
  for (i = 0; len > 0; i++, len -= 8)
440
    {
441
      int regnum = -1;
442
      int offset = 0;
443
 
444
      switch (class[i])
445
        {
446
        case AMD64_INTEGER:
447
          /* 3. If the class is INTEGER, the next available register
448
             of the sequence %rax, %rdx is used.  */
449
          regnum = integer_regnum[integer_reg++];
450
          break;
451
 
452
        case AMD64_SSE:
453
          /* 4. If the class is SSE, the next available SSE register
454
             of the sequence %xmm0, %xmm1 is used.  */
455
          regnum = sse_regnum[sse_reg++];
456
          break;
457
 
458
        case AMD64_SSEUP:
459
          /* 5. If the class is SSEUP, the eightbyte is passed in the
460
             upper half of the last used SSE register.  */
461
          gdb_assert (sse_reg > 0);
462
          regnum = sse_regnum[sse_reg - 1];
463
          offset = 8;
464
          break;
465
 
466
        case AMD64_X87:
467
          /* 6. If the class is X87, the value is returned on the X87
468
             stack in %st0 as 80-bit x87 number.  */
469
          regnum = AMD64_ST0_REGNUM;
470
          if (writebuf)
471
            i387_return_value (gdbarch, regcache);
472
          break;
473
 
474
        case AMD64_X87UP:
475
          /* 7. If the class is X87UP, the value is returned together
476
             with the previous X87 value in %st0.  */
477
          gdb_assert (i > 0 && class[0] == AMD64_X87);
478
          regnum = AMD64_ST0_REGNUM;
479
          offset = 8;
480
          len = 2;
481
          break;
482
 
483
        case AMD64_NO_CLASS:
484
          continue;
485
 
486
        default:
487
          gdb_assert (!"Unexpected register class.");
488
        }
489
 
490
      gdb_assert (regnum != -1);
491
 
492
      if (readbuf)
493
        regcache_raw_read_part (regcache, regnum, offset, min (len, 8),
494
                                readbuf + i * 8);
495
      if (writebuf)
496
        regcache_raw_write_part (regcache, regnum, offset, min (len, 8),
497
                                 writebuf + i * 8);
498
    }
499
 
500
  return RETURN_VALUE_REGISTER_CONVENTION;
501
}
502
 
503
 
504
static CORE_ADDR
505
amd64_push_arguments (struct regcache *regcache, int nargs,
506
                      struct value **args, CORE_ADDR sp, int struct_return)
507
{
508
  static int integer_regnum[] =
509
  {
510
    AMD64_RDI_REGNUM,           /* %rdi */
511
    AMD64_RSI_REGNUM,           /* %rsi */
512
    AMD64_RDX_REGNUM,           /* %rdx */
513
    AMD64_RCX_REGNUM,           /* %rcx */
514
    8,                          /* %r8 */
515
    9                           /* %r9 */
516
  };
517
  static int sse_regnum[] =
518
  {
519
    /* %xmm0 ... %xmm7 */
520
    AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
521
    AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
522
    AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
523
    AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
524
  };
525
  struct value **stack_args = alloca (nargs * sizeof (struct value *));
526
  int num_stack_args = 0;
527
  int num_elements = 0;
528
  int element = 0;
529
  int integer_reg = 0;
530
  int sse_reg = 0;
531
  int i;
532
 
533
  /* Reserve a register for the "hidden" argument.  */
534
  if (struct_return)
535
    integer_reg++;
536
 
537
  for (i = 0; i < nargs; i++)
538
    {
539
      struct type *type = value_type (args[i]);
540
      int len = TYPE_LENGTH (type);
541
      enum amd64_reg_class class[2];
542
      int needed_integer_regs = 0;
543
      int needed_sse_regs = 0;
544
      int j;
545
 
546
      /* Classify argument.  */
547
      amd64_classify (type, class);
548
 
549
      /* Calculate the number of integer and SSE registers needed for
550
         this argument.  */
551
      for (j = 0; j < 2; j++)
552
        {
553
          if (class[j] == AMD64_INTEGER)
554
            needed_integer_regs++;
555
          else if (class[j] == AMD64_SSE)
556
            needed_sse_regs++;
557
        }
558
 
559
      /* Check whether enough registers are available, and if the
560
         argument should be passed in registers at all.  */
561
      if (integer_reg + needed_integer_regs > ARRAY_SIZE (integer_regnum)
562
          || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum)
563
          || (needed_integer_regs == 0 && needed_sse_regs == 0))
564
        {
565
          /* The argument will be passed on the stack.  */
566
          num_elements += ((len + 7) / 8);
567
          stack_args[num_stack_args++] = args[i];
568
        }
569
      else
570
        {
571
          /* The argument will be passed in registers.  */
572
          const gdb_byte *valbuf = value_contents (args[i]);
573
          gdb_byte buf[8];
574
 
575
          gdb_assert (len <= 16);
576
 
577
          for (j = 0; len > 0; j++, len -= 8)
578
            {
579
              int regnum = -1;
580
              int offset = 0;
581
 
582
              switch (class[j])
583
                {
584
                case AMD64_INTEGER:
585
                  regnum = integer_regnum[integer_reg++];
586
                  break;
587
 
588
                case AMD64_SSE:
589
                  regnum = sse_regnum[sse_reg++];
590
                  break;
591
 
592
                case AMD64_SSEUP:
593
                  gdb_assert (sse_reg > 0);
594
                  regnum = sse_regnum[sse_reg - 1];
595
                  offset = 8;
596
                  break;
597
 
598
                default:
599
                  gdb_assert (!"Unexpected register class.");
600
                }
601
 
602
              gdb_assert (regnum != -1);
603
              memset (buf, 0, sizeof buf);
604
              memcpy (buf, valbuf + j * 8, min (len, 8));
605
              regcache_raw_write_part (regcache, regnum, offset, 8, buf);
606
            }
607
        }
608
    }
609
 
610
  /* Allocate space for the arguments on the stack.  */
611
  sp -= num_elements * 8;
612
 
613
  /* The psABI says that "The end of the input argument area shall be
614
     aligned on a 16 byte boundary."  */
615
  sp &= ~0xf;
616
 
617
  /* Write out the arguments to the stack.  */
618
  for (i = 0; i < num_stack_args; i++)
619
    {
620
      struct type *type = value_type (stack_args[i]);
621
      const gdb_byte *valbuf = value_contents (stack_args[i]);
622
      int len = TYPE_LENGTH (type);
623
 
624
      write_memory (sp + element * 8, valbuf, len);
625
      element += ((len + 7) / 8);
626
    }
627
 
628
  /* The psABI says that "For calls that may call functions that use
629
     varargs or stdargs (prototype-less calls or calls to functions
630
     containing ellipsis (...) in the declaration) %al is used as
631
     hidden argument to specify the number of SSE registers used.  */
632
  regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg);
633
  return sp;
634
}
635
 
636
static CORE_ADDR
637
amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
638
                       struct regcache *regcache, CORE_ADDR bp_addr,
639
                       int nargs, struct value **args,  CORE_ADDR sp,
640
                       int struct_return, CORE_ADDR struct_addr)
641
{
642
  gdb_byte buf[8];
643
 
644
  /* Pass arguments.  */
645
  sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return);
646
 
647
  /* Pass "hidden" argument".  */
648
  if (struct_return)
649
    {
650
      store_unsigned_integer (buf, 8, struct_addr);
651
      regcache_cooked_write (regcache, AMD64_RDI_REGNUM, buf);
652
    }
653
 
654
  /* Store return address.  */
655
  sp -= 8;
656
  store_unsigned_integer (buf, 8, bp_addr);
657
  write_memory (sp, buf, 8);
658
 
659
  /* Finally, update the stack pointer...  */
660
  store_unsigned_integer (buf, 8, sp);
661
  regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf);
662
 
663
  /* ...and fake a frame pointer.  */
664
  regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf);
665
 
666
  return sp + 16;
667
}
668
 
669
 
670
/* The maximum number of saved registers.  This should include %rip.  */
671
#define AMD64_NUM_SAVED_REGS    AMD64_NUM_GREGS
672
 
673
struct amd64_frame_cache
674
{
675
  /* Base address.  */
676
  CORE_ADDR base;
677
  CORE_ADDR sp_offset;
678
  CORE_ADDR pc;
679
 
680
  /* Saved registers.  */
681
  CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS];
682
  CORE_ADDR saved_sp;
683
 
684
  /* Do we have a frame?  */
685
  int frameless_p;
686
};
687
 
688
/* Initialize a frame cache.  */
689
 
690
static void
691
amd64_init_frame_cache (struct amd64_frame_cache *cache)
692
{
693
  int i;
694
 
695
  /* Base address.  */
696
  cache->base = 0;
697
  cache->sp_offset = -8;
698
  cache->pc = 0;
699
 
700
  /* Saved registers.  We initialize these to -1 since zero is a valid
701
     offset (that's where %rbp is supposed to be stored).  */
702
  for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
703
    cache->saved_regs[i] = -1;
704
  cache->saved_sp = 0;
705
 
706
  /* Frameless until proven otherwise.  */
707
  cache->frameless_p = 1;
708
}
709
 
710
/* Allocate and initialize a frame cache.  */
711
 
712
static struct amd64_frame_cache *
713
amd64_alloc_frame_cache (void)
714
{
715
  struct amd64_frame_cache *cache;
716
 
717
  cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache);
718
  amd64_init_frame_cache (cache);
719
  return cache;
720
}
721
 
722
/* Do a limited analysis of the prologue at PC and update CACHE
723
   accordingly.  Bail out early if CURRENT_PC is reached.  Return the
724
   address where the analysis stopped.
725
 
726
   We will handle only functions beginning with:
727
 
728
      pushq %rbp        0x55
729
      movq %rsp, %rbp   0x48 0x89 0xe5
730
 
731
   Any function that doesn't start with this sequence will be assumed
732
   to have no prologue and thus no valid frame pointer in %rbp.  */
733
 
734
static CORE_ADDR
735
amd64_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
736
                        struct amd64_frame_cache *cache)
737
{
738
  static gdb_byte proto[3] = { 0x48, 0x89, 0xe5 }; /* movq %rsp, %rbp */
739
  gdb_byte buf[3];
740
  gdb_byte op;
741
 
742
  if (current_pc <= pc)
743
    return current_pc;
744
 
745
  op = read_memory_unsigned_integer (pc, 1);
746
 
747
  if (op == 0x55)               /* pushq %rbp */
748
    {
749
      /* Take into account that we've executed the `pushq %rbp' that
750
         starts this instruction sequence.  */
751
      cache->saved_regs[AMD64_RBP_REGNUM] = 0;
752
      cache->sp_offset += 8;
753
 
754
      /* If that's all, return now.  */
755
      if (current_pc <= pc + 1)
756
        return current_pc;
757
 
758
      /* Check for `movq %rsp, %rbp'.  */
759
      read_memory (pc + 1, buf, 3);
760
      if (memcmp (buf, proto, 3) != 0)
761
        return pc + 1;
762
 
763
      /* OK, we actually have a frame.  */
764
      cache->frameless_p = 0;
765
      return pc + 4;
766
    }
767
 
768
  return pc;
769
}
770
 
771
/* Return PC of first real instruction.  */
772
 
773
static CORE_ADDR
774
amd64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
775
{
776
  struct amd64_frame_cache cache;
777
  CORE_ADDR pc;
778
 
779
  amd64_init_frame_cache (&cache);
780
  pc = amd64_analyze_prologue (start_pc, 0xffffffffffffffffLL, &cache);
781
  if (cache.frameless_p)
782
    return start_pc;
783
 
784
  return pc;
785
}
786
 
787
 
788
/* Normal frames.  */
789
 
790
static struct amd64_frame_cache *
791
amd64_frame_cache (struct frame_info *next_frame, void **this_cache)
792
{
793
  struct amd64_frame_cache *cache;
794
  gdb_byte buf[8];
795
  int i;
796
 
797
  if (*this_cache)
798
    return *this_cache;
799
 
800
  cache = amd64_alloc_frame_cache ();
801
  *this_cache = cache;
802
 
803
  cache->pc = frame_func_unwind (next_frame, NORMAL_FRAME);
804
  if (cache->pc != 0)
805
    amd64_analyze_prologue (cache->pc, frame_pc_unwind (next_frame), cache);
806
 
807
  if (cache->frameless_p)
808
    {
809
      /* We didn't find a valid frame.  If we're at the start of a
810
         function, or somewhere half-way its prologue, the function's
811
         frame probably hasn't been fully setup yet.  Try to
812
         reconstruct the base address for the stack frame by looking
813
         at the stack pointer.  For truly "frameless" functions this
814
         might work too.  */
815
 
816
      frame_unwind_register (next_frame, AMD64_RSP_REGNUM, buf);
817
      cache->base = extract_unsigned_integer (buf, 8) + cache->sp_offset;
818
    }
819
  else
820
    {
821
      frame_unwind_register (next_frame, AMD64_RBP_REGNUM, buf);
822
      cache->base = extract_unsigned_integer (buf, 8);
823
    }
824
 
825
  /* Now that we have the base address for the stack frame we can
826
     calculate the value of %rsp in the calling frame.  */
827
  cache->saved_sp = cache->base + 16;
828
 
829
  /* For normal frames, %rip is stored at 8(%rbp).  If we don't have a
830
     frame we find it at the same offset from the reconstructed base
831
     address.  */
832
  cache->saved_regs[AMD64_RIP_REGNUM] = 8;
833
 
834
  /* Adjust all the saved registers such that they contain addresses
835
     instead of offsets.  */
836
  for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
837
    if (cache->saved_regs[i] != -1)
838
      cache->saved_regs[i] += cache->base;
839
 
840
  return cache;
841
}
842
 
843
static void
844
amd64_frame_this_id (struct frame_info *next_frame, void **this_cache,
845
                     struct frame_id *this_id)
846
{
847
  struct amd64_frame_cache *cache =
848
    amd64_frame_cache (next_frame, this_cache);
849
 
850
  /* This marks the outermost frame.  */
851
  if (cache->base == 0)
852
    return;
853
 
854
  (*this_id) = frame_id_build (cache->base + 16, cache->pc);
855
}
856
 
857
static void
858
amd64_frame_prev_register (struct frame_info *next_frame, void **this_cache,
859
                           int regnum, int *optimizedp,
860
                           enum lval_type *lvalp, CORE_ADDR *addrp,
861
                           int *realnump, gdb_byte *valuep)
862
{
863
  struct gdbarch *gdbarch = get_frame_arch (next_frame);
864
  struct amd64_frame_cache *cache =
865
    amd64_frame_cache (next_frame, this_cache);
866
 
867
  gdb_assert (regnum >= 0);
868
 
869
  if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
870
    {
871
      *optimizedp = 0;
872
      *lvalp = not_lval;
873
      *addrp = 0;
874
      *realnump = -1;
875
      if (valuep)
876
        {
877
          /* Store the value.  */
878
          store_unsigned_integer (valuep, 8, cache->saved_sp);
879
        }
880
      return;
881
    }
882
 
883
  if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
884
    {
885
      *optimizedp = 0;
886
      *lvalp = lval_memory;
887
      *addrp = cache->saved_regs[regnum];
888
      *realnump = -1;
889
      if (valuep)
890
        {
891
          /* Read the value in from memory.  */
892
          read_memory (*addrp, valuep,
893
                       register_size (gdbarch, regnum));
894
        }
895
      return;
896
    }
897
 
898
  *optimizedp = 0;
899
  *lvalp = lval_register;
900
  *addrp = 0;
901
  *realnump = regnum;
902
  if (valuep)
903
    frame_unwind_register (next_frame, (*realnump), valuep);
904
}
905
 
906
static const struct frame_unwind amd64_frame_unwind =
907
{
908
  NORMAL_FRAME,
909
  amd64_frame_this_id,
910
  amd64_frame_prev_register
911
};
912
 
913
static const struct frame_unwind *
914
amd64_frame_sniffer (struct frame_info *next_frame)
915
{
916
  return &amd64_frame_unwind;
917
}
918
 
919
 
920
/* Signal trampolines.  */
921
 
922
/* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
923
   64-bit variants.  This would require using identical frame caches
924
   on both platforms.  */
925
 
926
static struct amd64_frame_cache *
927
amd64_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache)
928
{
929
  struct amd64_frame_cache *cache;
930
  struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (next_frame));
931
  CORE_ADDR addr;
932
  gdb_byte buf[8];
933
  int i;
934
 
935
  if (*this_cache)
936
    return *this_cache;
937
 
938
  cache = amd64_alloc_frame_cache ();
939
 
940
  frame_unwind_register (next_frame, AMD64_RSP_REGNUM, buf);
941
  cache->base = extract_unsigned_integer (buf, 8) - 8;
942
 
943
  addr = tdep->sigcontext_addr (next_frame);
944
  gdb_assert (tdep->sc_reg_offset);
945
  gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS);
946
  for (i = 0; i < tdep->sc_num_regs; i++)
947
    if (tdep->sc_reg_offset[i] != -1)
948
      cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
949
 
950
  *this_cache = cache;
951
  return cache;
952
}
953
 
954
static void
955
amd64_sigtramp_frame_this_id (struct frame_info *next_frame,
956
                              void **this_cache, struct frame_id *this_id)
957
{
958
  struct amd64_frame_cache *cache =
959
    amd64_sigtramp_frame_cache (next_frame, this_cache);
960
 
961
  (*this_id) = frame_id_build (cache->base + 16, frame_pc_unwind (next_frame));
962
}
963
 
964
static void
965
amd64_sigtramp_frame_prev_register (struct frame_info *next_frame,
966
                                    void **this_cache,
967
                                    int regnum, int *optimizedp,
968
                                    enum lval_type *lvalp, CORE_ADDR *addrp,
969
                                    int *realnump, gdb_byte *valuep)
970
{
971
  /* Make sure we've initialized the cache.  */
972
  amd64_sigtramp_frame_cache (next_frame, this_cache);
973
 
974
  amd64_frame_prev_register (next_frame, this_cache, regnum,
975
                             optimizedp, lvalp, addrp, realnump, valuep);
976
}
977
 
978
static const struct frame_unwind amd64_sigtramp_frame_unwind =
979
{
980
  SIGTRAMP_FRAME,
981
  amd64_sigtramp_frame_this_id,
982
  amd64_sigtramp_frame_prev_register
983
};
984
 
985
static const struct frame_unwind *
986
amd64_sigtramp_frame_sniffer (struct frame_info *next_frame)
987
{
988
  struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (next_frame));
989
 
990
  /* We shouldn't even bother if we don't have a sigcontext_addr
991
     handler.  */
992
  if (tdep->sigcontext_addr == NULL)
993
    return NULL;
994
 
995
  if (tdep->sigtramp_p != NULL)
996
    {
997
      if (tdep->sigtramp_p (next_frame))
998
        return &amd64_sigtramp_frame_unwind;
999
    }
1000
 
1001
  if (tdep->sigtramp_start != 0)
1002
    {
1003
      CORE_ADDR pc = frame_pc_unwind (next_frame);
1004
 
1005
      gdb_assert (tdep->sigtramp_end != 0);
1006
      if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
1007
        return &amd64_sigtramp_frame_unwind;
1008
    }
1009
 
1010
  return NULL;
1011
}
1012
 
1013
 
1014
static CORE_ADDR
1015
amd64_frame_base_address (struct frame_info *next_frame, void **this_cache)
1016
{
1017
  struct amd64_frame_cache *cache =
1018
    amd64_frame_cache (next_frame, this_cache);
1019
 
1020
  return cache->base;
1021
}
1022
 
1023
static const struct frame_base amd64_frame_base =
1024
{
1025
  &amd64_frame_unwind,
1026
  amd64_frame_base_address,
1027
  amd64_frame_base_address,
1028
  amd64_frame_base_address
1029
};
1030
 
1031
static struct frame_id
1032
amd64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1033
{
1034
  gdb_byte buf[8];
1035
  CORE_ADDR fp;
1036
 
1037
  frame_unwind_register (next_frame, AMD64_RBP_REGNUM, buf);
1038
  fp = extract_unsigned_integer (buf, 8);
1039
 
1040
  return frame_id_build (fp + 16, frame_pc_unwind (next_frame));
1041
}
1042
 
1043
/* 16 byte align the SP per frame requirements.  */
1044
 
1045
static CORE_ADDR
1046
amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1047
{
1048
  return sp & -(CORE_ADDR)16;
1049
}
1050
 
1051
 
1052
/* Supply register REGNUM from the buffer specified by FPREGS and LEN
1053
   in the floating-point register set REGSET to register cache
1054
   REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */
1055
 
1056
static void
1057
amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache,
1058
                       int regnum, const void *fpregs, size_t len)
1059
{
1060
  const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
1061
 
1062
  gdb_assert (len == tdep->sizeof_fpregset);
1063
  amd64_supply_fxsave (regcache, regnum, fpregs);
1064
}
1065
 
1066
/* Collect register REGNUM from the register cache REGCACHE and store
1067
   it in the buffer specified by FPREGS and LEN as described by the
1068
   floating-point register set REGSET.  If REGNUM is -1, do this for
1069
   all registers in REGSET.  */
1070
 
1071
static void
1072
amd64_collect_fpregset (const struct regset *regset,
1073
                        const struct regcache *regcache,
1074
                        int regnum, void *fpregs, size_t len)
1075
{
1076
  const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
1077
 
1078
  gdb_assert (len == tdep->sizeof_fpregset);
1079
  amd64_collect_fxsave (regcache, regnum, fpregs);
1080
}
1081
 
1082
/* Return the appropriate register set for the core section identified
1083
   by SECT_NAME and SECT_SIZE.  */
1084
 
1085
static const struct regset *
1086
amd64_regset_from_core_section (struct gdbarch *gdbarch,
1087
                                const char *sect_name, size_t sect_size)
1088
{
1089
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1090
 
1091
  if (strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset)
1092
    {
1093
      if (tdep->fpregset == NULL)
1094
        tdep->fpregset = regset_alloc (gdbarch, amd64_supply_fpregset,
1095
                                       amd64_collect_fpregset);
1096
 
1097
      return tdep->fpregset;
1098
    }
1099
 
1100
  return i386_regset_from_core_section (gdbarch, sect_name, sect_size);
1101
}
1102
 
1103
 
1104
void
1105
amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
1106
{
1107
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1108
 
1109
  /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
1110
     floating-point registers.  */
1111
  tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE;
1112
 
1113
  /* AMD64 has an FPU and 16 SSE registers.  */
1114
  tdep->st0_regnum = AMD64_ST0_REGNUM;
1115
  tdep->num_xmm_regs = 16;
1116
 
1117
  /* This is what all the fuss is about.  */
1118
  set_gdbarch_long_bit (gdbarch, 64);
1119
  set_gdbarch_long_long_bit (gdbarch, 64);
1120
  set_gdbarch_ptr_bit (gdbarch, 64);
1121
 
1122
  /* In contrast to the i386, on AMD64 a `long double' actually takes
1123
     up 128 bits, even though it's still based on the i387 extended
1124
     floating-point format which has only 80 significant bits.  */
1125
  set_gdbarch_long_double_bit (gdbarch, 128);
1126
 
1127
  set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS);
1128
  set_gdbarch_register_name (gdbarch, amd64_register_name);
1129
  set_gdbarch_register_type (gdbarch, amd64_register_type);
1130
 
1131
  /* Register numbers of various important registers.  */
1132
  set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */
1133
  set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */
1134
  set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */
1135
  set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */
1136
 
1137
  /* The "default" register numbering scheme for AMD64 is referred to
1138
     as the "DWARF Register Number Mapping" in the System V psABI.
1139
     The preferred debugging format for all known AMD64 targets is
1140
     actually DWARF2, and GCC doesn't seem to support DWARF (that is
1141
     DWARF-1), but we provide the same mapping just in case.  This
1142
     mapping is also used for stabs, which GCC does support.  */
1143
  set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
1144
  set_gdbarch_dwarf_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
1145
  set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
1146
 
1147
  /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
1148
     be in use on any of the supported AMD64 targets.  */
1149
 
1150
  /* Call dummy code.  */
1151
  set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call);
1152
  set_gdbarch_frame_align (gdbarch, amd64_frame_align);
1153
  set_gdbarch_frame_red_zone_size (gdbarch, 128);
1154
 
1155
  set_gdbarch_convert_register_p (gdbarch, i387_convert_register_p);
1156
  set_gdbarch_register_to_value (gdbarch, i387_register_to_value);
1157
  set_gdbarch_value_to_register (gdbarch, i387_value_to_register);
1158
 
1159
  set_gdbarch_return_value (gdbarch, amd64_return_value);
1160
 
1161
  set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue);
1162
 
1163
  /* Avoid wiring in the MMX registers for now.  */
1164
  set_gdbarch_num_pseudo_regs (gdbarch, 0);
1165
  tdep->mm0_regnum = -1;
1166
 
1167
  set_gdbarch_unwind_dummy_id (gdbarch, amd64_unwind_dummy_id);
1168
 
1169
  frame_unwind_append_sniffer (gdbarch, amd64_sigtramp_frame_sniffer);
1170
  frame_unwind_append_sniffer (gdbarch, amd64_frame_sniffer);
1171
  frame_base_set_default (gdbarch, &amd64_frame_base);
1172
 
1173
  /* If we have a register mapping, enable the generic core file support.  */
1174
  if (tdep->gregset_reg_offset)
1175
    set_gdbarch_regset_from_core_section (gdbarch,
1176
                                          amd64_regset_from_core_section);
1177
}
1178
 
1179
 
1180
#define I387_ST0_REGNUM AMD64_ST0_REGNUM
1181
 
1182
/* The 64-bit FXSAVE format differs from the 32-bit format in the
1183
   sense that the instruction pointer and data pointer are simply
1184
   64-bit offsets into the code segment and the data segment instead
1185
   of a selector offset pair.  The functions below store the upper 32
1186
   bits of these pointers (instead of just the 16-bits of the segment
1187
   selector).  */
1188
 
1189
/* Fill register REGNUM in REGCACHE with the appropriate
1190
   floating-point or SSE register value from *FXSAVE.  If REGNUM is
1191
   -1, do this for all registers.  This function masks off any of the
1192
   reserved bits in *FXSAVE.  */
1193
 
1194
void
1195
amd64_supply_fxsave (struct regcache *regcache, int regnum,
1196
                      const void *fxsave)
1197
{
1198
  i387_supply_fxsave (regcache, regnum, fxsave);
1199
 
1200
  if (fxsave && gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64)
1201
    {
1202
      const gdb_byte *regs = fxsave;
1203
 
1204
      if (regnum == -1 || regnum == I387_FISEG_REGNUM)
1205
        regcache_raw_supply (regcache, I387_FISEG_REGNUM, regs + 12);
1206
      if (regnum == -1 || regnum == I387_FOSEG_REGNUM)
1207
        regcache_raw_supply (regcache, I387_FOSEG_REGNUM, regs + 20);
1208
    }
1209
}
1210
 
1211
/* Fill register REGNUM (if it is a floating-point or SSE register) in
1212
   *FXSAVE with the value from REGCACHE.  If REGNUM is -1, do this for
1213
   all registers.  This function doesn't touch any of the reserved
1214
   bits in *FXSAVE.  */
1215
 
1216
void
1217
amd64_collect_fxsave (const struct regcache *regcache, int regnum,
1218
                      void *fxsave)
1219
{
1220
  gdb_byte *regs = fxsave;
1221
 
1222
  i387_collect_fxsave (regcache, regnum, fxsave);
1223
 
1224
  if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64)
1225
    {
1226
      if (regnum == -1 || regnum == I387_FISEG_REGNUM)
1227
        regcache_raw_collect (regcache, I387_FISEG_REGNUM, regs + 12);
1228
      if (regnum == -1 || regnum == I387_FOSEG_REGNUM)
1229
        regcache_raw_collect (regcache, I387_FOSEG_REGNUM, regs + 20);
1230
    }
1231
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.