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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [gdb/] [dcache.c] - Blame information for rev 233

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1 24 jeremybenn
/* Caching code for GDB, the GNU debugger.
2
 
3
   Copyright (C) 1992, 1993, 1995, 1996, 1998, 1999, 2000, 2001, 2003, 2007,
4
   2008 Free Software Foundation, Inc.
5
 
6
   This file is part of GDB.
7
 
8
   This program is free software; you can redistribute it and/or modify
9
   it under the terms of the GNU General Public License as published by
10
   the Free Software Foundation; either version 3 of the License, or
11
   (at your option) any later version.
12
 
13
   This program is distributed in the hope that it will be useful,
14
   but WITHOUT ANY WARRANTY; without even the implied warranty of
15
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
   GNU General Public License for more details.
17
 
18
   You should have received a copy of the GNU General Public License
19
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
20
 
21
#include "defs.h"
22
#include "dcache.h"
23
#include "gdbcmd.h"
24
#include "gdb_string.h"
25
#include "gdbcore.h"
26
#include "target.h"
27
 
28
/* The data cache could lead to incorrect results because it doesn't
29
   know about volatile variables, thus making it impossible to debug
30
   functions which use memory mapped I/O devices.  Set the nocache
31
   memory region attribute in those cases.
32
 
33
   In general the dcache speeds up performance, some speed improvement
34
   comes from the actual caching mechanism, but the major gain is in
35
   the reduction of the remote protocol overhead; instead of reading
36
   or writing a large area of memory in 4 byte requests, the cache
37
   bundles up the requests into 32 byte (actually LINE_SIZE) chunks.
38
   Reducing the overhead to an eighth of what it was.  This is very
39
   obvious when displaying a large amount of data,
40
 
41
   eg, x/200x 0
42
 
43
   caching     |   no    yes
44
   ----------------------------
45
   first time  |   4 sec  2 sec improvement due to chunking
46
   second time |   4 sec  0 sec improvement due to caching
47
 
48
   The cache structure is unusual, we keep a number of cache blocks
49
   (DCACHE_SIZE) and each one caches a LINE_SIZEed area of memory.
50
   Within each line we remember the address of the line (always a
51
   multiple of the LINE_SIZE) and a vector of bytes over the range.
52
   There's another vector which contains the state of the bytes.
53
 
54
   ENTRY_BAD means that the byte is just plain wrong, and has no
55
   correspondence with anything else (as it would when the cache is
56
   turned on, but nothing has been done to it.
57
 
58
   ENTRY_DIRTY means that the byte has some data in it which should be
59
   written out to the remote target one day, but contains correct
60
   data.
61
 
62
   ENTRY_OK means that the data is the same in the cache as it is in
63
   remote memory.
64
 
65
 
66
   The ENTRY_DIRTY state is necessary because GDB likes to write large
67
   lumps of memory in small bits.  If the caching mechanism didn't
68
   maintain the DIRTY information, then something like a two byte
69
   write would mean that the entire cache line would have to be read,
70
   the two bytes modified and then written out again.  The alternative
71
   would be to not read in the cache line in the first place, and just
72
   write the two bytes directly into target memory.  The trouble with
73
   that is that it really nails performance, because of the remote
74
   protocol overhead.  This way, all those little writes are bundled
75
   up into an entire cache line write in one go, without having to
76
   read the cache line in the first place.
77
 */
78
 
79
/* NOTE: Interaction of dcache and memory region attributes
80
 
81
   As there is no requirement that memory region attributes be aligned
82
   to or be a multiple of the dcache page size, dcache_read_line() and
83
   dcache_write_line() must break up the page by memory region.  If a
84
   chunk does not have the cache attribute set, an invalid memory type
85
   is set, etc., then the chunk is skipped.  Those chunks are handled
86
   in target_xfer_memory() (or target_xfer_memory_partial()).
87
 
88
   This doesn't occur very often.  The most common occurance is when
89
   the last bit of the .text segment and the first bit of the .data
90
   segment fall within the same dcache page with a ro/cacheable memory
91
   region defined for the .text segment and a rw/non-cacheable memory
92
   region defined for the .data segment. */
93
 
94
/* This value regulates the number of cache blocks stored.
95
   Smaller values reduce the time spent searching for a cache
96
   line, and reduce memory requirements, but increase the risk
97
   of a line not being in memory */
98
 
99
#define DCACHE_SIZE 64
100
 
101
/* This value regulates the size of a cache line.  Smaller values
102
   reduce the time taken to read a single byte, but reduce overall
103
   throughput.  */
104
 
105
#define LINE_SIZE_POWER (5)
106
#define LINE_SIZE (1 << LINE_SIZE_POWER)
107
 
108
/* Each cache block holds LINE_SIZE bytes of data
109
   starting at a multiple-of-LINE_SIZE address.  */
110
 
111
#define LINE_SIZE_MASK  ((LINE_SIZE - 1))
112
#define XFORM(x)        ((x) & LINE_SIZE_MASK)
113
#define MASK(x)         ((x) & ~LINE_SIZE_MASK)
114
 
115
 
116
#define ENTRY_BAD   0           /* data at this byte is wrong */
117
#define ENTRY_DIRTY 1           /* data at this byte needs to be written back */
118
#define ENTRY_OK    2           /* data at this byte is same as in memory */
119
 
120
 
121
struct dcache_block
122
  {
123
    struct dcache_block *p;     /* next in list */
124
    CORE_ADDR addr;             /* Address for which data is recorded.  */
125
    gdb_byte data[LINE_SIZE];   /* bytes at given address */
126
    unsigned char state[LINE_SIZE];     /* what state the data is in */
127
 
128
    /* whether anything in state is dirty - used to speed up the
129
       dirty scan. */
130
    int anydirty;
131
 
132
    int refs;
133
  };
134
 
135
 
136
/* FIXME: dcache_struct used to have a cache_has_stuff field that was
137
   used to record whether the cache had been accessed.  This was used
138
   to invalidate the cache whenever caching was (re-)enabled (if the
139
   cache was disabled and later re-enabled, it could contain stale
140
   data).  This was not needed because the cache is write through and
141
   the code that enables, disables, and deletes memory region all
142
   invalidate the cache.
143
 
144
   This is overkill, since it also invalidates cache lines from
145
   unrelated regions.  One way this could be addressed by adding a
146
   new function that takes an address and a length and invalidates
147
   only those cache lines that match. */
148
 
149
struct dcache_struct
150
  {
151
    /* free list */
152
    struct dcache_block *free_head;
153
    struct dcache_block *free_tail;
154
 
155
    /* in use list */
156
    struct dcache_block *valid_head;
157
    struct dcache_block *valid_tail;
158
 
159
    /* The cache itself. */
160
    struct dcache_block *the_cache;
161
  };
162
 
163
static struct dcache_block *dcache_hit (DCACHE *dcache, CORE_ADDR addr);
164
 
165
static int dcache_write_line (DCACHE *dcache, struct dcache_block *db);
166
 
167
static int dcache_read_line (DCACHE *dcache, struct dcache_block *db);
168
 
169
static struct dcache_block *dcache_alloc (DCACHE *dcache, CORE_ADDR addr);
170
 
171
static int dcache_writeback (DCACHE *dcache);
172
 
173
static void dcache_info (char *exp, int tty);
174
 
175
void _initialize_dcache (void);
176
 
177
static int dcache_enabled_p = 0;
178
static void
179
show_dcache_enabled_p (struct ui_file *file, int from_tty,
180
                       struct cmd_list_element *c, const char *value)
181
{
182
  fprintf_filtered (file, _("Cache use for remote targets is %s.\n"), value);
183
}
184
 
185
 
186
DCACHE *last_cache;             /* Used by info dcache */
187
 
188
 
189
/* Free all the data cache blocks, thus discarding all cached data.  */
190
 
191
void
192
dcache_invalidate (DCACHE *dcache)
193
{
194
  int i;
195
  dcache->valid_head = 0;
196
  dcache->valid_tail = 0;
197
 
198
  dcache->free_head = 0;
199
  dcache->free_tail = 0;
200
 
201
  for (i = 0; i < DCACHE_SIZE; i++)
202
    {
203
      struct dcache_block *db = dcache->the_cache + i;
204
 
205
      if (!dcache->free_head)
206
        dcache->free_head = db;
207
      else
208
        dcache->free_tail->p = db;
209
      dcache->free_tail = db;
210
      db->p = 0;
211
    }
212
 
213
  return;
214
}
215
 
216
/* If addr is present in the dcache, return the address of the block
217
   containing it. */
218
 
219
static struct dcache_block *
220
dcache_hit (DCACHE *dcache, CORE_ADDR addr)
221
{
222
  struct dcache_block *db;
223
 
224
  /* Search all cache blocks for one that is at this address.  */
225
  db = dcache->valid_head;
226
 
227
  while (db)
228
    {
229
      if (MASK (addr) == db->addr)
230
        {
231
          db->refs++;
232
          return db;
233
        }
234
      db = db->p;
235
    }
236
 
237
  return NULL;
238
}
239
 
240
/* Make sure that anything in this line which needs to
241
   be written is. */
242
 
243
static int
244
dcache_write_line (DCACHE *dcache, struct dcache_block *db)
245
{
246
  CORE_ADDR memaddr;
247
  gdb_byte *myaddr;
248
  int len;
249
  int res;
250
  int reg_len;
251
  struct mem_region *region;
252
 
253
  if (!db->anydirty)
254
    return 1;
255
 
256
  len = LINE_SIZE;
257
  memaddr = db->addr;
258
  myaddr  = db->data;
259
 
260
  while (len > 0)
261
    {
262
      int s;
263
      int e;
264
      int dirty_len;
265
 
266
      region = lookup_mem_region(memaddr);
267
      if (memaddr + len < region->hi)
268
        reg_len = len;
269
      else
270
        reg_len = region->hi - memaddr;
271
 
272
      if (!region->attrib.cache || region->attrib.mode == MEM_RO)
273
        {
274
          memaddr += reg_len;
275
          myaddr  += reg_len;
276
          len     -= reg_len;
277
          continue;
278
        }
279
 
280
      while (reg_len > 0)
281
        {
282
          s = XFORM(memaddr);
283
          while (reg_len > 0) {
284
            if (db->state[s] == ENTRY_DIRTY)
285
              break;
286
            s++;
287
            reg_len--;
288
 
289
            memaddr++;
290
            myaddr++;
291
            len--;
292
          }
293
 
294
          e = s;
295
          while (reg_len > 0) {
296
            if (db->state[e] != ENTRY_DIRTY)
297
              break;
298
            e++;
299
            reg_len--;
300
          }
301
 
302
          dirty_len = e - s;
303
          res = target_write (&current_target, TARGET_OBJECT_RAW_MEMORY,
304
                              NULL, myaddr, memaddr, dirty_len);
305
          if (res < dirty_len)
306
            return 0;
307
 
308
          memset (&db->state[XFORM(memaddr)], ENTRY_OK, res);
309
          memaddr += res;
310
          myaddr += res;
311
          len -= res;
312
        }
313
    }
314
 
315
  db->anydirty = 0;
316
  return 1;
317
}
318
 
319
/* Read cache line */
320
static int
321
dcache_read_line (DCACHE *dcache, struct dcache_block *db)
322
{
323
  CORE_ADDR memaddr;
324
  gdb_byte *myaddr;
325
  int len;
326
  int res;
327
  int reg_len;
328
  struct mem_region *region;
329
 
330
  /* If there are any dirty bytes in the line, it must be written
331
     before a new line can be read */
332
  if (db->anydirty)
333
    {
334
      if (!dcache_write_line (dcache, db))
335
        return 0;
336
    }
337
 
338
  len = LINE_SIZE;
339
  memaddr = db->addr;
340
  myaddr  = db->data;
341
 
342
  while (len > 0)
343
    {
344
      region = lookup_mem_region(memaddr);
345
      if (memaddr + len < region->hi)
346
        reg_len = len;
347
      else
348
        reg_len = region->hi - memaddr;
349
 
350
      if (!region->attrib.cache || region->attrib.mode == MEM_WO)
351
        {
352
          memaddr += reg_len;
353
          myaddr  += reg_len;
354
          len     -= reg_len;
355
          continue;
356
        }
357
 
358
      res = target_read (&current_target, TARGET_OBJECT_RAW_MEMORY,
359
                         NULL, myaddr, memaddr, reg_len);
360
      if (res < reg_len)
361
        return 0;
362
 
363
      memaddr += res;
364
      myaddr += res;
365
      len -= res;
366
    }
367
 
368
  memset (db->state, ENTRY_OK, sizeof (db->data));
369
  db->anydirty = 0;
370
 
371
  return 1;
372
}
373
 
374
/* Get a free cache block, put or keep it on the valid list,
375
   and return its address.  */
376
 
377
static struct dcache_block *
378
dcache_alloc (DCACHE *dcache, CORE_ADDR addr)
379
{
380
  struct dcache_block *db;
381
 
382
  /* Take something from the free list */
383
  db = dcache->free_head;
384
  if (db)
385
    {
386
      dcache->free_head = db->p;
387
    }
388
  else
389
    {
390
      /* Nothing left on free list, so grab one from the valid list */
391
      db = dcache->valid_head;
392
 
393
      if (!dcache_write_line (dcache, db))
394
        return NULL;
395
 
396
      dcache->valid_head = db->p;
397
    }
398
 
399
  db->addr = MASK(addr);
400
  db->refs = 0;
401
  db->anydirty = 0;
402
  memset (db->state, ENTRY_BAD, sizeof (db->data));
403
 
404
  /* append this line to end of valid list */
405
  if (!dcache->valid_head)
406
    dcache->valid_head = db;
407
  else
408
    dcache->valid_tail->p = db;
409
  dcache->valid_tail = db;
410
  db->p = 0;
411
 
412
  return db;
413
}
414
 
415
/* Writeback any dirty lines. */
416
static int
417
dcache_writeback (DCACHE *dcache)
418
{
419
  struct dcache_block *db;
420
 
421
  db = dcache->valid_head;
422
 
423
  while (db)
424
    {
425
      if (!dcache_write_line (dcache, db))
426
        return 0;
427
      db = db->p;
428
    }
429
  return 1;
430
}
431
 
432
 
433
/* Using the data cache DCACHE return the contents of the byte at
434
   address ADDR in the remote machine.
435
 
436
   Returns 0 on error. */
437
 
438
static int
439
dcache_peek_byte (DCACHE *dcache, CORE_ADDR addr, gdb_byte *ptr)
440
{
441
  struct dcache_block *db = dcache_hit (dcache, addr);
442
 
443
  if (!db)
444
    {
445
      db = dcache_alloc (dcache, addr);
446
      if (!db)
447
        return 0;
448
    }
449
 
450
  if (db->state[XFORM (addr)] == ENTRY_BAD)
451
    {
452
      if (!dcache_read_line(dcache, db))
453
         return 0;
454
    }
455
 
456
  *ptr = db->data[XFORM (addr)];
457
  return 1;
458
}
459
 
460
 
461
/* Write the byte at PTR into ADDR in the data cache.
462
   Return zero on write error.
463
 */
464
 
465
static int
466
dcache_poke_byte (DCACHE *dcache, CORE_ADDR addr, gdb_byte *ptr)
467
{
468
  struct dcache_block *db = dcache_hit (dcache, addr);
469
 
470
  if (!db)
471
    {
472
      db = dcache_alloc (dcache, addr);
473
      if (!db)
474
        return 0;
475
    }
476
 
477
  db->data[XFORM (addr)] = *ptr;
478
  db->state[XFORM (addr)] = ENTRY_DIRTY;
479
  db->anydirty = 1;
480
  return 1;
481
}
482
 
483
/* Initialize the data cache.  */
484
DCACHE *
485
dcache_init (void)
486
{
487
  int csize = sizeof (struct dcache_block) * DCACHE_SIZE;
488
  DCACHE *dcache;
489
 
490
  dcache = (DCACHE *) xmalloc (sizeof (*dcache));
491
 
492
  dcache->the_cache = (struct dcache_block *) xmalloc (csize);
493
  memset (dcache->the_cache, 0, csize);
494
 
495
  dcache_invalidate (dcache);
496
 
497
  last_cache = dcache;
498
  return dcache;
499
}
500
 
501
/* Free a data cache */
502
void
503
dcache_free (DCACHE *dcache)
504
{
505
  if (last_cache == dcache)
506
    last_cache = NULL;
507
 
508
  xfree (dcache->the_cache);
509
  xfree (dcache);
510
}
511
 
512
/* Read or write LEN bytes from inferior memory at MEMADDR, transferring
513
   to or from debugger address MYADDR.  Write to inferior if SHOULD_WRITE is
514
   nonzero.
515
 
516
   Returns length of data written or read; 0 for error.
517
 
518
   This routine is indended to be called by remote_xfer_ functions. */
519
 
520
int
521
dcache_xfer_memory (DCACHE *dcache, CORE_ADDR memaddr, gdb_byte *myaddr,
522
                    int len, int should_write)
523
{
524
  int i;
525
  int (*xfunc) (DCACHE *dcache, CORE_ADDR addr, gdb_byte *ptr);
526
  xfunc = should_write ? dcache_poke_byte : dcache_peek_byte;
527
 
528
  for (i = 0; i < len; i++)
529
    {
530
      if (!xfunc (dcache, memaddr + i, myaddr + i))
531
        return 0;
532
    }
533
 
534
  /* FIXME: There may be some benefit from moving the cache writeback
535
     to a higher layer, as it could occur after a sequence of smaller
536
     writes have been completed (as when a stack frame is constructed
537
     for an inferior function call).  Note that only moving it up one
538
     level to target_xfer_memory() (also target_xfer_memory_partial())
539
     is not sufficent, since we want to coalesce memory transfers that
540
     are "logically" connected but not actually a single call to one
541
     of the memory transfer functions. */
542
 
543
  if (should_write)
544
    dcache_writeback (dcache);
545
 
546
  return len;
547
}
548
 
549
static void
550
dcache_info (char *exp, int tty)
551
{
552
  struct dcache_block *p;
553
 
554
  printf_filtered (_("Dcache line width %d, depth %d\n"),
555
                   LINE_SIZE, DCACHE_SIZE);
556
 
557
  if (last_cache)
558
    {
559
      printf_filtered (_("Cache state:\n"));
560
 
561
      for (p = last_cache->valid_head; p; p = p->p)
562
        {
563
          int j;
564
          printf_filtered (_("Line at %s, referenced %d times\n"),
565
                           paddr (p->addr), p->refs);
566
 
567
          for (j = 0; j < LINE_SIZE; j++)
568
            printf_filtered ("%02x", p->data[j] & 0xFF);
569
          printf_filtered (("\n"));
570
 
571
          for (j = 0; j < LINE_SIZE; j++)
572
            printf_filtered ("%2x", p->state[j]);
573
          printf_filtered ("\n");
574
        }
575
    }
576
}
577
 
578
void
579
_initialize_dcache (void)
580
{
581
  add_setshow_boolean_cmd ("remotecache", class_support,
582
                           &dcache_enabled_p, _("\
583
Set cache use for remote targets."), _("\
584
Show cache use for remote targets."), _("\
585
When on, use data caching for remote targets.  For many remote targets\n\
586
this option can offer better throughput for reading target memory.\n\
587
Unfortunately, gdb does not currently know anything about volatile\n\
588
registers and thus data caching will produce incorrect results with\n\
589
volatile registers are in use.  By default, this option is off."),
590
                           NULL,
591
                           show_dcache_enabled_p,
592
                           &setlist, &showlist);
593
 
594
  add_info ("dcache", dcache_info,
595
            _("Print information on the dcache performance."));
596
 
597
}

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