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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [gdb/] [frv-tdep.c] - Blame information for rev 157

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1 24 jeremybenn
/* Target-dependent code for the Fujitsu FR-V, for GDB, the GNU Debugger.
2
 
3
   Copyright (C) 2002, 2003, 2004, 2005, 2007, 2008
4
   Free Software Foundation, Inc.
5
 
6
   This file is part of GDB.
7
 
8
   This program is free software; you can redistribute it and/or modify
9
   it under the terms of the GNU General Public License as published by
10
   the Free Software Foundation; either version 3 of the License, or
11
   (at your option) any later version.
12
 
13
   This program is distributed in the hope that it will be useful,
14
   but WITHOUT ANY WARRANTY; without even the implied warranty of
15
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
   GNU General Public License for more details.
17
 
18
   You should have received a copy of the GNU General Public License
19
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
20
 
21
#include "defs.h"
22
#include "gdb_string.h"
23
#include "inferior.h"
24
#include "gdbcore.h"
25
#include "arch-utils.h"
26
#include "regcache.h"
27
#include "frame.h"
28
#include "frame-unwind.h"
29
#include "frame-base.h"
30
#include "trad-frame.h"
31
#include "dis-asm.h"
32
#include "gdb_assert.h"
33
#include "sim-regno.h"
34
#include "gdb/sim-frv.h"
35
#include "opcodes/frv-desc.h"   /* for the H_SPR_... enums */
36
#include "symtab.h"
37
#include "elf-bfd.h"
38
#include "elf/frv.h"
39
#include "osabi.h"
40
#include "infcall.h"
41
#include "solib.h"
42
#include "frv-tdep.h"
43
 
44
extern void _initialize_frv_tdep (void);
45
 
46
struct frv_unwind_cache         /* was struct frame_extra_info */
47
  {
48
    /* The previous frame's inner-most stack address.  Used as this
49
       frame ID's stack_addr.  */
50
    CORE_ADDR prev_sp;
51
 
52
    /* The frame's base, optionally used by the high-level debug info.  */
53
    CORE_ADDR base;
54
 
55
    /* Table indicating the location of each and every register.  */
56
    struct trad_frame_saved_reg *saved_regs;
57
  };
58
 
59
/* A structure describing a particular variant of the FRV.
60
   We allocate and initialize one of these structures when we create
61
   the gdbarch object for a variant.
62
 
63
   At the moment, all the FR variants we support differ only in which
64
   registers are present; the portable code of GDB knows that
65
   registers whose names are the empty string don't exist, so the
66
   `register_names' array captures all the per-variant information we
67
   need.
68
 
69
   in the future, if we need to have per-variant maps for raw size,
70
   virtual type, etc., we should replace register_names with an array
71
   of structures, each of which gives all the necessary info for one
72
   register.  Don't stick parallel arrays in here --- that's so
73
   Fortran.  */
74
struct gdbarch_tdep
75
{
76
  /* Which ABI is in use?  */
77
  enum frv_abi frv_abi;
78
 
79
  /* How many general-purpose registers does this variant have?  */
80
  int num_gprs;
81
 
82
  /* How many floating-point registers does this variant have?  */
83
  int num_fprs;
84
 
85
  /* How many hardware watchpoints can it support?  */
86
  int num_hw_watchpoints;
87
 
88
  /* How many hardware breakpoints can it support?  */
89
  int num_hw_breakpoints;
90
 
91
  /* Register names.  */
92
  char **register_names;
93
};
94
 
95
/* Return the FR-V ABI associated with GDBARCH.  */
96
enum frv_abi
97
frv_abi (struct gdbarch *gdbarch)
98
{
99
  return gdbarch_tdep (gdbarch)->frv_abi;
100
}
101
 
102
/* Fetch the interpreter and executable loadmap addresses (for shared
103
   library support) for the FDPIC ABI.  Return 0 if successful, -1 if
104
   not.  (E.g, -1 will be returned if the ABI isn't the FDPIC ABI.)  */
105
int
106
frv_fdpic_loadmap_addresses (struct gdbarch *gdbarch, CORE_ADDR *interp_addr,
107
                             CORE_ADDR *exec_addr)
108
{
109
  if (frv_abi (gdbarch) != FRV_ABI_FDPIC)
110
    return -1;
111
  else
112
    {
113
      struct regcache *regcache = get_current_regcache ();
114
 
115
      if (interp_addr != NULL)
116
        {
117
          ULONGEST val;
118
          regcache_cooked_read_unsigned (regcache,
119
                                         fdpic_loadmap_interp_regnum, &val);
120
          *interp_addr = val;
121
        }
122
      if (exec_addr != NULL)
123
        {
124
          ULONGEST val;
125
          regcache_cooked_read_unsigned (regcache,
126
                                         fdpic_loadmap_exec_regnum, &val);
127
          *exec_addr = val;
128
        }
129
      return 0;
130
    }
131
}
132
 
133
/* Allocate a new variant structure, and set up default values for all
134
   the fields.  */
135
static struct gdbarch_tdep *
136
new_variant (void)
137
{
138
  struct gdbarch_tdep *var;
139
  int r;
140
  char buf[20];
141
 
142
  var = xmalloc (sizeof (*var));
143
  memset (var, 0, sizeof (*var));
144
 
145
  var->frv_abi = FRV_ABI_EABI;
146
  var->num_gprs = 64;
147
  var->num_fprs = 64;
148
  var->num_hw_watchpoints = 0;
149
  var->num_hw_breakpoints = 0;
150
 
151
  /* By default, don't supply any general-purpose or floating-point
152
     register names.  */
153
  var->register_names
154
    = (char **) xmalloc ((frv_num_regs + frv_num_pseudo_regs)
155
                         * sizeof (char *));
156
  for (r = 0; r < frv_num_regs + frv_num_pseudo_regs; r++)
157
    var->register_names[r] = "";
158
 
159
  /* Do, however, supply default names for the known special-purpose
160
     registers.  */
161
 
162
  var->register_names[pc_regnum] = "pc";
163
  var->register_names[lr_regnum] = "lr";
164
  var->register_names[lcr_regnum] = "lcr";
165
 
166
  var->register_names[psr_regnum] = "psr";
167
  var->register_names[ccr_regnum] = "ccr";
168
  var->register_names[cccr_regnum] = "cccr";
169
  var->register_names[tbr_regnum] = "tbr";
170
 
171
  /* Debug registers.  */
172
  var->register_names[brr_regnum] = "brr";
173
  var->register_names[dbar0_regnum] = "dbar0";
174
  var->register_names[dbar1_regnum] = "dbar1";
175
  var->register_names[dbar2_regnum] = "dbar2";
176
  var->register_names[dbar3_regnum] = "dbar3";
177
 
178
  /* iacc0 (Only found on MB93405.)  */
179
  var->register_names[iacc0h_regnum] = "iacc0h";
180
  var->register_names[iacc0l_regnum] = "iacc0l";
181
  var->register_names[iacc0_regnum] = "iacc0";
182
 
183
  /* fsr0 (Found on FR555 and FR501.)  */
184
  var->register_names[fsr0_regnum] = "fsr0";
185
 
186
  /* acc0 - acc7.  The architecture provides for the possibility of many
187
     more (up to 64 total), but we don't want to make that big of a hole
188
     in the G packet.  If we need more in the future, we'll add them
189
     elsewhere.  */
190
  for (r = acc0_regnum; r <= acc7_regnum; r++)
191
    {
192
      char *buf;
193
      buf = xstrprintf ("acc%d", r - acc0_regnum);
194
      var->register_names[r] = buf;
195
    }
196
 
197
  /* accg0 - accg7: These are one byte registers.  The remote protocol
198
     provides the raw values packed four into a slot.  accg0123 and
199
     accg4567 correspond to accg0 - accg3 and accg4-accg7 respectively.
200
     We don't provide names for accg0123 and accg4567 since the user will
201
     likely not want to see these raw values.  */
202
 
203
  for (r = accg0_regnum; r <= accg7_regnum; r++)
204
    {
205
      char *buf;
206
      buf = xstrprintf ("accg%d", r - accg0_regnum);
207
      var->register_names[r] = buf;
208
    }
209
 
210
  /* msr0 and msr1.  */
211
 
212
  var->register_names[msr0_regnum] = "msr0";
213
  var->register_names[msr1_regnum] = "msr1";
214
 
215
  /* gner and fner registers.  */
216
  var->register_names[gner0_regnum] = "gner0";
217
  var->register_names[gner1_regnum] = "gner1";
218
  var->register_names[fner0_regnum] = "fner0";
219
  var->register_names[fner1_regnum] = "fner1";
220
 
221
  return var;
222
}
223
 
224
 
225
/* Indicate that the variant VAR has NUM_GPRS general-purpose
226
   registers, and fill in the names array appropriately.  */
227
static void
228
set_variant_num_gprs (struct gdbarch_tdep *var, int num_gprs)
229
{
230
  int r;
231
 
232
  var->num_gprs = num_gprs;
233
 
234
  for (r = 0; r < num_gprs; ++r)
235
    {
236
      char buf[20];
237
 
238
      sprintf (buf, "gr%d", r);
239
      var->register_names[first_gpr_regnum + r] = xstrdup (buf);
240
    }
241
}
242
 
243
 
244
/* Indicate that the variant VAR has NUM_FPRS floating-point
245
   registers, and fill in the names array appropriately.  */
246
static void
247
set_variant_num_fprs (struct gdbarch_tdep *var, int num_fprs)
248
{
249
  int r;
250
 
251
  var->num_fprs = num_fprs;
252
 
253
  for (r = 0; r < num_fprs; ++r)
254
    {
255
      char buf[20];
256
 
257
      sprintf (buf, "fr%d", r);
258
      var->register_names[first_fpr_regnum + r] = xstrdup (buf);
259
    }
260
}
261
 
262
static void
263
set_variant_abi_fdpic (struct gdbarch_tdep *var)
264
{
265
  var->frv_abi = FRV_ABI_FDPIC;
266
  var->register_names[fdpic_loadmap_exec_regnum] = xstrdup ("loadmap_exec");
267
  var->register_names[fdpic_loadmap_interp_regnum] = xstrdup ("loadmap_interp");
268
}
269
 
270
static void
271
set_variant_scratch_registers (struct gdbarch_tdep *var)
272
{
273
  var->register_names[scr0_regnum] = xstrdup ("scr0");
274
  var->register_names[scr1_regnum] = xstrdup ("scr1");
275
  var->register_names[scr2_regnum] = xstrdup ("scr2");
276
  var->register_names[scr3_regnum] = xstrdup ("scr3");
277
}
278
 
279
static const char *
280
frv_register_name (struct gdbarch *gdbarch, int reg)
281
{
282
  if (reg < 0)
283
    return "?toosmall?";
284
  if (reg >= frv_num_regs + frv_num_pseudo_regs)
285
    return "?toolarge?";
286
 
287
  return gdbarch_tdep (gdbarch)->register_names[reg];
288
}
289
 
290
 
291
static struct type *
292
frv_register_type (struct gdbarch *gdbarch, int reg)
293
{
294
  if (reg >= first_fpr_regnum && reg <= last_fpr_regnum)
295
    return builtin_type_float;
296
  else if (reg == iacc0_regnum)
297
    return builtin_type_int64;
298
  else
299
    return builtin_type_int32;
300
}
301
 
302
static void
303
frv_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
304
                          int reg, gdb_byte *buffer)
305
{
306
  if (reg == iacc0_regnum)
307
    {
308
      regcache_raw_read (regcache, iacc0h_regnum, buffer);
309
      regcache_raw_read (regcache, iacc0l_regnum, (bfd_byte *) buffer + 4);
310
    }
311
  else if (accg0_regnum <= reg && reg <= accg7_regnum)
312
    {
313
      /* The accg raw registers have four values in each slot with the
314
         lowest register number occupying the first byte.  */
315
 
316
      int raw_regnum = accg0123_regnum + (reg - accg0_regnum) / 4;
317
      int byte_num = (reg - accg0_regnum) % 4;
318
      bfd_byte buf[4];
319
 
320
      regcache_raw_read (regcache, raw_regnum, buf);
321
      memset (buffer, 0, 4);
322
      /* FR-V is big endian, so put the requested byte in the first byte
323
         of the buffer allocated to hold the pseudo-register.  */
324
      ((bfd_byte *) buffer)[0] = buf[byte_num];
325
    }
326
}
327
 
328
static void
329
frv_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
330
                          int reg, const gdb_byte *buffer)
331
{
332
  if (reg == iacc0_regnum)
333
    {
334
      regcache_raw_write (regcache, iacc0h_regnum, buffer);
335
      regcache_raw_write (regcache, iacc0l_regnum, (bfd_byte *) buffer + 4);
336
    }
337
  else if (accg0_regnum <= reg && reg <= accg7_regnum)
338
    {
339
      /* The accg raw registers have four values in each slot with the
340
         lowest register number occupying the first byte.  */
341
 
342
      int raw_regnum = accg0123_regnum + (reg - accg0_regnum) / 4;
343
      int byte_num = (reg - accg0_regnum) % 4;
344
      char buf[4];
345
 
346
      regcache_raw_read (regcache, raw_regnum, buf);
347
      buf[byte_num] = ((bfd_byte *) buffer)[0];
348
      regcache_raw_write (regcache, raw_regnum, buf);
349
    }
350
}
351
 
352
static int
353
frv_register_sim_regno (struct gdbarch *gdbarch, int reg)
354
{
355
  static const int spr_map[] =
356
    {
357
      H_SPR_PSR,                /* psr_regnum */
358
      H_SPR_CCR,                /* ccr_regnum */
359
      H_SPR_CCCR,               /* cccr_regnum */
360
      -1,                       /* fdpic_loadmap_exec_regnum */
361
      -1,                       /* fdpic_loadmap_interp_regnum */
362
      -1,                       /* 134 */
363
      H_SPR_TBR,                /* tbr_regnum */
364
      H_SPR_BRR,                /* brr_regnum */
365
      H_SPR_DBAR0,              /* dbar0_regnum */
366
      H_SPR_DBAR1,              /* dbar1_regnum */
367
      H_SPR_DBAR2,              /* dbar2_regnum */
368
      H_SPR_DBAR3,              /* dbar3_regnum */
369
      H_SPR_SCR0,               /* scr0_regnum */
370
      H_SPR_SCR1,               /* scr1_regnum */
371
      H_SPR_SCR2,               /* scr2_regnum */
372
      H_SPR_SCR3,               /* scr3_regnum */
373
      H_SPR_LR,                 /* lr_regnum */
374
      H_SPR_LCR,                /* lcr_regnum */
375
      H_SPR_IACC0H,             /* iacc0h_regnum */
376
      H_SPR_IACC0L,             /* iacc0l_regnum */
377
      H_SPR_FSR0,               /* fsr0_regnum */
378
      /* FIXME: Add infrastructure for fetching/setting ACC and ACCG regs.  */
379
      -1,                       /* acc0_regnum */
380
      -1,                       /* acc1_regnum */
381
      -1,                       /* acc2_regnum */
382
      -1,                       /* acc3_regnum */
383
      -1,                       /* acc4_regnum */
384
      -1,                       /* acc5_regnum */
385
      -1,                       /* acc6_regnum */
386
      -1,                       /* acc7_regnum */
387
      -1,                       /* acc0123_regnum */
388
      -1,                       /* acc4567_regnum */
389
      H_SPR_MSR0,               /* msr0_regnum */
390
      H_SPR_MSR1,               /* msr1_regnum */
391
      H_SPR_GNER0,              /* gner0_regnum */
392
      H_SPR_GNER1,              /* gner1_regnum */
393
      H_SPR_FNER0,              /* fner0_regnum */
394
      H_SPR_FNER1,              /* fner1_regnum */
395
    };
396
 
397
  gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch));
398
 
399
  if (first_gpr_regnum <= reg && reg <= last_gpr_regnum)
400
    return reg - first_gpr_regnum + SIM_FRV_GR0_REGNUM;
401
  else if (first_fpr_regnum <= reg && reg <= last_fpr_regnum)
402
    return reg - first_fpr_regnum + SIM_FRV_FR0_REGNUM;
403
  else if (pc_regnum == reg)
404
    return SIM_FRV_PC_REGNUM;
405
  else if (reg >= first_spr_regnum
406
           && reg < first_spr_regnum + sizeof (spr_map) / sizeof (spr_map[0]))
407
    {
408
      int spr_reg_offset = spr_map[reg - first_spr_regnum];
409
 
410
      if (spr_reg_offset < 0)
411
        return SIM_REGNO_DOES_NOT_EXIST;
412
      else
413
        return SIM_FRV_SPR0_REGNUM + spr_reg_offset;
414
    }
415
 
416
  internal_error (__FILE__, __LINE__, _("Bad register number %d"), reg);
417
}
418
 
419
static const unsigned char *
420
frv_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenp)
421
{
422
  static unsigned char breakpoint[] = {0xc0, 0x70, 0x00, 0x01};
423
  *lenp = sizeof (breakpoint);
424
  return breakpoint;
425
}
426
 
427
/* Define the maximum number of instructions which may be packed into a
428
   bundle (VLIW instruction).  */
429
static const int max_instrs_per_bundle = 8;
430
 
431
/* Define the size (in bytes) of an FR-V instruction.  */
432
static const int frv_instr_size = 4;
433
 
434
/* Adjust a breakpoint's address to account for the FR-V architecture's
435
   constraint that a break instruction must not appear as any but the
436
   first instruction in the bundle.  */
437
static CORE_ADDR
438
frv_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr)
439
{
440
  int count = max_instrs_per_bundle;
441
  CORE_ADDR addr = bpaddr - frv_instr_size;
442
  CORE_ADDR func_start = get_pc_function_start (bpaddr);
443
 
444
  /* Find the end of the previous packing sequence.  This will be indicated
445
     by either attempting to access some inaccessible memory or by finding
446
     an instruction word whose packing bit is set to one. */
447
  while (count-- > 0 && addr >= func_start)
448
    {
449
      char instr[frv_instr_size];
450
      int status;
451
 
452
      status = read_memory_nobpt (addr, instr, sizeof instr);
453
 
454
      if (status != 0)
455
        break;
456
 
457
      /* This is a big endian architecture, so byte zero will have most
458
         significant byte.  The most significant bit of this byte is the
459
         packing bit.  */
460
      if (instr[0] & 0x80)
461
        break;
462
 
463
      addr -= frv_instr_size;
464
    }
465
 
466
  if (count > 0)
467
    bpaddr = addr + frv_instr_size;
468
 
469
  return bpaddr;
470
}
471
 
472
 
473
/* Return true if REG is a caller-saves ("scratch") register,
474
   false otherwise.  */
475
static int
476
is_caller_saves_reg (int reg)
477
{
478
  return ((4 <= reg && reg <= 7)
479
          || (14 <= reg && reg <= 15)
480
          || (32 <= reg && reg <= 47));
481
}
482
 
483
 
484
/* Return true if REG is a callee-saves register, false otherwise.  */
485
static int
486
is_callee_saves_reg (int reg)
487
{
488
  return ((16 <= reg && reg <= 31)
489
          || (48 <= reg && reg <= 63));
490
}
491
 
492
 
493
/* Return true if REG is an argument register, false otherwise.  */
494
static int
495
is_argument_reg (int reg)
496
{
497
  return (8 <= reg && reg <= 13);
498
}
499
 
500
/* Scan an FR-V prologue, starting at PC, until frame->PC.
501
   If FRAME is non-zero, fill in its saved_regs with appropriate addresses.
502
   We assume FRAME's saved_regs array has already been allocated and cleared.
503
   Return the first PC value after the prologue.
504
 
505
   Note that, for unoptimized code, we almost don't need this function
506
   at all; all arguments and locals live on the stack, so we just need
507
   the FP to find everything.  The catch: structures passed by value
508
   have their addresses living in registers; they're never spilled to
509
   the stack.  So if you ever want to be able to get to these
510
   arguments in any frame but the top, you'll need to do this serious
511
   prologue analysis.  */
512
static CORE_ADDR
513
frv_analyze_prologue (CORE_ADDR pc, struct frame_info *next_frame,
514
                      struct frv_unwind_cache *info)
515
{
516
  /* When writing out instruction bitpatterns, we use the following
517
     letters to label instruction fields:
518
     P - The parallel bit.  We don't use this.
519
     J - The register number of GRj in the instruction description.
520
     K - The register number of GRk in the instruction description.
521
     I - The register number of GRi.
522
     S - a signed imediate offset.
523
     U - an unsigned immediate offset.
524
 
525
     The dots below the numbers indicate where hex digit boundaries
526
     fall, to make it easier to check the numbers.  */
527
 
528
  /* Non-zero iff we've seen the instruction that initializes the
529
     frame pointer for this function's frame.  */
530
  int fp_set = 0;
531
 
532
  /* If fp_set is non_zero, then this is the distance from
533
     the stack pointer to frame pointer: fp = sp + fp_offset.  */
534
  int fp_offset = 0;
535
 
536
  /* Total size of frame prior to any alloca operations. */
537
  int framesize = 0;
538
 
539
  /* Flag indicating if lr has been saved on the stack.  */
540
  int lr_saved_on_stack = 0;
541
 
542
  /* The number of the general-purpose register we saved the return
543
     address ("link register") in, or -1 if we haven't moved it yet.  */
544
  int lr_save_reg = -1;
545
 
546
  /* Offset (from sp) at which lr has been saved on the stack.  */
547
 
548
  int lr_sp_offset = 0;
549
 
550
  /* If gr_saved[i] is non-zero, then we've noticed that general
551
     register i has been saved at gr_sp_offset[i] from the stack
552
     pointer.  */
553
  char gr_saved[64];
554
  int gr_sp_offset[64];
555
 
556
  /* The address of the most recently scanned prologue instruction.  */
557
  CORE_ADDR last_prologue_pc;
558
 
559
  /* The address of the next instruction. */
560
  CORE_ADDR next_pc;
561
 
562
  /* The upper bound to of the pc values to scan.  */
563
  CORE_ADDR lim_pc;
564
 
565
  memset (gr_saved, 0, sizeof (gr_saved));
566
 
567
  last_prologue_pc = pc;
568
 
569
  /* Try to compute an upper limit (on how far to scan) based on the
570
     line number info.  */
571
  lim_pc = skip_prologue_using_sal (pc);
572
  /* If there's no line number info, lim_pc will be 0.  In that case,
573
     set the limit to be 100 instructions away from pc.  Hopefully, this
574
     will be far enough away to account for the entire prologue.  Don't
575
     worry about overshooting the end of the function.  The scan loop
576
     below contains some checks to avoid scanning unreasonably far.  */
577
  if (lim_pc == 0)
578
    lim_pc = pc + 400;
579
 
580
  /* If we have a frame, we don't want to scan past the frame's pc.  This
581
     will catch those cases where the pc is in the prologue.  */
582
  if (next_frame)
583
    {
584
      CORE_ADDR frame_pc = frame_pc_unwind (next_frame);
585
      if (frame_pc < lim_pc)
586
        lim_pc = frame_pc;
587
    }
588
 
589
  /* Scan the prologue.  */
590
  while (pc < lim_pc)
591
    {
592
      char buf[frv_instr_size];
593
      LONGEST op;
594
 
595
      if (target_read_memory (pc, buf, sizeof buf) != 0)
596
        break;
597
      op = extract_signed_integer (buf, sizeof buf);
598
 
599
      next_pc = pc + 4;
600
 
601
      /* The tests in this chain of ifs should be in order of
602
         decreasing selectivity, so that more particular patterns get
603
         to fire before less particular patterns.  */
604
 
605
      /* Some sort of control transfer instruction: stop scanning prologue.
606
         Integer Conditional Branch:
607
          X XXXX XX 0000110 XX XXXXXXXXXXXXXXXX
608
         Floating-point / media Conditional Branch:
609
          X XXXX XX 0000111 XX XXXXXXXXXXXXXXXX
610
         LCR Conditional Branch to LR
611
          X XXXX XX 0001110 XX XX 001 X XXXXXXXXXX
612
         Integer conditional Branches to LR
613
          X XXXX XX 0001110 XX XX 010 X XXXXXXXXXX
614
          X XXXX XX 0001110 XX XX 011 X XXXXXXXXXX
615
         Floating-point/Media Branches to LR
616
          X XXXX XX 0001110 XX XX 110 X XXXXXXXXXX
617
          X XXXX XX 0001110 XX XX 111 X XXXXXXXXXX
618
         Jump and Link
619
          X XXXXX X 0001100 XXXXXX XXXXXX XXXXXX
620
          X XXXXX X 0001101 XXXXXX XXXXXX XXXXXX
621
         Call
622
          X XXXXXX 0001111 XXXXXXXXXXXXXXXXXX
623
         Return from Trap
624
          X XXXXX X 0000101 XXXXXX XXXXXX XXXXXX
625
         Integer Conditional Trap
626
          X XXXX XX 0000100 XXXXXX XXXX 00 XXXXXX
627
          X XXXX XX 0011100 XXXXXX XXXXXXXXXXXX
628
         Floating-point /media Conditional Trap
629
          X XXXX XX 0000100 XXXXXX XXXX 01 XXXXXX
630
          X XXXX XX 0011101 XXXXXX XXXXXXXXXXXX
631
         Break
632
          X XXXX XX 0000100 XXXXXX XXXX 11 XXXXXX
633
         Media Trap
634
          X XXXX XX 0000100 XXXXXX XXXX 10 XXXXXX */
635
      if ((op & 0x01d80000) == 0x00180000 /* Conditional branches and Call */
636
          || (op & 0x01f80000) == 0x00300000  /* Jump and Link */
637
          || (op & 0x01f80000) == 0x00100000  /* Return from Trap, Trap */
638
          || (op & 0x01f80000) == 0x00700000) /* Trap immediate */
639
        {
640
          /* Stop scanning; not in prologue any longer.  */
641
          break;
642
        }
643
 
644
      /* Loading something from memory into fp probably means that
645
         we're in the epilogue.  Stop scanning the prologue.
646
         ld @(GRi, GRk), fp
647
         X 000010 0000010 XXXXXX 000100 XXXXXX
648
         ldi @(GRi, d12), fp
649
         X 000010 0110010 XXXXXX XXXXXXXXXXXX */
650
      else if ((op & 0x7ffc0fc0) == 0x04080100
651
               || (op & 0x7ffc0000) == 0x04c80000)
652
        {
653
          break;
654
        }
655
 
656
      /* Setting the FP from the SP:
657
         ori sp, 0, fp
658
         P 000010 0100010 000001 000000000000 = 0x04881000
659
 
660
             .    .   .    .   .    .   .   .
661
         We treat this as part of the prologue.  */
662
      else if ((op & 0x7fffffff) == 0x04881000)
663
        {
664
          fp_set = 1;
665
          fp_offset = 0;
666
          last_prologue_pc = next_pc;
667
        }
668
 
669
      /* Move the link register to the scratch register grJ, before saving:
670
         movsg lr, grJ
671
         P 000100 0000011 010000 000111 JJJJJJ = 0x080d01c0
672
 
673
             .    .   .    .   .    .    .   .
674
         We treat this as part of the prologue.  */
675
      else if ((op & 0x7fffffc0) == 0x080d01c0)
676
        {
677
          int gr_j = op & 0x3f;
678
 
679
          /* If we're moving it to a scratch register, that's fine.  */
680
          if (is_caller_saves_reg (gr_j))
681
            {
682
              lr_save_reg = gr_j;
683
              last_prologue_pc = next_pc;
684
            }
685
        }
686
 
687
      /* To save multiple callee-saves registers on the stack, at
688
         offset zero:
689
 
690
         std grK,@(sp,gr0)
691
         P KKKKKK 0000011 000001 000011 000000 = 0x000c10c0
692
 
693
 
694
         stq grK,@(sp,gr0)
695
         P KKKKKK 0000011 000001 000100 000000 = 0x000c1100
696
 
697
             .    .   .    .   .    .    .   .
698
         We treat this as part of the prologue, and record the register's
699
         saved address in the frame structure.  */
700
      else if ((op & 0x01ffffff) == 0x000c10c0
701
            || (op & 0x01ffffff) == 0x000c1100)
702
        {
703
          int gr_k = ((op >> 25) & 0x3f);
704
          int ope  = ((op >> 6)  & 0x3f);
705
          int count;
706
          int i;
707
 
708
          /* Is it an std or an stq?  */
709
          if (ope == 0x03)
710
            count = 2;
711
          else
712
            count = 4;
713
 
714
          /* Is it really a callee-saves register?  */
715
          if (is_callee_saves_reg (gr_k))
716
            {
717
              for (i = 0; i < count; i++)
718
                {
719
                  gr_saved[gr_k + i] = 1;
720
                  gr_sp_offset[gr_k + i] = 4 * i;
721
                }
722
              last_prologue_pc = next_pc;
723
            }
724
        }
725
 
726
      /* Adjusting the stack pointer.  (The stack pointer is GR1.)
727
         addi sp, S, sp
728
         P 000001 0010000 000001 SSSSSSSSSSSS = 0x02401000
729
 
730
             .    .   .    .   .    .   .   .
731
         We treat this as part of the prologue.  */
732
      else if ((op & 0x7ffff000) == 0x02401000)
733
        {
734
          if (framesize == 0)
735
            {
736
              /* Sign-extend the twelve-bit field.
737
                 (Isn't there a better way to do this?)  */
738
              int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;
739
 
740
              framesize -= s;
741
              last_prologue_pc = pc;
742
            }
743
          else
744
            {
745
              /* If the prologue is being adjusted again, we've
746
                 likely gone too far; i.e. we're probably in the
747
                 epilogue.  */
748
              break;
749
            }
750
        }
751
 
752
      /* Setting the FP to a constant distance from the SP:
753
         addi sp, S, fp
754
         P 000010 0010000 000001 SSSSSSSSSSSS = 0x04401000
755
 
756
             .    .   .    .   .    .   .   .
757
         We treat this as part of the prologue.  */
758
      else if ((op & 0x7ffff000) == 0x04401000)
759
        {
760
          /* Sign-extend the twelve-bit field.
761
             (Isn't there a better way to do this?)  */
762
          int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;
763
          fp_set = 1;
764
          fp_offset = s;
765
          last_prologue_pc = pc;
766
        }
767
 
768
      /* To spill an argument register to a scratch register:
769
            ori GRi, 0, GRk
770
         P KKKKKK 0100010 IIIIII 000000000000 = 0x00880000
771
 
772
             .    .   .    .   .    .   .   .
773
         For the time being, we treat this as a prologue instruction,
774
         assuming that GRi is an argument register.  This one's kind
775
         of suspicious, because it seems like it could be part of a
776
         legitimate body instruction.  But we only come here when the
777
         source info wasn't helpful, so we have to do the best we can.
778
         Hopefully once GCC and GDB agree on how to emit line number
779
         info for prologues, then this code will never come into play.  */
780
      else if ((op & 0x01fc0fff) == 0x00880000)
781
        {
782
          int gr_i = ((op >> 12) & 0x3f);
783
 
784
          /* Make sure that the source is an arg register; if it is, we'll
785
             treat it as a prologue instruction.  */
786
          if (is_argument_reg (gr_i))
787
            last_prologue_pc = next_pc;
788
        }
789
 
790
      /* To spill 16-bit values to the stack:
791
             sthi GRk, @(fp, s)
792
         P KKKKKK 1010001 000010 SSSSSSSSSSSS = 0x01442000
793
 
794
             .    .   .    .   .    .   .   .
795
         And for 8-bit values, we use STB instructions.
796
             stbi GRk, @(fp, s)
797
         P KKKKKK 1010000 000010 SSSSSSSSSSSS = 0x01402000
798
 
799
             .    .   .    .   .    .   .   .
800
         We check that GRk is really an argument register, and treat
801
         all such as part of the prologue.  */
802
      else if (   (op & 0x01fff000) == 0x01442000
803
               || (op & 0x01fff000) == 0x01402000)
804
        {
805
          int gr_k = ((op >> 25) & 0x3f);
806
 
807
          /* Make sure that GRk is really an argument register; treat
808
             it as a prologue instruction if so.  */
809
          if (is_argument_reg (gr_k))
810
            last_prologue_pc = next_pc;
811
        }
812
 
813
      /* To save multiple callee-saves register on the stack, at a
814
         non-zero offset:
815
 
816
         stdi GRk, @(sp, s)
817
         P KKKKKK 1010011 000001 SSSSSSSSSSSS = 0x014c1000
818
 
819
             .    .   .    .   .    .   .   .
820
         stqi GRk, @(sp, s)
821
         P KKKKKK 1010100 000001 SSSSSSSSSSSS = 0x01501000
822
 
823
             .    .   .    .   .    .   .   .
824
         We treat this as part of the prologue, and record the register's
825
         saved address in the frame structure.  */
826
      else if ((op & 0x01fff000) == 0x014c1000
827
            || (op & 0x01fff000) == 0x01501000)
828
        {
829
          int gr_k = ((op >> 25) & 0x3f);
830
          int count;
831
          int i;
832
 
833
          /* Is it a stdi or a stqi?  */
834
          if ((op & 0x01fff000) == 0x014c1000)
835
            count = 2;
836
          else
837
            count = 4;
838
 
839
          /* Is it really a callee-saves register?  */
840
          if (is_callee_saves_reg (gr_k))
841
            {
842
              /* Sign-extend the twelve-bit field.
843
                 (Isn't there a better way to do this?)  */
844
              int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;
845
 
846
              for (i = 0; i < count; i++)
847
                {
848
                  gr_saved[gr_k + i] = 1;
849
                  gr_sp_offset[gr_k + i] = s + (4 * i);
850
                }
851
              last_prologue_pc = next_pc;
852
            }
853
        }
854
 
855
      /* Storing any kind of integer register at any constant offset
856
         from any other register.
857
 
858
         st GRk, @(GRi, gr0)
859
         P KKKKKK 0000011 IIIIII 000010 000000 = 0x000c0080
860
 
861
             .    .   .    .   .    .    .   .
862
         sti GRk, @(GRi, d12)
863
         P KKKKKK 1010010 IIIIII SSSSSSSSSSSS = 0x01480000
864
 
865
             .    .   .    .   .    .   .   .
866
         These could be almost anything, but a lot of prologue
867
         instructions fall into this pattern, so let's decode the
868
         instruction once, and then work at a higher level.  */
869
      else if (((op & 0x01fc0fff) == 0x000c0080)
870
            || ((op & 0x01fc0000) == 0x01480000))
871
        {
872
          int gr_k = ((op >> 25) & 0x3f);
873
          int gr_i = ((op >> 12) & 0x3f);
874
          int offset;
875
 
876
          /* Are we storing with gr0 as an offset, or using an
877
             immediate value?  */
878
          if ((op & 0x01fc0fff) == 0x000c0080)
879
            offset = 0;
880
          else
881
            offset = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;
882
 
883
          /* If the address isn't relative to the SP or FP, it's not a
884
             prologue instruction.  */
885
          if (gr_i != sp_regnum && gr_i != fp_regnum)
886
            {
887
              /* Do nothing; not a prologue instruction.  */
888
            }
889
 
890
          /* Saving the old FP in the new frame (relative to the SP).  */
891
          else if (gr_k == fp_regnum && gr_i == sp_regnum)
892
            {
893
              gr_saved[fp_regnum] = 1;
894
              gr_sp_offset[fp_regnum] = offset;
895
              last_prologue_pc = next_pc;
896
            }
897
 
898
          /* Saving callee-saves register(s) on the stack, relative to
899
             the SP.  */
900
          else if (gr_i == sp_regnum
901
                   && is_callee_saves_reg (gr_k))
902
            {
903
              gr_saved[gr_k] = 1;
904
              if (gr_i == sp_regnum)
905
                gr_sp_offset[gr_k] = offset;
906
              else
907
                gr_sp_offset[gr_k] = offset + fp_offset;
908
              last_prologue_pc = next_pc;
909
            }
910
 
911
          /* Saving the scratch register holding the return address.  */
912
          else if (lr_save_reg != -1
913
                   && gr_k == lr_save_reg)
914
            {
915
              lr_saved_on_stack = 1;
916
              if (gr_i == sp_regnum)
917
                lr_sp_offset = offset;
918
              else
919
                lr_sp_offset = offset + fp_offset;
920
              last_prologue_pc = next_pc;
921
            }
922
 
923
          /* Spilling int-sized arguments to the stack.  */
924
          else if (is_argument_reg (gr_k))
925
            last_prologue_pc = next_pc;
926
        }
927
      pc = next_pc;
928
    }
929
 
930
  if (next_frame && info)
931
    {
932
      int i;
933
      ULONGEST this_base;
934
 
935
      /* If we know the relationship between the stack and frame
936
         pointers, record the addresses of the registers we noticed.
937
         Note that we have to do this as a separate step at the end,
938
         because instructions may save relative to the SP, but we need
939
         their addresses relative to the FP.  */
940
      if (fp_set)
941
        this_base = frame_unwind_register_unsigned (next_frame, fp_regnum);
942
      else
943
        this_base = frame_unwind_register_unsigned (next_frame, sp_regnum);
944
 
945
      for (i = 0; i < 64; i++)
946
        if (gr_saved[i])
947
          info->saved_regs[i].addr = this_base - fp_offset + gr_sp_offset[i];
948
 
949
      info->prev_sp = this_base - fp_offset + framesize;
950
      info->base = this_base;
951
 
952
      /* If LR was saved on the stack, record its location.  */
953
      if (lr_saved_on_stack)
954
        info->saved_regs[lr_regnum].addr = this_base - fp_offset + lr_sp_offset;
955
 
956
      /* The call instruction moves the caller's PC in the callee's LR.
957
         Since this is an unwind, do the reverse.  Copy the location of LR
958
         into PC (the address / regnum) so that a request for PC will be
959
         converted into a request for the LR.  */
960
      info->saved_regs[pc_regnum] = info->saved_regs[lr_regnum];
961
 
962
      /* Save the previous frame's computed SP value.  */
963
      trad_frame_set_value (info->saved_regs, sp_regnum, info->prev_sp);
964
    }
965
 
966
  return last_prologue_pc;
967
}
968
 
969
 
970
static CORE_ADDR
971
frv_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
972
{
973
  CORE_ADDR func_addr, func_end, new_pc;
974
 
975
  new_pc = pc;
976
 
977
  /* If the line table has entry for a line *within* the function
978
     (i.e., not in the prologue, and not past the end), then that's
979
     our location.  */
980
  if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
981
    {
982
      struct symtab_and_line sal;
983
 
984
      sal = find_pc_line (func_addr, 0);
985
 
986
      if (sal.line != 0 && sal.end < func_end)
987
        {
988
          new_pc = sal.end;
989
        }
990
    }
991
 
992
  /* The FR-V prologue is at least five instructions long (twenty bytes).
993
     If we didn't find a real source location past that, then
994
     do a full analysis of the prologue.  */
995
  if (new_pc < pc + 20)
996
    new_pc = frv_analyze_prologue (pc, 0, 0);
997
 
998
  return new_pc;
999
}
1000
 
1001
 
1002
static struct frv_unwind_cache *
1003
frv_frame_unwind_cache (struct frame_info *next_frame,
1004
                         void **this_prologue_cache)
1005
{
1006
  struct gdbarch *gdbarch = get_frame_arch (next_frame);
1007
  CORE_ADDR pc;
1008
  ULONGEST this_base;
1009
  struct frv_unwind_cache *info;
1010
 
1011
  if ((*this_prologue_cache))
1012
    return (*this_prologue_cache);
1013
 
1014
  info = FRAME_OBSTACK_ZALLOC (struct frv_unwind_cache);
1015
  (*this_prologue_cache) = info;
1016
  info->saved_regs = trad_frame_alloc_saved_regs (next_frame);
1017
 
1018
  /* Prologue analysis does the rest...  */
1019
  frv_analyze_prologue (frame_func_unwind (next_frame, NORMAL_FRAME),
1020
                        next_frame, info);
1021
 
1022
  return info;
1023
}
1024
 
1025
static void
1026
frv_extract_return_value (struct type *type, struct regcache *regcache,
1027
                          gdb_byte *valbuf)
1028
{
1029
  int len = TYPE_LENGTH (type);
1030
 
1031
  if (len <= 4)
1032
    {
1033
      ULONGEST gpr8_val;
1034
      regcache_cooked_read_unsigned (regcache, 8, &gpr8_val);
1035
      store_unsigned_integer (valbuf, len, gpr8_val);
1036
    }
1037
  else if (len == 8)
1038
    {
1039
      ULONGEST regval;
1040
      regcache_cooked_read_unsigned (regcache, 8, &regval);
1041
      store_unsigned_integer (valbuf, 4, regval);
1042
      regcache_cooked_read_unsigned (regcache, 9, &regval);
1043
      store_unsigned_integer ((bfd_byte *) valbuf + 4, 4, regval);
1044
    }
1045
  else
1046
    internal_error (__FILE__, __LINE__, _("Illegal return value length: %d"), len);
1047
}
1048
 
1049
static CORE_ADDR
1050
frv_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1051
{
1052
  /* Require dword alignment.  */
1053
  return align_down (sp, 8);
1054
}
1055
 
1056
static CORE_ADDR
1057
find_func_descr (struct gdbarch *gdbarch, CORE_ADDR entry_point)
1058
{
1059
  CORE_ADDR descr;
1060
  char valbuf[4];
1061
  CORE_ADDR start_addr;
1062
 
1063
  /* If we can't find the function in the symbol table, then we assume
1064
     that the function address is already in descriptor form.  */
1065
  if (!find_pc_partial_function (entry_point, NULL, &start_addr, NULL)
1066
      || entry_point != start_addr)
1067
    return entry_point;
1068
 
1069
  descr = frv_fdpic_find_canonical_descriptor (entry_point);
1070
 
1071
  if (descr != 0)
1072
    return descr;
1073
 
1074
  /* Construct a non-canonical descriptor from space allocated on
1075
     the stack.  */
1076
 
1077
  descr = value_as_long (value_allocate_space_in_inferior (8));
1078
  store_unsigned_integer (valbuf, 4, entry_point);
1079
  write_memory (descr, valbuf, 4);
1080
  store_unsigned_integer (valbuf, 4,
1081
                          frv_fdpic_find_global_pointer (entry_point));
1082
  write_memory (descr + 4, valbuf, 4);
1083
  return descr;
1084
}
1085
 
1086
static CORE_ADDR
1087
frv_convert_from_func_ptr_addr (struct gdbarch *gdbarch, CORE_ADDR addr,
1088
                                struct target_ops *targ)
1089
{
1090
  CORE_ADDR entry_point;
1091
  CORE_ADDR got_address;
1092
 
1093
  entry_point = get_target_memory_unsigned (targ, addr, 4);
1094
  got_address = get_target_memory_unsigned (targ, addr + 4, 4);
1095
 
1096
  if (got_address == frv_fdpic_find_global_pointer (entry_point))
1097
    return entry_point;
1098
  else
1099
    return addr;
1100
}
1101
 
1102
static CORE_ADDR
1103
frv_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1104
                     struct regcache *regcache, CORE_ADDR bp_addr,
1105
                     int nargs, struct value **args, CORE_ADDR sp,
1106
                     int struct_return, CORE_ADDR struct_addr)
1107
{
1108
  int argreg;
1109
  int argnum;
1110
  char *val;
1111
  char valbuf[4];
1112
  struct value *arg;
1113
  struct type *arg_type;
1114
  int len;
1115
  enum type_code typecode;
1116
  CORE_ADDR regval;
1117
  int stack_space;
1118
  int stack_offset;
1119
  enum frv_abi abi = frv_abi (gdbarch);
1120
  CORE_ADDR func_addr = find_function_addr (function, NULL);
1121
 
1122
#if 0
1123
  printf("Push %d args at sp = %x, struct_return=%d (%x)\n",
1124
         nargs, (int) sp, struct_return, struct_addr);
1125
#endif
1126
 
1127
  stack_space = 0;
1128
  for (argnum = 0; argnum < nargs; ++argnum)
1129
    stack_space += align_up (TYPE_LENGTH (value_type (args[argnum])), 4);
1130
 
1131
  stack_space -= (6 * 4);
1132
  if (stack_space > 0)
1133
    sp -= stack_space;
1134
 
1135
  /* Make sure stack is dword aligned. */
1136
  sp = align_down (sp, 8);
1137
 
1138
  stack_offset = 0;
1139
 
1140
  argreg = 8;
1141
 
1142
  if (struct_return)
1143
    regcache_cooked_write_unsigned (regcache, struct_return_regnum,
1144
                                    struct_addr);
1145
 
1146
  for (argnum = 0; argnum < nargs; ++argnum)
1147
    {
1148
      arg = args[argnum];
1149
      arg_type = check_typedef (value_type (arg));
1150
      len = TYPE_LENGTH (arg_type);
1151
      typecode = TYPE_CODE (arg_type);
1152
 
1153
      if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
1154
        {
1155
          store_unsigned_integer (valbuf, 4, VALUE_ADDRESS (arg));
1156
          typecode = TYPE_CODE_PTR;
1157
          len = 4;
1158
          val = valbuf;
1159
        }
1160
      else if (abi == FRV_ABI_FDPIC
1161
               && len == 4
1162
               && typecode == TYPE_CODE_PTR
1163
               && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC)
1164
        {
1165
          /* The FDPIC ABI requires function descriptors to be passed instead
1166
             of entry points.  */
1167
          store_unsigned_integer
1168
            (valbuf, 4,
1169
             find_func_descr (gdbarch,
1170
                              extract_unsigned_integer (value_contents (arg),
1171
                                                        4)));
1172
          typecode = TYPE_CODE_PTR;
1173
          len = 4;
1174
          val = valbuf;
1175
        }
1176
      else
1177
        {
1178
          val = (char *) value_contents (arg);
1179
        }
1180
 
1181
      while (len > 0)
1182
        {
1183
          int partial_len = (len < 4 ? len : 4);
1184
 
1185
          if (argreg < 14)
1186
            {
1187
              regval = extract_unsigned_integer (val, partial_len);
1188
#if 0
1189
              printf("  Argnum %d data %x -> reg %d\n",
1190
                     argnum, (int) regval, argreg);
1191
#endif
1192
              regcache_cooked_write_unsigned (regcache, argreg, regval);
1193
              ++argreg;
1194
            }
1195
          else
1196
            {
1197
#if 0
1198
              printf("  Argnum %d data %x -> offset %d (%x)\n",
1199
                     argnum, *((int *)val), stack_offset, (int) (sp + stack_offset));
1200
#endif
1201
              write_memory (sp + stack_offset, val, partial_len);
1202
              stack_offset += align_up (partial_len, 4);
1203
            }
1204
          len -= partial_len;
1205
          val += partial_len;
1206
        }
1207
    }
1208
 
1209
  /* Set the return address.  For the frv, the return breakpoint is
1210
     always at BP_ADDR.  */
1211
  regcache_cooked_write_unsigned (regcache, lr_regnum, bp_addr);
1212
 
1213
  if (abi == FRV_ABI_FDPIC)
1214
    {
1215
      /* Set the GOT register for the FDPIC ABI.  */
1216
      regcache_cooked_write_unsigned
1217
        (regcache, first_gpr_regnum + 15,
1218
         frv_fdpic_find_global_pointer (func_addr));
1219
    }
1220
 
1221
  /* Finally, update the SP register.  */
1222
  regcache_cooked_write_unsigned (regcache, sp_regnum, sp);
1223
 
1224
  return sp;
1225
}
1226
 
1227
static void
1228
frv_store_return_value (struct type *type, struct regcache *regcache,
1229
                        const gdb_byte *valbuf)
1230
{
1231
  int len = TYPE_LENGTH (type);
1232
 
1233
  if (len <= 4)
1234
    {
1235
      bfd_byte val[4];
1236
      memset (val, 0, sizeof (val));
1237
      memcpy (val + (4 - len), valbuf, len);
1238
      regcache_cooked_write (regcache, 8, val);
1239
    }
1240
  else if (len == 8)
1241
    {
1242
      regcache_cooked_write (regcache, 8, valbuf);
1243
      regcache_cooked_write (regcache, 9, (bfd_byte *) valbuf + 4);
1244
    }
1245
  else
1246
    internal_error (__FILE__, __LINE__,
1247
                    _("Don't know how to return a %d-byte value."), len);
1248
}
1249
 
1250
enum return_value_convention
1251
frv_return_value (struct gdbarch *gdbarch, struct type *valtype,
1252
                  struct regcache *regcache, gdb_byte *readbuf,
1253
                  const gdb_byte *writebuf)
1254
{
1255
  int struct_return = TYPE_CODE (valtype) == TYPE_CODE_STRUCT
1256
                      || TYPE_CODE (valtype) == TYPE_CODE_UNION
1257
                      || TYPE_CODE (valtype) == TYPE_CODE_ARRAY;
1258
 
1259
  if (writebuf != NULL)
1260
    {
1261
      gdb_assert (!struct_return);
1262
      frv_store_return_value (valtype, regcache, writebuf);
1263
    }
1264
 
1265
  if (readbuf != NULL)
1266
    {
1267
      gdb_assert (!struct_return);
1268
      frv_extract_return_value (valtype, regcache, readbuf);
1269
    }
1270
 
1271
  if (struct_return)
1272
    return RETURN_VALUE_STRUCT_CONVENTION;
1273
  else
1274
    return RETURN_VALUE_REGISTER_CONVENTION;
1275
}
1276
 
1277
 
1278
/* Hardware watchpoint / breakpoint support for the FR500
1279
   and FR400.  */
1280
 
1281
int
1282
frv_check_watch_resources (struct gdbarch *gdbarch, int type, int cnt, int ot)
1283
{
1284
  struct gdbarch_tdep *var = gdbarch_tdep (gdbarch);
1285
 
1286
  /* Watchpoints not supported on simulator.  */
1287
  if (strcmp (target_shortname, "sim") == 0)
1288
    return 0;
1289
 
1290
  if (type == bp_hardware_breakpoint)
1291
    {
1292
      if (var->num_hw_breakpoints == 0)
1293
        return 0;
1294
      else if (cnt <= var->num_hw_breakpoints)
1295
        return 1;
1296
    }
1297
  else
1298
    {
1299
      if (var->num_hw_watchpoints == 0)
1300
        return 0;
1301
      else if (ot)
1302
        return -1;
1303
      else if (cnt <= var->num_hw_watchpoints)
1304
        return 1;
1305
    }
1306
  return -1;
1307
}
1308
 
1309
 
1310
int
1311
frv_stopped_data_address (CORE_ADDR *addr_p)
1312
{
1313
  struct frame_info *frame = get_current_frame ();
1314
  CORE_ADDR brr, dbar0, dbar1, dbar2, dbar3;
1315
 
1316
  brr = get_frame_register_unsigned (frame, brr_regnum);
1317
  dbar0 = get_frame_register_unsigned (frame, dbar0_regnum);
1318
  dbar1 = get_frame_register_unsigned (frame, dbar1_regnum);
1319
  dbar2 = get_frame_register_unsigned (frame, dbar2_regnum);
1320
  dbar3 = get_frame_register_unsigned (frame, dbar3_regnum);
1321
 
1322
  if (brr & (1<<11))
1323
    *addr_p = dbar0;
1324
  else if (brr & (1<<10))
1325
    *addr_p = dbar1;
1326
  else if (brr & (1<<9))
1327
    *addr_p = dbar2;
1328
  else if (brr & (1<<8))
1329
    *addr_p = dbar3;
1330
  else
1331
    return 0;
1332
 
1333
  return 1;
1334
}
1335
 
1336
int
1337
frv_have_stopped_data_address (void)
1338
{
1339
  CORE_ADDR addr = 0;
1340
  return frv_stopped_data_address (&addr);
1341
}
1342
 
1343
static CORE_ADDR
1344
frv_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1345
{
1346
  return frame_unwind_register_unsigned (next_frame, pc_regnum);
1347
}
1348
 
1349
/* Given a GDB frame, determine the address of the calling function's
1350
   frame.  This will be used to create a new GDB frame struct.  */
1351
 
1352
static void
1353
frv_frame_this_id (struct frame_info *next_frame,
1354
                    void **this_prologue_cache, struct frame_id *this_id)
1355
{
1356
  struct frv_unwind_cache *info
1357
    = frv_frame_unwind_cache (next_frame, this_prologue_cache);
1358
  CORE_ADDR base;
1359
  CORE_ADDR func;
1360
  struct minimal_symbol *msym_stack;
1361
  struct frame_id id;
1362
 
1363
  /* The FUNC is easy.  */
1364
  func = frame_func_unwind (next_frame, NORMAL_FRAME);
1365
 
1366
  /* Check if the stack is empty.  */
1367
  msym_stack = lookup_minimal_symbol ("_stack", NULL, NULL);
1368
  if (msym_stack && info->base == SYMBOL_VALUE_ADDRESS (msym_stack))
1369
    return;
1370
 
1371
  /* Hopefully the prologue analysis either correctly determined the
1372
     frame's base (which is the SP from the previous frame), or set
1373
     that base to "NULL".  */
1374
  base = info->prev_sp;
1375
  if (base == 0)
1376
    return;
1377
 
1378
  id = frame_id_build (base, func);
1379
  (*this_id) = id;
1380
}
1381
 
1382
static void
1383
frv_frame_prev_register (struct frame_info *next_frame,
1384
                          void **this_prologue_cache,
1385
                          int regnum, int *optimizedp,
1386
                          enum lval_type *lvalp, CORE_ADDR *addrp,
1387
                          int *realnump, gdb_byte *bufferp)
1388
{
1389
  struct frv_unwind_cache *info
1390
    = frv_frame_unwind_cache (next_frame, this_prologue_cache);
1391
  trad_frame_get_prev_register (next_frame, info->saved_regs, regnum,
1392
                                optimizedp, lvalp, addrp, realnump, bufferp);
1393
}
1394
 
1395
static const struct frame_unwind frv_frame_unwind = {
1396
  NORMAL_FRAME,
1397
  frv_frame_this_id,
1398
  frv_frame_prev_register
1399
};
1400
 
1401
static const struct frame_unwind *
1402
frv_frame_sniffer (struct frame_info *next_frame)
1403
{
1404
  return &frv_frame_unwind;
1405
}
1406
 
1407
static CORE_ADDR
1408
frv_frame_base_address (struct frame_info *next_frame, void **this_cache)
1409
{
1410
  struct frv_unwind_cache *info
1411
    = frv_frame_unwind_cache (next_frame, this_cache);
1412
  return info->base;
1413
}
1414
 
1415
static const struct frame_base frv_frame_base = {
1416
  &frv_frame_unwind,
1417
  frv_frame_base_address,
1418
  frv_frame_base_address,
1419
  frv_frame_base_address
1420
};
1421
 
1422
static CORE_ADDR
1423
frv_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1424
{
1425
  return frame_unwind_register_unsigned (next_frame, sp_regnum);
1426
}
1427
 
1428
 
1429
/* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1430
   dummy frame.  The frame ID's base needs to match the TOS value
1431
   saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1432
   breakpoint.  */
1433
 
1434
static struct frame_id
1435
frv_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1436
{
1437
  return frame_id_build (frv_unwind_sp (gdbarch, next_frame),
1438
                         frame_pc_unwind (next_frame));
1439
}
1440
 
1441
static struct gdbarch *
1442
frv_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1443
{
1444
  struct gdbarch *gdbarch;
1445
  struct gdbarch_tdep *var;
1446
  int elf_flags = 0;
1447
 
1448
  /* Check to see if we've already built an appropriate architecture
1449
     object for this executable.  */
1450
  arches = gdbarch_list_lookup_by_info (arches, &info);
1451
  if (arches)
1452
    return arches->gdbarch;
1453
 
1454
  /* Select the right tdep structure for this variant.  */
1455
  var = new_variant ();
1456
  switch (info.bfd_arch_info->mach)
1457
    {
1458
    case bfd_mach_frv:
1459
    case bfd_mach_frvsimple:
1460
    case bfd_mach_fr500:
1461
    case bfd_mach_frvtomcat:
1462
    case bfd_mach_fr550:
1463
      set_variant_num_gprs (var, 64);
1464
      set_variant_num_fprs (var, 64);
1465
      break;
1466
 
1467
    case bfd_mach_fr400:
1468
    case bfd_mach_fr450:
1469
      set_variant_num_gprs (var, 32);
1470
      set_variant_num_fprs (var, 32);
1471
      break;
1472
 
1473
    default:
1474
      /* Never heard of this variant.  */
1475
      return 0;
1476
    }
1477
 
1478
  /* Extract the ELF flags, if available.  */
1479
  if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
1480
    elf_flags = elf_elfheader (info.abfd)->e_flags;
1481
 
1482
  if (elf_flags & EF_FRV_FDPIC)
1483
    set_variant_abi_fdpic (var);
1484
 
1485
  if (elf_flags & EF_FRV_CPU_FR450)
1486
    set_variant_scratch_registers (var);
1487
 
1488
  gdbarch = gdbarch_alloc (&info, var);
1489
 
1490
  set_gdbarch_short_bit (gdbarch, 16);
1491
  set_gdbarch_int_bit (gdbarch, 32);
1492
  set_gdbarch_long_bit (gdbarch, 32);
1493
  set_gdbarch_long_long_bit (gdbarch, 64);
1494
  set_gdbarch_float_bit (gdbarch, 32);
1495
  set_gdbarch_double_bit (gdbarch, 64);
1496
  set_gdbarch_long_double_bit (gdbarch, 64);
1497
  set_gdbarch_ptr_bit (gdbarch, 32);
1498
 
1499
  set_gdbarch_num_regs (gdbarch, frv_num_regs);
1500
  set_gdbarch_num_pseudo_regs (gdbarch, frv_num_pseudo_regs);
1501
 
1502
  set_gdbarch_sp_regnum (gdbarch, sp_regnum);
1503
  set_gdbarch_deprecated_fp_regnum (gdbarch, fp_regnum);
1504
  set_gdbarch_pc_regnum (gdbarch, pc_regnum);
1505
 
1506
  set_gdbarch_register_name (gdbarch, frv_register_name);
1507
  set_gdbarch_register_type (gdbarch, frv_register_type);
1508
  set_gdbarch_register_sim_regno (gdbarch, frv_register_sim_regno);
1509
 
1510
  set_gdbarch_pseudo_register_read (gdbarch, frv_pseudo_register_read);
1511
  set_gdbarch_pseudo_register_write (gdbarch, frv_pseudo_register_write);
1512
 
1513
  set_gdbarch_skip_prologue (gdbarch, frv_skip_prologue);
1514
  set_gdbarch_breakpoint_from_pc (gdbarch, frv_breakpoint_from_pc);
1515
  set_gdbarch_adjust_breakpoint_address
1516
    (gdbarch, frv_adjust_breakpoint_address);
1517
 
1518
  set_gdbarch_return_value (gdbarch, frv_return_value);
1519
 
1520
  /* Frame stuff.  */
1521
  set_gdbarch_unwind_pc (gdbarch, frv_unwind_pc);
1522
  set_gdbarch_unwind_sp (gdbarch, frv_unwind_sp);
1523
  set_gdbarch_frame_align (gdbarch, frv_frame_align);
1524
  frame_base_set_default (gdbarch, &frv_frame_base);
1525
  /* We set the sniffer lower down after the OSABI hooks have been
1526
     established.  */
1527
 
1528
  /* Settings for calling functions in the inferior.  */
1529
  set_gdbarch_push_dummy_call (gdbarch, frv_push_dummy_call);
1530
  set_gdbarch_unwind_dummy_id (gdbarch, frv_unwind_dummy_id);
1531
 
1532
  /* Settings that should be unnecessary.  */
1533
  set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1534
 
1535
  /* Hardware watchpoint / breakpoint support.  */
1536
  switch (info.bfd_arch_info->mach)
1537
    {
1538
    case bfd_mach_frv:
1539
    case bfd_mach_frvsimple:
1540
    case bfd_mach_fr500:
1541
    case bfd_mach_frvtomcat:
1542
      /* fr500-style hardware debugging support.  */
1543
      var->num_hw_watchpoints = 4;
1544
      var->num_hw_breakpoints = 4;
1545
      break;
1546
 
1547
    case bfd_mach_fr400:
1548
    case bfd_mach_fr450:
1549
      /* fr400-style hardware debugging support.  */
1550
      var->num_hw_watchpoints = 2;
1551
      var->num_hw_breakpoints = 4;
1552
      break;
1553
 
1554
    default:
1555
      /* Otherwise, assume we don't have hardware debugging support.  */
1556
      var->num_hw_watchpoints = 0;
1557
      var->num_hw_breakpoints = 0;
1558
      break;
1559
    }
1560
 
1561
  set_gdbarch_print_insn (gdbarch, print_insn_frv);
1562
  if (frv_abi (gdbarch) == FRV_ABI_FDPIC)
1563
    set_gdbarch_convert_from_func_ptr_addr (gdbarch,
1564
                                            frv_convert_from_func_ptr_addr);
1565
 
1566
  set_solib_ops (gdbarch, &frv_so_ops);
1567
 
1568
  /* Hook in ABI-specific overrides, if they have been registered.  */
1569
  gdbarch_init_osabi (info, gdbarch);
1570
 
1571
  /* Set the fallback (prologue based) frame sniffer.  */
1572
  frame_unwind_append_sniffer (gdbarch, frv_frame_sniffer);
1573
 
1574
  /* Enable TLS support.  */
1575
  set_gdbarch_fetch_tls_load_module_address (gdbarch,
1576
                                             frv_fetch_objfile_link_map);
1577
 
1578
  return gdbarch;
1579
}
1580
 
1581
void
1582
_initialize_frv_tdep (void)
1583
{
1584
  register_gdbarch_init (bfd_arch_frv, frv_gdbarch_init);
1585
}

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