OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [gdb/] [ia64-linux-nat.c] - Blame information for rev 321

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn 
/* Functions specific to running gdb native on IA-64 running
2 
   GNU/Linux.
3 
 
4 
   Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
5 
   Free Software Foundation, Inc.
6 
 
7 
   This file is part of GDB.
8 
 
9 
   This program is free software; you can redistribute it and/or modify
10 
   it under the terms of the GNU General Public License as published by
11 
   the Free Software Foundation; either version 3 of the License, or
12 
   (at your option) any later version.
13 
 
14 
   This program is distributed in the hope that it will be useful,
15 
   but WITHOUT ANY WARRANTY; without even the implied warranty of
16 
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 
   GNU General Public License for more details.
18 
 
19 
   You should have received a copy of the GNU General Public License
20 
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
21 
 
22 
#include "defs.h"
23 
#include "gdb_string.h"
24 
#include "inferior.h"
25 
#include "target.h"
26 
#include "gdbcore.h"
27 
#include "regcache.h"
28 
#include "ia64-tdep.h"
29 
#include "linux-nat.h"
30 
 
31 
#include <signal.h>
32 
#include <sys/ptrace.h>
33 
#include "gdb_wait.h"
34 
#ifdef HAVE_SYS_REG_H
35 
#include <sys/reg.h>
36 
#endif
37 
#include <sys/syscall.h>
38 
#include <sys/user.h>
39 
 
40 
#include <asm/ptrace_offsets.h>
41 
#include <sys/procfs.h>
42 
 
43 
/* Prototypes for supply_gregset etc. */
44 
#include "gregset.h"
45 
 
46 
/* These must match the order of the register names.
47 
 
48 
   Some sort of lookup table is needed because the offsets associated
49 
   with the registers are all over the board.  */
50 
 
51 
static int u_offsets[] =
52 
  {
53 
    /* general registers */
54 
    -1,         /* gr0 not available; i.e, it's always zero */
55 
    PT_R1,
56 
    PT_R2,
57 
    PT_R3,
58 
    PT_R4,
59 
    PT_R5,
60 
    PT_R6,
61 
    PT_R7,
62 
    PT_R8,
63 
    PT_R9,
64 
    PT_R10,
65 
    PT_R11,
66 
    PT_R12,
67 
    PT_R13,
68 
    PT_R14,
69 
    PT_R15,
70 
    PT_R16,
71 
    PT_R17,
72 
    PT_R18,
73 
    PT_R19,
74 
    PT_R20,
75 
    PT_R21,
76 
    PT_R22,
77 
    PT_R23,
78 
    PT_R24,
79 
    PT_R25,
80 
    PT_R26,
81 
    PT_R27,
82 
    PT_R28,
83 
    PT_R29,
84 
    PT_R30,
85 
    PT_R31,
86 
    /* gr32 through gr127 not directly available via the ptrace interface */
87 
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
88 
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
89 
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
90 
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
91 
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
92 
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
93 
    /* Floating point registers */
94 
    -1, -1,     /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0) */
95 
    PT_F2,
96 
    PT_F3,
97 
    PT_F4,
98 
    PT_F5,
99 
    PT_F6,
100 
    PT_F7,
101 
    PT_F8,
102 
    PT_F9,
103 
    PT_F10,
104 
    PT_F11,
105 
    PT_F12,
106 
    PT_F13,
107 
    PT_F14,
108 
    PT_F15,
109 
    PT_F16,
110 
    PT_F17,
111 
    PT_F18,
112 
    PT_F19,
113 
    PT_F20,
114 
    PT_F21,
115 
    PT_F22,
116 
    PT_F23,
117 
    PT_F24,
118 
    PT_F25,
119 
    PT_F26,
120 
    PT_F27,
121 
    PT_F28,
122 
    PT_F29,
123 
    PT_F30,
124 
    PT_F31,
125 
    PT_F32,
126 
    PT_F33,
127 
    PT_F34,
128 
    PT_F35,
129 
    PT_F36,
130 
    PT_F37,
131 
    PT_F38,
132 
    PT_F39,
133 
    PT_F40,
134 
    PT_F41,
135 
    PT_F42,
136 
    PT_F43,
137 
    PT_F44,
138 
    PT_F45,
139 
    PT_F46,
140 
    PT_F47,
141 
    PT_F48,
142 
    PT_F49,
143 
    PT_F50,
144 
    PT_F51,
145 
    PT_F52,
146 
    PT_F53,
147 
    PT_F54,
148 
    PT_F55,
149 
    PT_F56,
150 
    PT_F57,
151 
    PT_F58,
152 
    PT_F59,
153 
    PT_F60,
154 
    PT_F61,
155 
    PT_F62,
156 
    PT_F63,
157 
    PT_F64,
158 
    PT_F65,
159 
    PT_F66,
160 
    PT_F67,
161 
    PT_F68,
162 
    PT_F69,
163 
    PT_F70,
164 
    PT_F71,
165 
    PT_F72,
166 
    PT_F73,
167 
    PT_F74,
168 
    PT_F75,
169 
    PT_F76,
170 
    PT_F77,
171 
    PT_F78,
172 
    PT_F79,
173 
    PT_F80,
174 
    PT_F81,
175 
    PT_F82,
176 
    PT_F83,
177 
    PT_F84,
178 
    PT_F85,
179 
    PT_F86,
180 
    PT_F87,
181 
    PT_F88,
182 
    PT_F89,
183 
    PT_F90,
184 
    PT_F91,
185 
    PT_F92,
186 
    PT_F93,
187 
    PT_F94,
188 
    PT_F95,
189 
    PT_F96,
190 
    PT_F97,
191 
    PT_F98,
192 
    PT_F99,
193 
    PT_F100,
194 
    PT_F101,
195 
    PT_F102,
196 
    PT_F103,
197 
    PT_F104,
198 
    PT_F105,
199 
    PT_F106,
200 
    PT_F107,
201 
    PT_F108,
202 
    PT_F109,
203 
    PT_F110,
204 
    PT_F111,
205 
    PT_F112,
206 
    PT_F113,
207 
    PT_F114,
208 
    PT_F115,
209 
    PT_F116,
210 
    PT_F117,
211 
    PT_F118,
212 
    PT_F119,
213 
    PT_F120,
214 
    PT_F121,
215 
    PT_F122,
216 
    PT_F123,
217 
    PT_F124,
218 
    PT_F125,
219 
    PT_F126,
220 
    PT_F127,
221 
    /* predicate registers - we don't fetch these individually */
222 
    -1, -1, -1, -1, -1, -1, -1, -1,
223 
    -1, -1, -1, -1, -1, -1, -1, -1,
224 
    -1, -1, -1, -1, -1, -1, -1, -1,
225 
    -1, -1, -1, -1, -1, -1, -1, -1,
226 
    -1, -1, -1, -1, -1, -1, -1, -1,
227 
    -1, -1, -1, -1, -1, -1, -1, -1,
228 
    -1, -1, -1, -1, -1, -1, -1, -1,
229 
    -1, -1, -1, -1, -1, -1, -1, -1,
230 
    /* branch registers */
231 
    PT_B0,
232 
    PT_B1,
233 
    PT_B2,
234 
    PT_B3,
235 
    PT_B4,
236 
    PT_B5,
237 
    PT_B6,
238 
    PT_B7,
239 
    /* virtual frame pointer and virtual return address pointer */
240 
    -1, -1,
241 
    /* other registers */
242 
    PT_PR,
243 
    PT_CR_IIP,  /* ip */
244 
    PT_CR_IPSR, /* psr */
245 
    PT_CFM,     /* cfm */
246 
    /* kernel registers not visible via ptrace interface (?) */
247 
    -1, -1, -1, -1, -1, -1, -1, -1,
248 
    /* hole */
249 
    -1, -1, -1, -1, -1, -1, -1, -1,
250 
    PT_AR_RSC,
251 
    PT_AR_BSP,
252 
    PT_AR_BSPSTORE,
253 
    PT_AR_RNAT,
254 
    -1,
255 
    -1,         /* Not available: FCR, IA32 floating control register */
256 
    -1, -1,
257 
    -1,         /* Not available: EFLAG */
258 
    -1,         /* Not available: CSD */
259 
    -1,         /* Not available: SSD */
260 
    -1,         /* Not available: CFLG */
261 
    -1,         /* Not available: FSR */
262 
    -1,         /* Not available: FIR */
263 
    -1,         /* Not available: FDR */
264 
    -1,
265 
    PT_AR_CCV,
266 
    -1, -1, -1,
267 
    PT_AR_UNAT,
268 
    -1, -1, -1,
269 
    PT_AR_FPSR,
270 
    -1, -1, -1,
271 
    -1,         /* Not available: ITC */
272 
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
273 
    -1, -1, -1, -1, -1, -1, -1, -1, -1,
274 
    PT_AR_PFS,
275 
    PT_AR_LC,
276 
    -1,         /* Not available: EC, the Epilog Count register */
277 
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
278 
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
279 
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
280 
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
281 
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
282 
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
283 
    -1,
284 
    /* nat bits - not fetched directly; instead we obtain these bits from
285 
       either rnat or unat or from memory. */
286 
    -1, -1, -1, -1, -1, -1, -1, -1,
287 
    -1, -1, -1, -1, -1, -1, -1, -1,
288 
    -1, -1, -1, -1, -1, -1, -1, -1,
289 
    -1, -1, -1, -1, -1, -1, -1, -1,
290 
    -1, -1, -1, -1, -1, -1, -1, -1,
291 
    -1, -1, -1, -1, -1, -1, -1, -1,
292 
    -1, -1, -1, -1, -1, -1, -1, -1,
293 
    -1, -1, -1, -1, -1, -1, -1, -1,
294 
    -1, -1, -1, -1, -1, -1, -1, -1,
295 
    -1, -1, -1, -1, -1, -1, -1, -1,
296 
    -1, -1, -1, -1, -1, -1, -1, -1,
297 
    -1, -1, -1, -1, -1, -1, -1, -1,
298 
    -1, -1, -1, -1, -1, -1, -1, -1,
299 
    -1, -1, -1, -1, -1, -1, -1, -1,
300 
    -1, -1, -1, -1, -1, -1, -1, -1,
301 
    -1, -1, -1, -1, -1, -1, -1, -1,
302 
  };
303 
 
304 
static CORE_ADDR
305 
ia64_register_addr (struct gdbarch *gdbarch, int regno)
306 
{
307 
  CORE_ADDR addr;
308 
 
309 
  if (regno < 0 || regno >= gdbarch_num_regs (gdbarch))
310 
    error (_("Invalid register number %d."), regno);
311 
 
312 
  if (u_offsets[regno] == -1)
313 
    addr = 0;
314 
  else
315 
    addr = (CORE_ADDR) u_offsets[regno];
316 
 
317 
  return addr;
318 
}
319 
 
320 
static int
321 
ia64_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
322 
{
323 
  return regno < 0
324 
         || regno >= gdbarch_num_regs (gdbarch)
325 
         || u_offsets[regno] == -1;
326 
}
327 
 
328 
static int
329 
ia64_cannot_store_register (struct gdbarch *gdbarch, int regno)
330 
{
331 
  /* Rationale behind not permitting stores to bspstore...
332 
 
333 
     The IA-64 architecture provides bspstore and bsp which refer
334 
     memory locations in the RSE's backing store.  bspstore is the
335 
     next location which will be written when the RSE needs to write
336 
     to memory.  bsp is the address at which r32 in the current frame
337 
     would be found if it were written to the backing store.
338 
 
339 
     The IA-64 architecture provides read-only access to bsp and
340 
     read/write access to bspstore (but only when the RSE is in
341 
     the enforced lazy mode).  It should be noted that stores
342 
     to bspstore also affect the value of bsp.  Changing bspstore
343 
     does not affect the number of dirty entries between bspstore
344 
     and bsp, so changing bspstore by N words will also cause bsp
345 
     to be changed by (roughly) N as well.  (It could be N-1 or N+1
346 
     depending upon where the NaT collection bits fall.)
347 
 
348 
     OTOH, the Linux kernel provides read/write access to bsp (and
349 
     currently read/write access to bspstore as well).  But it
350 
     is definitely the case that if you change one, the other
351 
     will change at the same time.  It is more useful to gdb to
352 
     be able to change bsp.  So in order to prevent strange and
353 
     undesirable things from happening when a dummy stack frame
354 
     is popped (after calling an inferior function), we allow
355 
     bspstore to be read, but not written.  (Note that popping
356 
     a (generic) dummy stack frame causes all registers that
357 
     were previously read from the inferior process to be written
358 
     back.)  */
359 
 
360 
  return regno < 0
361 
         || regno >= gdbarch_num_regs (gdbarch)
362 
         || u_offsets[regno] == -1
363 
         || regno == IA64_BSPSTORE_REGNUM;
364 
}
365 
 
366 
void
367 
supply_gregset (struct regcache *regcache, const gregset_t *gregsetp)
368 
{
369 
  int regi;
370 
  const greg_t *regp = (const greg_t *) gregsetp;
371 
 
372 
  for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
373 
    {
374 
      regcache_raw_supply (regcache, regi, regp + (regi - IA64_GR0_REGNUM));
375 
    }
376 
 
377 
  /* FIXME: NAT collection bits are at index 32; gotta deal with these
378 
     somehow... */
379 
 
380 
  regcache_raw_supply (regcache, IA64_PR_REGNUM, regp + 33);
381 
 
382 
  for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
383 
    {
384 
      regcache_raw_supply (regcache, regi,
385 
                           regp + 34 + (regi - IA64_BR0_REGNUM));
386 
    }
387 
 
388 
  regcache_raw_supply (regcache, IA64_IP_REGNUM, regp + 42);
389 
  regcache_raw_supply (regcache, IA64_CFM_REGNUM, regp + 43);
390 
  regcache_raw_supply (regcache, IA64_PSR_REGNUM, regp + 44);
391 
  regcache_raw_supply (regcache, IA64_RSC_REGNUM, regp + 45);
392 
  regcache_raw_supply (regcache, IA64_BSP_REGNUM, regp + 46);
393 
  regcache_raw_supply (regcache, IA64_BSPSTORE_REGNUM, regp + 47);
394 
  regcache_raw_supply (regcache, IA64_RNAT_REGNUM, regp + 48);
395 
  regcache_raw_supply (regcache, IA64_CCV_REGNUM, regp + 49);
396 
  regcache_raw_supply (regcache, IA64_UNAT_REGNUM, regp + 50);
397 
  regcache_raw_supply (regcache, IA64_FPSR_REGNUM, regp + 51);
398 
  regcache_raw_supply (regcache, IA64_PFS_REGNUM, regp + 52);
399 
  regcache_raw_supply (regcache, IA64_LC_REGNUM, regp + 53);
400 
  regcache_raw_supply (regcache, IA64_EC_REGNUM, regp + 54);
401 
}
402 
 
403 
void
404 
fill_gregset (const struct regcache *regcache, gregset_t *gregsetp, int regno)
405 
{
406 
  int regi;
407 
  greg_t *regp = (greg_t *) gregsetp;
408 
 
409 
#define COPY_REG(_idx_,_regi_) \
410 
  if ((regno == -1) || regno == _regi_) \
411 
    regcache_raw_collect (regcache, _regi_, regp + _idx_)
412 
 
413 
  for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
414 
    {
415 
      COPY_REG (regi - IA64_GR0_REGNUM, regi);
416 
    }
417 
 
418 
  /* FIXME: NAT collection bits at index 32? */
419 
 
420 
  COPY_REG (33, IA64_PR_REGNUM);
421 
 
422 
  for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
423 
    {
424 
      COPY_REG (34 + (regi - IA64_BR0_REGNUM), regi);
425 
    }
426 
 
427 
  COPY_REG (42, IA64_IP_REGNUM);
428 
  COPY_REG (43, IA64_CFM_REGNUM);
429 
  COPY_REG (44, IA64_PSR_REGNUM);
430 
  COPY_REG (45, IA64_RSC_REGNUM);
431 
  COPY_REG (46, IA64_BSP_REGNUM);
432 
  COPY_REG (47, IA64_BSPSTORE_REGNUM);
433 
  COPY_REG (48, IA64_RNAT_REGNUM);
434 
  COPY_REG (49, IA64_CCV_REGNUM);
435 
  COPY_REG (50, IA64_UNAT_REGNUM);
436 
  COPY_REG (51, IA64_FPSR_REGNUM);
437 
  COPY_REG (52, IA64_PFS_REGNUM);
438 
  COPY_REG (53, IA64_LC_REGNUM);
439 
  COPY_REG (54, IA64_EC_REGNUM);
440 
}
441 
 
442 
/*  Given a pointer to a floating point register set in /proc format
443 
   (fpregset_t *), unpack the register contents and supply them as gdb's
444 
   idea of the current floating point register values. */
445 
 
446 
void
447 
supply_fpregset (struct regcache *regcache, const fpregset_t *fpregsetp)
448 
{
449 
  int regi;
450 
  const char *from;
451 
 
452 
  for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
453 
    {
454 
      from = (const char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]);
455 
      regcache_raw_supply (regcache, regi, from);
456 
    }
457 
}
458 
 
459 
/*  Given a pointer to a floating point register set in /proc format
460 
   (fpregset_t *), update the register specified by REGNO from gdb's idea
461 
   of the current floating point register set.  If REGNO is -1, update
462 
   them all. */
463 
 
464 
void
465 
fill_fpregset (const struct regcache *regcache,
466 
               fpregset_t *fpregsetp, int regno)
467 
{
468 
  int regi;
469 
 
470 
  for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
471 
    {
472 
      if ((regno == -1) || (regno == regi))
473 
        regcache_raw_collect (regcache, regi,
474 
                              &((*fpregsetp)[regi - IA64_FR0_REGNUM]));
475 
    }
476 
}
477 
 
478 
#define IA64_PSR_DB (1UL << 24)
479 
#define IA64_PSR_DD (1UL << 39)
480 
 
481 
static void
482 
enable_watchpoints_in_psr (ptid_t ptid)
483 
{
484 
  struct regcache *regcache = get_thread_regcache (ptid);
485 
  ULONGEST psr;
486 
 
487 
  regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr);
488 
  if (!(psr & IA64_PSR_DB))
489 
    {
490 
      psr |= IA64_PSR_DB;       /* Set the db bit - this enables hardware
491 
                                   watchpoints and breakpoints. */
492 
      regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr);
493 
    }
494 
}
495 
 
496 
static long debug_registers[8];
497 
 
498 
static void
499 
store_debug_register (ptid_t ptid, int idx, long val)
500 
{
501 
  int tid;
502 
 
503 
  tid = TIDGET (ptid);
504 
  if (tid == 0)
505 
    tid = PIDGET (ptid);
506 
 
507 
  (void) ptrace (PT_WRITE_U, tid, (PTRACE_TYPE_ARG3) (PT_DBR + 8 * idx), val);
508 
}
509 
 
510 
static void
511 
store_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr, long *dbr_mask)
512 
{
513 
  if (dbr_addr)
514 
    store_debug_register (ptid, 2 * idx, *dbr_addr);
515 
  if (dbr_mask)
516 
    store_debug_register (ptid, 2 * idx + 1, *dbr_mask);
517 
}
518 
 
519 
static int
520 
is_power_of_2 (int val)
521 
{
522 
  int i, onecount;
523 
 
524 
  onecount = 0;
525 
  for (i = 0; i < 8 * sizeof (val); i++)
526 
    if (val & (1 << i))
527 
      onecount++;
528 
 
529 
  return onecount <= 1;
530 
}
531 
 
532 
static int
533 
ia64_linux_insert_watchpoint (CORE_ADDR addr, int len, int rw)
534 
{
535 
  struct lwp_info *lp;
536 
  ptid_t ptid;
537 
  int idx;
538 
  long dbr_addr, dbr_mask;
539 
  int max_watchpoints = 4;
540 
 
541 
  if (len <= 0 || !is_power_of_2 (len))
542 
    return -1;
543 
 
544 
  for (idx = 0; idx < max_watchpoints; idx++)
545 
    {
546 
      dbr_mask = debug_registers[idx * 2 + 1];
547 
      if ((dbr_mask & (0x3UL << 62)) == 0)
548 
        {
549 
          /* Exit loop if both r and w bits clear */
550 
          break;
551 
        }
552 
    }
553 
 
554 
  if (idx == max_watchpoints)
555 
    return -1;
556 
 
557 
  dbr_addr = (long) addr;
558 
  dbr_mask = (~(len - 1) & 0x00ffffffffffffffL);  /* construct mask to match */
559 
  dbr_mask |= 0x0800000000000000L;           /* Only match privilege level 3 */
560 
  switch (rw)
561 
    {
562 
    case hw_write:
563 
      dbr_mask |= (1L << 62);                   /* Set w bit */
564 
      break;
565 
    case hw_read:
566 
      dbr_mask |= (1L << 63);                   /* Set r bit */
567 
      break;
568 
    case hw_access:
569 
      dbr_mask |= (3L << 62);                   /* Set both r and w bits */
570 
      break;
571 
    default:
572 
      return -1;
573 
    }
574 
 
575 
  debug_registers[2 * idx] = dbr_addr;
576 
  debug_registers[2 * idx + 1] = dbr_mask;
577 
  ALL_LWPS (lp, ptid)
578 
    {
579 
      store_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);
580 
      enable_watchpoints_in_psr (ptid);
581 
    }
582 
 
583 
  return 0;
584 
}
585 
 
586 
static int
587 
ia64_linux_remove_watchpoint (CORE_ADDR addr, int len, int type)
588 
{
589 
  int idx;
590 
  long dbr_addr, dbr_mask;
591 
  int max_watchpoints = 4;
592 
 
593 
  if (len <= 0 || !is_power_of_2 (len))
594 
    return -1;
595 
 
596 
  for (idx = 0; idx < max_watchpoints; idx++)
597 
    {
598 
      dbr_addr = debug_registers[2 * idx];
599 
      dbr_mask = debug_registers[2 * idx + 1];
600 
      if ((dbr_mask & (0x3UL << 62)) && addr == (CORE_ADDR) dbr_addr)
601 
        {
602 
          struct lwp_info *lp;
603 
          ptid_t ptid;
604 
 
605 
          debug_registers[2 * idx] = 0;
606 
          debug_registers[2 * idx + 1] = 0;
607 
          dbr_addr = 0;
608 
          dbr_mask = 0;
609 
 
610 
          ALL_LWPS (lp, ptid)
611 
            store_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);
612 
 
613 
          return 0;
614 
        }
615 
    }
616 
  return -1;
617 
}
618 
 
619 
static void
620 
ia64_linux_new_thread (ptid_t ptid)
621 
{
622 
  int i, any;
623 
 
624 
  any = 0;
625 
  for (i = 0; i < 8; i++)
626 
    {
627 
      if (debug_registers[i] != 0)
628 
        any = 1;
629 
      store_debug_register (ptid, i, debug_registers[i]);
630 
    }
631 
 
632 
  if (any)
633 
    enable_watchpoints_in_psr (ptid);
634 
}
635 
 
636 
static int
637 
ia64_linux_stopped_data_address (struct target_ops *ops, CORE_ADDR *addr_p)
638 
{
639 
  CORE_ADDR psr;
640 
  struct siginfo *siginfo_p;
641 
  struct regcache *regcache = get_current_regcache ();
642 
 
643 
  siginfo_p = linux_nat_get_siginfo (inferior_ptid);
644 
 
645 
  if (siginfo_p->si_signo != SIGTRAP
646 
      || (siginfo_p->si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
647 
    return 0;
648 
 
649 
  regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr);
650 
  psr |= IA64_PSR_DD;   /* Set the dd bit - this will disable the watchpoint
651 
                           for the next instruction */
652 
  regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr);
653 
 
654 
  *addr_p = (CORE_ADDR)siginfo_p->si_addr;
655 
  return 1;
656 
}
657 
 
658 
static int
659 
ia64_linux_stopped_by_watchpoint (void)
660 
{
661 
  CORE_ADDR addr;
662 
  return ia64_linux_stopped_data_address (&current_target, &addr);
663 
}
664 
 
665 
static int
666 
ia64_linux_can_use_hw_breakpoint (int type, int cnt, int othertype)
667 
{
668 
  return 1;
669 
}
670 
 
671 
 
672 
/* Fetch register REGNUM from the inferior.  */
673 
 
674 
static void
675 
ia64_linux_fetch_register (struct regcache *regcache, int regnum)
676 
{
677 
  struct gdbarch *gdbarch = get_regcache_arch (regcache);
678 
  CORE_ADDR addr;
679 
  size_t size;
680 
  PTRACE_TYPE_RET *buf;
681 
  int pid, i;
682 
 
683 
  if (ia64_cannot_fetch_register (gdbarch, regnum))
684 
    {
685 
      regcache_raw_supply (regcache, regnum, NULL);
686 
      return;
687 
    }
688 
 
689 
  /* Cater for systems like GNU/Linux, that implement threads as
690 
     separate processes.  */
691 
  pid = ptid_get_lwp (inferior_ptid);
692 
  if (pid == 0)
693 
    pid = ptid_get_pid (inferior_ptid);
694 
 
695 
  /* This isn't really an address, but ptrace thinks of it as one.  */
696 
  addr = ia64_register_addr (gdbarch, regnum);
697 
  size = register_size (gdbarch, regnum);
698 
 
699 
  gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0);
700 
  buf = alloca (size);
701 
 
702 
  /* Read the register contents from the inferior a chunk at a time.  */
703 
  for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++)
704 
    {
705 
      errno = 0;
706 
      buf[i] = ptrace (PT_READ_U, pid, (PTRACE_TYPE_ARG3)addr, 0);
707 
      if (errno != 0)
708 
        error (_("Couldn't read register %s (#%d): %s."),
709 
               gdbarch_register_name (gdbarch, regnum),
710 
               regnum, safe_strerror (errno));
711 
 
712 
      addr += sizeof (PTRACE_TYPE_RET);
713 
    }
714 
  regcache_raw_supply (regcache, regnum, buf);
715 
}
716 
 
717 
/* Fetch register REGNUM from the inferior.  If REGNUM is -1, do this
718 
   for all registers.  */
719 
 
720 
static void
721 
ia64_linux_fetch_registers (struct regcache *regcache, int regnum)
722 
{
723 
  if (regnum == -1)
724 
    for (regnum = 0;
725 
         regnum < gdbarch_num_regs (get_regcache_arch (regcache));
726 
         regnum++)
727 
      ia64_linux_fetch_register (regcache, regnum);
728 
  else
729 
    ia64_linux_fetch_register (regcache, regnum);
730 
}
731 
 
732 
/* Store register REGNUM into the inferior.  */
733 
 
734 
static void
735 
ia64_linux_store_register (const struct regcache *regcache, int regnum)
736 
{
737 
  struct gdbarch *gdbarch = get_regcache_arch (regcache);
738 
  CORE_ADDR addr;
739 
  size_t size;
740 
  PTRACE_TYPE_RET *buf;
741 
  int pid, i;
742 
 
743 
  if (ia64_cannot_store_register (gdbarch, regnum))
744 
    return;
745 
 
746 
  /* Cater for systems like GNU/Linux, that implement threads as
747 
     separate processes.  */
748 
  pid = ptid_get_lwp (inferior_ptid);
749 
  if (pid == 0)
750 
    pid = ptid_get_pid (inferior_ptid);
751 
 
752 
  /* This isn't really an address, but ptrace thinks of it as one.  */
753 
  addr = ia64_register_addr (gdbarch, regnum);
754 
  size = register_size (gdbarch, regnum);
755 
 
756 
  gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0);
757 
  buf = alloca (size);
758 
 
759 
  /* Write the register contents into the inferior a chunk at a time.  */
760 
  regcache_raw_collect (regcache, regnum, buf);
761 
  for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++)
762 
    {
763 
      errno = 0;
764 
      ptrace (PT_WRITE_U, pid, (PTRACE_TYPE_ARG3)addr, buf[i]);
765 
      if (errno != 0)
766 
        error (_("Couldn't write register %s (#%d): %s."),
767 
               gdbarch_register_name (gdbarch, regnum),
768 
               regnum, safe_strerror (errno));
769 
 
770 
      addr += sizeof (PTRACE_TYPE_RET);
771 
    }
772 
}
773 
 
774 
/* Store register REGNUM back into the inferior.  If REGNUM is -1, do
775 
   this for all registers.  */
776 
 
777 
static void
778 
ia64_linux_store_registers (struct regcache *regcache, int regnum)
779 
{
780 
  if (regnum == -1)
781 
    for (regnum = 0;
782 
         regnum < gdbarch_num_regs (get_regcache_arch (regcache));
783 
         regnum++)
784 
      ia64_linux_store_register (regcache, regnum);
785 
  else
786 
    ia64_linux_store_register (regcache, regnum);
787 
}
788 
 
789 
 
790 
static LONGEST (*super_xfer_partial) (struct target_ops *, enum target_object,
791 
                                      const char *, gdb_byte *, const gdb_byte *,
792 
                                      ULONGEST, LONGEST);
793 
 
794 
static LONGEST
795 
ia64_linux_xfer_partial (struct target_ops *ops,
796 
                         enum target_object object,
797 
                         const char *annex,
798 
                         gdb_byte *readbuf, const gdb_byte *writebuf,
799 
                         ULONGEST offset, LONGEST len)
800 
{
801 
  if (object == TARGET_OBJECT_UNWIND_TABLE && writebuf == NULL && offset == 0)
802 
    return syscall (__NR_getunwind, readbuf, len);
803 
 
804 
  return super_xfer_partial (ops, object, annex, readbuf, writebuf,
805 
                             offset, len);
806 
}
807 
 
808 
void _initialize_ia64_linux_nat (void);
809 
 
810 
void
811 
_initialize_ia64_linux_nat (void)
812 
{
813 
  struct target_ops *t = linux_target ();
814 
 
815 
  /* Fill in the generic GNU/Linux methods.  */
816 
  t = linux_target ();
817 
 
818 
  /* Override the default fetch/store register routines.  */
819 
  t->to_fetch_registers = ia64_linux_fetch_registers;
820 
  t->to_store_registers = ia64_linux_store_registers;
821 
 
822 
  /* Override the default to_xfer_partial.  */
823 
  super_xfer_partial = t->to_xfer_partial;
824 
  t->to_xfer_partial = ia64_linux_xfer_partial;
825 
 
826 
  /* Override watchpoint routines.  */
827 
 
828 
  /* The IA-64 architecture can step over a watch point (without triggering
829 
     it again) if the "dd" (data debug fault disable) bit in the processor
830 
     status word is set.
831 
 
832 
     This PSR bit is set in ia64_linux_stopped_by_watchpoint when the
833 
     code there has determined that a hardware watchpoint has indeed
834 
     been hit.  The CPU will then be able to execute one instruction
835 
     without triggering a watchpoint. */
836 
 
837 
  t->to_have_steppable_watchpoint = 1;
838 
  t->to_can_use_hw_breakpoint = ia64_linux_can_use_hw_breakpoint;
839 
  t->to_stopped_by_watchpoint = ia64_linux_stopped_by_watchpoint;
840 
  t->to_stopped_data_address = ia64_linux_stopped_data_address;
841 
  t->to_insert_watchpoint = ia64_linux_insert_watchpoint;
842 
  t->to_remove_watchpoint = ia64_linux_remove_watchpoint;
843 
 
844 
  /* Register the target.  */
845 
  linux_nat_add_target (t);
846 
  linux_nat_set_new_thread (t, ia64_linux_new_thread);
847 
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.