Subversion Repositories openrisc_2011-10-31

/* Target-dependent code for Motorola 68HC11 & 68HC12

   Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008

   Free Software Foundation, Inc.

   Contributed by Stephane Carrez, stcarrez@nerim.fr

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify

   it under the terms of the GNU General Public License as published by

   the Free Software Foundation; either version 3 of the License, or

   (at your option) any later version.

   This program is distributed in the hope that it will be useful,

   but WITHOUT ANY WARRANTY; without even the implied warranty of

   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License

   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#include "defs.h"

#include "frame.h"

#include "frame-unwind.h"

#include "frame-base.h"

#include "dwarf2-frame.h"

#include "trad-frame.h"

#include "symtab.h"

#include "gdbtypes.h"

#include "gdbcmd.h"

#include "gdbcore.h"

#include "gdb_string.h"

#include "value.h"

#include "inferior.h"

#include "dis-asm.h"  

#include "symfile.h"

#include "objfiles.h"

#include "arch-utils.h"

#include "regcache.h"

#include "reggroups.h"

#include "target.h"

#include "opcode/m68hc11.h"

#include "elf/m68hc11.h"

#include "elf-bfd.h"

/* Macros for setting and testing a bit in a minimal symbol.

   For 68HC11/68HC12 we have two flags that tell which return

   type the function is using.  This is used for prologue and frame

   analysis to compute correct stack frame layout.

   The MSB of the minimal symbol's "info" field is used for this purpose.

   MSYMBOL_SET_RTC      Actually sets the "RTC" bit.

   MSYMBOL_SET_RTI      Actually sets the "RTI" bit.

   MSYMBOL_IS_RTC       Tests the "RTC" bit in a minimal symbol.

   MSYMBOL_IS_RTI       Tests the "RTC" bit in a minimal symbol.  */

#define MSYMBOL_SET_RTC(msym)                                           \

        MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym))    \

                                        | 0x80000000)

#define MSYMBOL_SET_RTI(msym)                                           \

        MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym))    \

                                        | 0x40000000)

#define MSYMBOL_IS_RTC(msym)                            \

        (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)

#define MSYMBOL_IS_RTI(msym)                            \

        (((long) MSYMBOL_INFO (msym) & 0x40000000) != 0)

enum insn_return_kind {

  RETURN_RTS,

  RETURN_RTC,

  RETURN_RTI

};

/* Register numbers of various important registers.  */

#define HARD_X_REGNUM   0

#define HARD_D_REGNUM   1

#define HARD_Y_REGNUM   2

#define HARD_SP_REGNUM  3

#define HARD_PC_REGNUM  4

#define HARD_A_REGNUM   5

#define HARD_B_REGNUM   6

#define HARD_CCR_REGNUM 7

/* 68HC12 page number register.

   Note: to keep a compatibility with gcc register naming, we must

   not have to rename FP and other soft registers.  The page register

   is a real hard register and must therefore be counted by gdbarch_num_regs.

   For this it has the same number as Z register (which is not used).  */

#define HARD_PAGE_REGNUM 8

#define M68HC11_LAST_HARD_REG (HARD_PAGE_REGNUM)

/* Z is replaced by X or Y by gcc during machine reorg.

   ??? There is no way to get it and even know whether

   it's in X or Y or in ZS.  */

#define SOFT_Z_REGNUM        8

/* Soft registers.  These registers are special.  There are treated

   like normal hard registers by gcc and gdb (ie, within dwarf2 info).

   They are physically located in memory.  */

#define SOFT_FP_REGNUM       9

#define SOFT_TMP_REGNUM     10

#define SOFT_ZS_REGNUM      11

#define SOFT_XY_REGNUM      12

#define SOFT_UNUSED_REGNUM  13

#define SOFT_D1_REGNUM      14

#define SOFT_D32_REGNUM     (SOFT_D1_REGNUM+31)

#define M68HC11_MAX_SOFT_REGS 32

#define M68HC11_NUM_REGS        (8)

#define M68HC11_NUM_PSEUDO_REGS (M68HC11_MAX_SOFT_REGS+5)

#define M68HC11_ALL_REGS        (M68HC11_NUM_REGS+M68HC11_NUM_PSEUDO_REGS)

#define M68HC11_REG_SIZE    (2)

#define M68HC12_NUM_REGS        (9)

#define M68HC12_NUM_PSEUDO_REGS ((M68HC11_MAX_SOFT_REGS+5)+1-1)

#define M68HC12_HARD_PC_REGNUM  (SOFT_D32_REGNUM+1)

struct insn_sequence;

struct gdbarch_tdep

  {

    /* Stack pointer correction value.  For 68hc11, the stack pointer points

       to the next push location.  An offset of 1 must be applied to obtain

       the address where the last value is saved.  For 68hc12, the stack

       pointer points to the last value pushed.  No offset is necessary.  */

    int stack_correction;

    /* Description of instructions in the prologue.  */

    struct insn_sequence *prologue;

    /* True if the page memory bank register is available

       and must be used.  */

    int use_page_register;

    /* ELF flags for ABI.  */

    int elf_flags;

  };

#define STACK_CORRECTION(gdbarch) (gdbarch_tdep (gdbarch)->stack_correction)

#define USE_PAGE_REGISTER(gdbarch) (gdbarch_tdep (gdbarch)->use_page_register)

struct m68hc11_unwind_cache

{

  /* The previous frame's inner most stack address.  Used as this

     frame ID's stack_addr.  */

  CORE_ADDR prev_sp;

  /* The frame's base, optionally used by the high-level debug info.  */

  CORE_ADDR base;

  CORE_ADDR pc;

  int size;

  int prologue_type;

  CORE_ADDR return_pc;

  CORE_ADDR sp_offset;

  int frameless;

  enum insn_return_kind return_kind;

  /* Table indicating the location of each and every register.  */

  struct trad_frame_saved_reg *saved_regs;

};

/* Table of registers for 68HC11.  This includes the hard registers

   and the soft registers used by GCC.  */

static char *

m68hc11_register_names[] =

{

  "x",    "d",    "y",    "sp",   "pc",   "a",    "b",

  "ccr",  "page", "frame","tmp",  "zs",   "xy",   0,

  "d1",   "d2",   "d3",   "d4",   "d5",   "d6",   "d7",

  "d8",   "d9",   "d10",  "d11",  "d12",  "d13",  "d14",

  "d15",  "d16",  "d17",  "d18",  "d19",  "d20",  "d21",

  "d22",  "d23",  "d24",  "d25",  "d26",  "d27",  "d28",

  "d29",  "d30",  "d31",  "d32"

};

struct m68hc11_soft_reg

{

  const char *name;

  CORE_ADDR   addr;

};

static struct m68hc11_soft_reg soft_regs[M68HC11_ALL_REGS];

#define M68HC11_FP_ADDR soft_regs[SOFT_FP_REGNUM].addr

static int soft_min_addr;

static int soft_max_addr;

static int soft_reg_initialized = 0;

/* Look in the symbol table for the address of a pseudo register

   in memory.  If we don't find it, pretend the register is not used

   and not available.  */

static void

m68hc11_get_register_info (struct m68hc11_soft_reg *reg, const char *name)

{

  struct minimal_symbol *msymbol;

  msymbol = lookup_minimal_symbol (name, NULL, NULL);

  if (msymbol)

    {

      reg->addr = SYMBOL_VALUE_ADDRESS (msymbol);

      reg->name = xstrdup (name);

      /* Keep track of the address range for soft registers.  */

      if (reg->addr < (CORE_ADDR) soft_min_addr)

        soft_min_addr = reg->addr;

      if (reg->addr > (CORE_ADDR) soft_max_addr)

        soft_max_addr = reg->addr;

    }

  else

    {

      reg->name = 0;

      reg->addr = 0;

    }

}

/* Initialize the table of soft register addresses according

   to the symbol table.  */

  static void

m68hc11_initialize_register_info (void)

{

  int i;

  if (soft_reg_initialized)

    return;

  soft_min_addr = INT_MAX;

  soft_max_addr = 0;

  for (i = 0; i < M68HC11_ALL_REGS; i++)

    {

      soft_regs[i].name = 0;

    }

  m68hc11_get_register_info (&soft_regs[SOFT_FP_REGNUM], "_.frame");

  m68hc11_get_register_info (&soft_regs[SOFT_TMP_REGNUM], "_.tmp");

  m68hc11_get_register_info (&soft_regs[SOFT_ZS_REGNUM], "_.z");

  soft_regs[SOFT_Z_REGNUM] = soft_regs[SOFT_ZS_REGNUM];

  m68hc11_get_register_info (&soft_regs[SOFT_XY_REGNUM], "_.xy");

  for (i = SOFT_D1_REGNUM; i < M68HC11_MAX_SOFT_REGS; i++)

    {

      char buf[10];

      sprintf (buf, "_.d%d", i - SOFT_D1_REGNUM + 1);

      m68hc11_get_register_info (&soft_regs[i], buf);

    }

  if (soft_regs[SOFT_FP_REGNUM].name == 0)

    warning (_("No frame soft register found in the symbol table.\n"

               "Stack backtrace will not work."));

  soft_reg_initialized = 1;

}

/* Given an address in memory, return the soft register number if

   that address corresponds to a soft register.  Returns -1 if not.  */

static int

m68hc11_which_soft_register (CORE_ADDR addr)

{

  int i;

  if (addr < soft_min_addr || addr > soft_max_addr)

    return -1;

  for (i = SOFT_FP_REGNUM; i < M68HC11_ALL_REGS; i++)

    {

      if (soft_regs[i].name && soft_regs[i].addr == addr)

        return i;

    }

  return -1;

}

/* Fetch a pseudo register.  The 68hc11 soft registers are treated like

   pseudo registers.  They are located in memory.  Translate the register

   fetch into a memory read.  */

static void

m68hc11_pseudo_register_read (struct gdbarch *gdbarch,

                              struct regcache *regcache,

                              int regno, gdb_byte *buf)

{

  /* The PC is a pseudo reg only for 68HC12 with the memory bank

     addressing mode.  */

  if (regno == M68HC12_HARD_PC_REGNUM)

    {

      ULONGEST pc;

      const int regsize = TYPE_LENGTH (builtin_type_uint32);

      regcache_cooked_read_unsigned (regcache, HARD_PC_REGNUM, &pc);

      if (pc >= 0x8000 && pc < 0xc000)

        {

          ULONGEST page;

          regcache_cooked_read_unsigned (regcache, HARD_PAGE_REGNUM, &page);

          pc -= 0x8000;

          pc += (page << 14);

          pc += 0x1000000;

        }

      store_unsigned_integer (buf, regsize, pc);

      return;

    }

  m68hc11_initialize_register_info ();

  /* Fetch a soft register: translate into a memory read.  */

  if (soft_regs[regno].name)

    {

      target_read_memory (soft_regs[regno].addr, buf, 2);

    }

  else

    {

      memset (buf, 0, 2);

    }

}

/* Store a pseudo register.  Translate the register store

   into a memory write.  */

static void

m68hc11_pseudo_register_write (struct gdbarch *gdbarch,

                               struct regcache *regcache,

                               int regno, const gdb_byte *buf)

{

  /* The PC is a pseudo reg only for 68HC12 with the memory bank

     addressing mode.  */

  if (regno == M68HC12_HARD_PC_REGNUM)

    {

      const int regsize = TYPE_LENGTH (builtin_type_uint32);

      char *tmp = alloca (regsize);

      CORE_ADDR pc;

      memcpy (tmp, buf, regsize);

      pc = extract_unsigned_integer (tmp, regsize);

      if (pc >= 0x1000000)

        {

          pc -= 0x1000000;

          regcache_cooked_write_unsigned (regcache, HARD_PAGE_REGNUM,

                                          (pc >> 14) & 0x0ff);

          pc &= 0x03fff;

          regcache_cooked_write_unsigned (regcache, HARD_PC_REGNUM,

                                          pc + 0x8000);

        }

      else

        regcache_cooked_write_unsigned (regcache, HARD_PC_REGNUM, pc);

      return;

    }

  m68hc11_initialize_register_info ();

  /* Store a soft register: translate into a memory write.  */

  if (soft_regs[regno].name)

    {

      const int regsize = 2;

      char *tmp = alloca (regsize);

      memcpy (tmp, buf, regsize);

      target_write_memory (soft_regs[regno].addr, tmp, regsize);

    }

}

static const char *

m68hc11_register_name (struct gdbarch *gdbarch, int reg_nr)

{

  if (reg_nr == M68HC12_HARD_PC_REGNUM && USE_PAGE_REGISTER (gdbarch))

    return "pc";

  if (reg_nr == HARD_PC_REGNUM && USE_PAGE_REGISTER (gdbarch))

    return "ppc";

  if (reg_nr < 0)

    return NULL;

  if (reg_nr >= M68HC11_ALL_REGS)

    return NULL;

  m68hc11_initialize_register_info ();

  /* If we don't know the address of a soft register, pretend it

     does not exist.  */

  if (reg_nr > M68HC11_LAST_HARD_REG && soft_regs[reg_nr].name == 0)

    return NULL;

  return m68hc11_register_names[reg_nr];

}

static const unsigned char *

m68hc11_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,

                            int *lenptr)

{

  static unsigned char breakpoint[] = {0x0};

  *lenptr = sizeof (breakpoint);

  return breakpoint;

}

/* 68HC11 & 68HC12 prologue analysis.

 */

#define MAX_CODES 12

/* 68HC11 opcodes.  */

#undef M6811_OP_PAGE2

#define M6811_OP_PAGE2   (0x18)

#define M6811_OP_LDX     (0xde)

#define M6811_OP_LDX_EXT (0xfe)

#define M6811_OP_PSHX    (0x3c)

#define M6811_OP_STS     (0x9f)

#define M6811_OP_STS_EXT (0xbf)

#define M6811_OP_TSX     (0x30)

#define M6811_OP_XGDX    (0x8f)

#define M6811_OP_ADDD    (0xc3)

#define M6811_OP_TXS     (0x35)

#define M6811_OP_DES     (0x34)

/* 68HC12 opcodes.  */

#define M6812_OP_PAGE2   (0x18)

#define M6812_OP_MOVW    (0x01)

#define M6812_PB_PSHW    (0xae)

#define M6812_OP_STS     (0x5f)

#define M6812_OP_STS_EXT (0x7f)

#define M6812_OP_LEAS    (0x1b)

#define M6812_OP_PSHX    (0x34)

#define M6812_OP_PSHY    (0x35)

/* Operand extraction.  */

#define OP_DIRECT      (0x100) /* 8-byte direct addressing.  */

#define OP_IMM_LOW     (0x200) /* Low part of 16-bit constant/address.  */

#define OP_IMM_HIGH    (0x300) /* High part of 16-bit constant/address.  */

#define OP_PBYTE       (0x400) /* 68HC12 indexed operand.  */

/* Identification of the sequence.  */

enum m6811_seq_type

{

  P_LAST = 0,

  P_SAVE_REG,  /* Save a register on the stack.  */

  P_SET_FRAME, /* Setup the frame pointer.  */

  P_LOCAL_1,   /* Allocate 1 byte for locals.  */

  P_LOCAL_2,   /* Allocate 2 bytes for locals.  */

  P_LOCAL_N    /* Allocate N bytes for locals.  */

};

struct insn_sequence {

  enum m6811_seq_type type;

  unsigned length;

  unsigned short code[MAX_CODES];

};

/* Sequence of instructions in the 68HC11 function prologue.  */

static struct insn_sequence m6811_prologue[] = {

  /* Sequences to save a soft-register.  */

  { P_SAVE_REG, 3, { M6811_OP_LDX, OP_DIRECT,

                     M6811_OP_PSHX } },

  { P_SAVE_REG, 5, { M6811_OP_PAGE2, M6811_OP_LDX, OP_DIRECT,

                     M6811_OP_PAGE2, M6811_OP_PSHX } },

  { P_SAVE_REG, 4, { M6811_OP_LDX_EXT, OP_IMM_HIGH, OP_IMM_LOW,

                     M6811_OP_PSHX } },

  { P_SAVE_REG, 6, { M6811_OP_PAGE2, M6811_OP_LDX_EXT, OP_IMM_HIGH, OP_IMM_LOW,

                     M6811_OP_PAGE2, M6811_OP_PSHX } },

  /* Sequences to allocate local variables.  */

  { P_LOCAL_N,  7, { M6811_OP_TSX,

                     M6811_OP_XGDX,

                     M6811_OP_ADDD, OP_IMM_HIGH, OP_IMM_LOW,

                     M6811_OP_XGDX,

                     M6811_OP_TXS } },

  { P_LOCAL_N, 11, { M6811_OP_PAGE2, M6811_OP_TSX,

                     M6811_OP_PAGE2, M6811_OP_XGDX,

                     M6811_OP_ADDD, OP_IMM_HIGH, OP_IMM_LOW,

                     M6811_OP_PAGE2, M6811_OP_XGDX,

                     M6811_OP_PAGE2, M6811_OP_TXS } },

  { P_LOCAL_1,  1, { M6811_OP_DES } },

  { P_LOCAL_2,  1, { M6811_OP_PSHX } },

  { P_LOCAL_2,  2, { M6811_OP_PAGE2, M6811_OP_PSHX } },

  /* Initialize the frame pointer.  */

  { P_SET_FRAME, 2, { M6811_OP_STS, OP_DIRECT } },

  { P_SET_FRAME, 3, { M6811_OP_STS_EXT, OP_IMM_HIGH, OP_IMM_LOW } },

  { P_LAST, 0, { 0 } }

};

/* Sequence of instructions in the 68HC12 function prologue.  */

static struct insn_sequence m6812_prologue[] = {

  { P_SAVE_REG,  5, { M6812_OP_PAGE2, M6812_OP_MOVW, M6812_PB_PSHW,

                      OP_IMM_HIGH, OP_IMM_LOW } },

  { P_SET_FRAME, 2, { M6812_OP_STS, OP_DIRECT } },

  { P_SET_FRAME, 3, { M6812_OP_STS_EXT, OP_IMM_HIGH, OP_IMM_LOW } },

  { P_LOCAL_N,   2, { M6812_OP_LEAS, OP_PBYTE } },

  { P_LOCAL_2,   1, { M6812_OP_PSHX } },

  { P_LOCAL_2,   1, { M6812_OP_PSHY } },

  { P_LAST, 0 }

};

/* Analyze the sequence of instructions starting at the given address.

   Returns a pointer to the sequence when it is recognized and

   the optional value (constant/address) associated with it.  */

static struct insn_sequence *

m68hc11_analyze_instruction (struct insn_sequence *seq, CORE_ADDR pc,

                             CORE_ADDR *val)

{

  unsigned char buffer[MAX_CODES];

  unsigned bufsize;

  unsigned j;

  CORE_ADDR cur_val;

  short v = 0;

  bufsize = 0;

  for (; seq->type != P_LAST; seq++)

    {

      cur_val = 0;

      for (j = 0; j < seq->length; j++)

        {

          if (bufsize < j + 1)

            {

              buffer[bufsize] = read_memory_unsigned_integer (pc + bufsize,

                                                              1);

              bufsize++;

            }

          /* Continue while we match the opcode.  */

          if (seq->code[j] == buffer[j])

            continue;

          if ((seq->code[j] & 0xf00) == 0)

            break;

          /* Extract a sequence parameter (address or constant).  */

          switch (seq->code[j])

            {

            case OP_DIRECT:

              cur_val = (CORE_ADDR) buffer[j];

              break;

            case OP_IMM_HIGH:

              cur_val = cur_val & 0x0ff;

              cur_val |= (buffer[j] << 8);

              break;

            case OP_IMM_LOW:

              cur_val &= 0x0ff00;

              cur_val |= buffer[j];

              break;

            case OP_PBYTE:

              if ((buffer[j] & 0xE0) == 0x80)

                {

                  v = buffer[j] & 0x1f;

                  if (v & 0x10)

                    v |= 0xfff0;

                }

              else if ((buffer[j] & 0xfe) == 0xf0)

                {

                  v = read_memory_unsigned_integer (pc + j + 1, 1);

                  if (buffer[j] & 1)

                    v |= 0xff00;

                }

              else if (buffer[j] == 0xf2)

                {

                  v = read_memory_unsigned_integer (pc + j + 1, 2);

                }

              cur_val = v;

              break;

            }

        }

      /* We have a full match.  */

      if (j == seq->length)

        {

          *val = cur_val;

          return seq;

        }

    }

  return 0;

}

/* Return the instruction that the function at the PC is using.  */

static enum insn_return_kind

m68hc11_get_return_insn (CORE_ADDR pc)

{

  struct minimal_symbol *sym;

  /* A flag indicating that this is a STO_M68HC12_FAR or STO_M68HC12_INTERRUPT

     function is stored by elfread.c in the high bit of the info field.

     Use this to decide which instruction the function uses to return.  */

  sym = lookup_minimal_symbol_by_pc (pc);

  if (sym == 0)

    return RETURN_RTS;

  if (MSYMBOL_IS_RTC (sym))

    return RETURN_RTC;

  else if (MSYMBOL_IS_RTI (sym))

    return RETURN_RTI;

  else

    return RETURN_RTS;

}

/* Analyze the function prologue to find some information

   about the function:

    - the PC of the first line (for m68hc11_skip_prologue)

    - the offset of the previous frame saved address (from current frame)

    - the soft registers which are pushed.  */

static CORE_ADDR

m68hc11_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,

                       CORE_ADDR current_pc, struct m68hc11_unwind_cache *info)

{

  LONGEST save_addr;

  CORE_ADDR func_end;

  int size;

  int found_frame_point;

  int saved_reg;

  int done = 0;

  struct insn_sequence *seq_table;

  info->size = 0;

  info->sp_offset = 0;

  if (pc >= current_pc)

    return current_pc;

  size = 0;

  m68hc11_initialize_register_info ();

  if (pc == 0)

    {

      info->size = 0;

      return pc;

    }

  seq_table = gdbarch_tdep (gdbarch)->prologue;

  /* The 68hc11 stack is as follows:

     |           |

     +-----------+

     |           |

     | args      |

     |           |

     +-----------+

     | PC-return |

     +-----------+

     | Old frame |

     +-----------+

     |           |

     | Locals    |

     |           |

     +-----------+ <--- current frame

     |           |

     With most processors (like 68K) the previous frame can be computed

     easily because it is always at a fixed offset (see link/unlink).

     That is, locals are accessed with negative offsets, arguments are

     accessed with positive ones.  Since 68hc11 only supports offsets

     in the range [0..255], the frame is defined at the bottom of

     locals (see picture).

     The purpose of the analysis made here is to find out the size

     of locals in this function.  An alternative to this is to use

     DWARF2 info.  This would be better but I don't know how to

     access dwarf2 debug from this function.

     Walk from the function entry point to the point where we save

     the frame.  While walking instructions, compute the size of bytes

     which are pushed.  This gives us the index to access the previous

     frame.

     We limit the search to 128 bytes so that the algorithm is bounded

     in case of random and wrong code.  We also stop and abort if

     we find an instruction which is not supposed to appear in the

     prologue (as generated by gcc 2.95, 2.96).

  */

  func_end = pc + 128;

  found_frame_point = 0;

  info->size = 0;

  save_addr = 0;

  while (!done && pc + 2 < func_end)

    {

      struct insn_sequence *seq;

      CORE_ADDR val;

      seq = m68hc11_analyze_instruction (seq_table, pc, &val);

      if (seq == 0)

        break;

      /* If we are within the instruction group, we can't advance the

         pc nor the stack offset.  Otherwise the caller's stack computed

         from the current stack can be wrong.  */

      if (pc + seq->length > current_pc)

        break;

      pc = pc + seq->length;

      if (seq->type == P_SAVE_REG)

        {

          if (found_frame_point)

            {

              saved_reg = m68hc11_which_soft_register (val);

              if (saved_reg < 0)

                break;

              save_addr -= 2;

              if (info->saved_regs)

                info->saved_regs[saved_reg].addr = save_addr;

            }

          else

            {

              size += 2;

            }

        }

      else if (seq->type == P_SET_FRAME)

        {