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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [gdb/] [m88k-tdep.c] - Blame information for rev 157

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1 24 jeremybenn
/* Target-dependent code for the Motorola 88000 series.
2
 
3
   Copyright (C) 2004, 2005, 2007, 2008 Free Software Foundation, Inc.
4
 
5
   This file is part of GDB.
6
 
7
   This program is free software; you can redistribute it and/or modify
8
   it under the terms of the GNU General Public License as published by
9
   the Free Software Foundation; either version 3 of the License, or
10
   (at your option) any later version.
11
 
12
   This program is distributed in the hope that it will be useful,
13
   but WITHOUT ANY WARRANTY; without even the implied warranty of
14
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
   GNU General Public License for more details.
16
 
17
   You should have received a copy of the GNU General Public License
18
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
19
 
20
#include "defs.h"
21
#include "arch-utils.h"
22
#include "dis-asm.h"
23
#include "frame.h"
24
#include "frame-base.h"
25
#include "frame-unwind.h"
26
#include "gdbcore.h"
27
#include "gdbtypes.h"
28
#include "regcache.h"
29
#include "regset.h"
30
#include "symtab.h"
31
#include "trad-frame.h"
32
#include "value.h"
33
 
34
#include "gdb_assert.h"
35
#include "gdb_string.h"
36
 
37
#include "m88k-tdep.h"
38
 
39
/* Fetch the instruction at PC.  */
40
 
41
static unsigned long
42
m88k_fetch_instruction (CORE_ADDR pc)
43
{
44
  return read_memory_unsigned_integer (pc, 4);
45
}
46
 
47
/* Register information.  */
48
 
49
/* Return the name of register REGNUM.  */
50
 
51
static const char *
52
m88k_register_name (struct gdbarch *gdbarch, int regnum)
53
{
54
  static char *register_names[] =
55
  {
56
    "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
57
    "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
58
    "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
59
    "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
60
    "epsr", "fpsr", "fpcr", "sxip", "snip", "sfip"
61
  };
62
 
63
  if (regnum >= 0 && regnum < ARRAY_SIZE (register_names))
64
    return register_names[regnum];
65
 
66
  return NULL;
67
}
68
 
69
/* Return the GDB type object for the "standard" data type of data in
70
   register REGNUM. */
71
 
72
static struct type *
73
m88k_register_type (struct gdbarch *gdbarch, int regnum)
74
{
75
  /* SXIP, SNIP, SFIP and R1 contain code addresses.  */
76
  if ((regnum >= M88K_SXIP_REGNUM && regnum <= M88K_SFIP_REGNUM)
77
      || regnum == M88K_R1_REGNUM)
78
    return builtin_type_void_func_ptr;
79
 
80
  /* R30 and R31 typically contains data addresses.  */
81
  if (regnum == M88K_R30_REGNUM || regnum == M88K_R31_REGNUM)
82
    return builtin_type_void_data_ptr;
83
 
84
  return builtin_type_int32;
85
}
86
 
87
 
88
static CORE_ADDR
89
m88k_addr_bits_remove (CORE_ADDR addr)
90
{
91
  /* All instructures are 4-byte aligned.  The lower 2 bits of SXIP,
92
     SNIP and SFIP are used for special purposes: bit 0 is the
93
     exception bit and bit 1 is the valid bit.  */
94
  return addr & ~0x3;
95
}
96
 
97
/* Use the program counter to determine the contents and size of a
98
   breakpoint instruction.  Return a pointer to a string of bytes that
99
   encode a breakpoint instruction, store the length of the string in
100
   *LEN and optionally adjust *PC to point to the correct memory
101
   location for inserting the breakpoint.  */
102
 
103
static const gdb_byte *
104
m88k_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len)
105
{
106
  /* tb 0,r0,511 */
107
  static gdb_byte break_insn[] = { 0xf0, 0x00, 0xd1, 0xff };
108
 
109
  *len = sizeof (break_insn);
110
  return break_insn;
111
}
112
 
113
static CORE_ADDR
114
m88k_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
115
{
116
  CORE_ADDR pc;
117
 
118
  pc = frame_unwind_register_unsigned (next_frame, M88K_SXIP_REGNUM);
119
  return m88k_addr_bits_remove (pc);
120
}
121
 
122
static void
123
m88k_write_pc (struct regcache *regcache, CORE_ADDR pc)
124
{
125
  /* According to the MC88100 RISC Microprocessor User's Manual,
126
     section 6.4.3.1.2:
127
 
128
     "... can be made to return to a particular instruction by placing
129
     a valid instruction address in the SNIP and the next sequential
130
     instruction address in the SFIP (with V bits set and E bits
131
     clear).  The rte resumes execution at the instruction pointed to
132
     by the SNIP, then the SFIP."
133
 
134
     The E bit is the least significant bit (bit 0).  The V (valid)
135
     bit is bit 1.  This is why we logical or 2 into the values we are
136
     writing below.  It turns out that SXIP plays no role when
137
     returning from an exception so nothing special has to be done
138
     with it.  We could even (presumably) give it a totally bogus
139
     value.  */
140
 
141
  regcache_cooked_write_unsigned (regcache, M88K_SXIP_REGNUM, pc);
142
  regcache_cooked_write_unsigned (regcache, M88K_SNIP_REGNUM, pc | 2);
143
  regcache_cooked_write_unsigned (regcache, M88K_SFIP_REGNUM, (pc + 4) | 2);
144
}
145
 
146
 
147
/* The functions on this page are intended to be used to classify
148
   function arguments.  */
149
 
150
/* Check whether TYPE is "Integral or Pointer".  */
151
 
152
static int
153
m88k_integral_or_pointer_p (const struct type *type)
154
{
155
  switch (TYPE_CODE (type))
156
    {
157
    case TYPE_CODE_INT:
158
    case TYPE_CODE_BOOL:
159
    case TYPE_CODE_CHAR:
160
    case TYPE_CODE_ENUM:
161
    case TYPE_CODE_RANGE:
162
      {
163
        /* We have byte, half-word, word and extended-word/doubleword
164
           integral types.  */
165
        int len = TYPE_LENGTH (type);
166
        return (len == 1 || len == 2 || len == 4 || len == 8);
167
      }
168
      return 1;
169
    case TYPE_CODE_PTR:
170
    case TYPE_CODE_REF:
171
      {
172
        /* Allow only 32-bit pointers.  */
173
        return (TYPE_LENGTH (type) == 4);
174
      }
175
      return 1;
176
    default:
177
      break;
178
    }
179
 
180
  return 0;
181
}
182
 
183
/* Check whether TYPE is "Floating".  */
184
 
185
static int
186
m88k_floating_p (const struct type *type)
187
{
188
  switch (TYPE_CODE (type))
189
    {
190
    case TYPE_CODE_FLT:
191
      {
192
        int len = TYPE_LENGTH (type);
193
        return (len == 4 || len == 8);
194
      }
195
    default:
196
      break;
197
    }
198
 
199
  return 0;
200
}
201
 
202
/* Check whether TYPE is "Structure or Union".  */
203
 
204
static int
205
m88k_structure_or_union_p (const struct type *type)
206
{
207
  switch (TYPE_CODE (type))
208
    {
209
    case TYPE_CODE_STRUCT:
210
    case TYPE_CODE_UNION:
211
      return 1;
212
    default:
213
      break;
214
    }
215
 
216
  return 0;
217
}
218
 
219
/* Check whether TYPE has 8-byte alignment.  */
220
 
221
static int
222
m88k_8_byte_align_p (struct type *type)
223
{
224
  if (m88k_structure_or_union_p (type))
225
    {
226
      int i;
227
 
228
      for (i = 0; i < TYPE_NFIELDS (type); i++)
229
        {
230
          struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i));
231
 
232
          if (m88k_8_byte_align_p (subtype))
233
            return 1;
234
        }
235
    }
236
 
237
  if (m88k_integral_or_pointer_p (type) || m88k_floating_p (type))
238
    return (TYPE_LENGTH (type) == 8);
239
 
240
  return 0;
241
}
242
 
243
/* Check whether TYPE can be passed in a register.  */
244
 
245
static int
246
m88k_in_register_p (struct type *type)
247
{
248
  if (m88k_integral_or_pointer_p (type) || m88k_floating_p (type))
249
    return 1;
250
 
251
  if (m88k_structure_or_union_p (type) && TYPE_LENGTH (type) == 4)
252
    return 1;
253
 
254
  return 0;
255
}
256
 
257
static CORE_ADDR
258
m88k_store_arguments (struct regcache *regcache, int nargs,
259
                      struct value **args, CORE_ADDR sp)
260
{
261
  int num_register_words = 0;
262
  int num_stack_words = 0;
263
  int i;
264
 
265
  for (i = 0; i < nargs; i++)
266
    {
267
      struct type *type = value_type (args[i]);
268
      int len = TYPE_LENGTH (type);
269
 
270
      if (m88k_integral_or_pointer_p (type) && len < 4)
271
        {
272
          args[i] = value_cast (builtin_type_int32, args[i]);
273
          type = value_type (args[i]);
274
          len = TYPE_LENGTH (type);
275
        }
276
 
277
      if (m88k_in_register_p (type))
278
        {
279
          int num_words = 0;
280
 
281
          if (num_register_words % 2 == 1 && m88k_8_byte_align_p (type))
282
            num_words++;
283
 
284
          num_words += ((len + 3) / 4);
285
          if (num_register_words + num_words <= 8)
286
            {
287
              num_register_words += num_words;
288
              continue;
289
            }
290
 
291
          /* We've run out of available registers.  Pass the argument
292
             on the stack.  */
293
        }
294
 
295
      if (num_stack_words % 2 == 1 && m88k_8_byte_align_p (type))
296
        num_stack_words++;
297
 
298
      num_stack_words += ((len + 3) / 4);
299
    }
300
 
301
  /* Allocate stack space.  */
302
  sp = align_down (sp - 32 - num_stack_words * 4, 16);
303
  num_stack_words = num_register_words = 0;
304
 
305
  for (i = 0; i < nargs; i++)
306
    {
307
      const bfd_byte *valbuf = value_contents (args[i]);
308
      struct type *type = value_type (args[i]);
309
      int len = TYPE_LENGTH (type);
310
      int stack_word = num_stack_words;
311
 
312
      if (m88k_in_register_p (type))
313
        {
314
          int register_word = num_register_words;
315
 
316
          if (register_word % 2 == 1 && m88k_8_byte_align_p (type))
317
            register_word++;
318
 
319
          gdb_assert (len == 4 || len == 8);
320
 
321
          if (register_word + len / 8 < 8)
322
            {
323
              int regnum = M88K_R2_REGNUM + register_word;
324
 
325
              regcache_raw_write (regcache, regnum, valbuf);
326
              if (len > 4)
327
                regcache_raw_write (regcache, regnum + 1, valbuf + 4);
328
 
329
              num_register_words = (register_word + len / 4);
330
              continue;
331
            }
332
        }
333
 
334
      if (stack_word % 2 == -1 && m88k_8_byte_align_p (type))
335
        stack_word++;
336
 
337
      write_memory (sp + stack_word * 4, valbuf, len);
338
      num_stack_words = (stack_word + (len + 3) / 4);
339
    }
340
 
341
  return sp;
342
}
343
 
344
static CORE_ADDR
345
m88k_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
346
                      struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
347
                      struct value **args, CORE_ADDR sp, int struct_return,
348
                      CORE_ADDR struct_addr)
349
{
350
  /* Set up the function arguments.  */
351
  sp = m88k_store_arguments (regcache, nargs, args, sp);
352
  gdb_assert (sp % 16 == 0);
353
 
354
  /* Store return value address.  */
355
  if (struct_return)
356
    regcache_raw_write_unsigned (regcache, M88K_R12_REGNUM, struct_addr);
357
 
358
  /* Store the stack pointer and return address in the appropriate
359
     registers.  */
360
  regcache_raw_write_unsigned (regcache, M88K_R31_REGNUM, sp);
361
  regcache_raw_write_unsigned (regcache, M88K_R1_REGNUM, bp_addr);
362
 
363
  /* Return the stack pointer.  */
364
  return sp;
365
}
366
 
367
static struct frame_id
368
m88k_unwind_dummy_id (struct gdbarch *arch, struct frame_info *next_frame)
369
{
370
  CORE_ADDR sp;
371
 
372
  sp = frame_unwind_register_unsigned (next_frame, M88K_R31_REGNUM);
373
  return frame_id_build (sp, frame_pc_unwind (next_frame));
374
}
375
 
376
 
377
/* Determine, for architecture GDBARCH, how a return value of TYPE
378
   should be returned.  If it is supposed to be returned in registers,
379
   and READBUF is non-zero, read the appropriate value from REGCACHE,
380
   and copy it into READBUF.  If WRITEBUF is non-zero, write the value
381
   from WRITEBUF into REGCACHE.  */
382
 
383
static enum return_value_convention
384
m88k_return_value (struct gdbarch *gdbarch, struct type *type,
385
                   struct regcache *regcache, gdb_byte *readbuf,
386
                   const gdb_byte *writebuf)
387
{
388
  int len = TYPE_LENGTH (type);
389
  gdb_byte buf[8];
390
 
391
  if (!m88k_integral_or_pointer_p (type) && !m88k_floating_p (type))
392
    return RETURN_VALUE_STRUCT_CONVENTION;
393
 
394
  if (readbuf)
395
    {
396
      /* Read the contents of R2 and (if necessary) R3.  */
397
      regcache_cooked_read (regcache, M88K_R2_REGNUM, buf);
398
      if (len > 4)
399
        {
400
          regcache_cooked_read (regcache, M88K_R3_REGNUM, buf + 4);
401
          gdb_assert (len == 8);
402
          memcpy (readbuf, buf, len);
403
        }
404
      else
405
        {
406
          /* Just stripping off any unused bytes should preserve the
407
             signed-ness just fine.  */
408
          memcpy (readbuf, buf + 4 - len, len);
409
        }
410
    }
411
 
412
  if (writebuf)
413
    {
414
      /* Read the contents to R2 and (if necessary) R3.  */
415
      if (len > 4)
416
        {
417
          gdb_assert (len == 8);
418
          memcpy (buf, writebuf, 8);
419
          regcache_cooked_write (regcache, M88K_R3_REGNUM, buf + 4);
420
        }
421
      else
422
        {
423
          /* ??? Do we need to do any sign-extension here?  */
424
          memcpy (buf + 4 - len, writebuf, len);
425
        }
426
      regcache_cooked_write (regcache, M88K_R2_REGNUM, buf);
427
    }
428
 
429
  return RETURN_VALUE_REGISTER_CONVENTION;
430
}
431
 
432
/* Default frame unwinder.  */
433
 
434
struct m88k_frame_cache
435
{
436
  /* Base address.  */
437
  CORE_ADDR base;
438
  CORE_ADDR pc;
439
 
440
  int sp_offset;
441
  int fp_offset;
442
 
443
  /* Table of saved registers.  */
444
  struct trad_frame_saved_reg *saved_regs;
445
};
446
 
447
/* Prologue analysis.  */
448
 
449
/* Macros for extracting fields from instructions.  */
450
 
451
#define BITMASK(pos, width) (((0x1 << (width)) - 1) << (pos))
452
#define EXTRACT_FIELD(val, pos, width) ((val) >> (pos) & BITMASK (0, width))
453
#define SUBU_OFFSET(x)  ((unsigned)(x & 0xFFFF))
454
#define ST_OFFSET(x)    ((unsigned)((x) & 0xFFFF))
455
#define ST_SRC(x)       EXTRACT_FIELD ((x), 21, 5)
456
#define ADDU_OFFSET(x)  ((unsigned)(x & 0xFFFF))
457
 
458
/* Possible actions to be taken by the prologue analyzer for the
459
   instructions it encounters.  */
460
 
461
enum m88k_prologue_insn_action
462
{
463
  M88K_PIA_SKIP,                /* Ignore.  */
464
  M88K_PIA_NOTE_ST,             /* Note register store.  */
465
  M88K_PIA_NOTE_STD,            /* Note register pair store.  */
466
  M88K_PIA_NOTE_SP_ADJUSTMENT,  /* Note stack pointer adjustment.  */
467
  M88K_PIA_NOTE_FP_ASSIGNMENT,  /* Note frame pointer assignment.  */
468
  M88K_PIA_NOTE_BRANCH,         /* Note branch.  */
469
  M88K_PIA_NOTE_PROLOGUE_END    /* Note end of prologue.  */
470
};
471
 
472
/* Table of instructions that may comprise a function prologue.  */
473
 
474
struct m88k_prologue_insn
475
{
476
  unsigned long insn;
477
  unsigned long mask;
478
  enum m88k_prologue_insn_action action;
479
};
480
 
481
struct m88k_prologue_insn m88k_prologue_insn_table[] =
482
{
483
  /* Various register move instructions.  */
484
  { 0x58000000, 0xf800ffff, M88K_PIA_SKIP },     /* or/or.u with immed of 0 */
485
  { 0xf4005800, 0xfc1fffe0, M88K_PIA_SKIP },     /* or rd,r0,rs */
486
  { 0xf4005800, 0xfc00ffff, M88K_PIA_SKIP },     /* or rd,rs,r0 */
487
 
488
  /* Various other instructions.  */
489
  { 0x58000000, 0xf8000000, M88K_PIA_SKIP },     /* or/or.u */
490
 
491
  /* Stack pointer setup: "subu sp,sp,n" where n is a multiple of 8.  */
492
  { 0x67ff0000, 0xffff0007, M88K_PIA_NOTE_SP_ADJUSTMENT },
493
 
494
  /* Frame pointer assignment: "addu r30,r31,n".  */
495
  { 0x63df0000, 0xffff0000, M88K_PIA_NOTE_FP_ASSIGNMENT },
496
 
497
  /* Store to stack instructions; either "st rx,sp,n" or "st.d rx,sp,n".  */
498
  { 0x241f0000, 0xfc1f0000, M88K_PIA_NOTE_ST },  /* st rx,sp,n */
499
  { 0x201f0000, 0xfc1f0000, M88K_PIA_NOTE_STD }, /* st.d rs,sp,n */
500
 
501
  /* Instructions needed for setting up r25 for pic code.  */
502
  { 0x5f200000, 0xffff0000, M88K_PIA_SKIP },     /* or.u r25,r0,offset_high */
503
  { 0xcc000002, 0xffffffff, M88K_PIA_SKIP },     /* bsr.n Lab */
504
  { 0x5b390000, 0xffff0000, M88K_PIA_SKIP },     /* or r25,r25,offset_low */
505
  { 0xf7396001, 0xffffffff, M88K_PIA_SKIP },     /* Lab: addu r25,r25,r1 */
506
 
507
  /* Various branch or jump instructions which have a delay slot --
508
     these do not form part of the prologue, but the instruction in
509
     the delay slot might be a store instruction which should be
510
     noted.  */
511
  { 0xc4000000, 0xe4000000, M88K_PIA_NOTE_BRANCH },
512
                                      /* br.n, bsr.n, bb0.n, or bb1.n */
513
  { 0xec000000, 0xfc000000, M88K_PIA_NOTE_BRANCH }, /* bcnd.n */
514
  { 0xf400c400, 0xfffff7e0, M88K_PIA_NOTE_BRANCH }, /* jmp.n or jsr.n */
515
 
516
  /* Catch all.  Ends prologue analysis.  */
517
  { 0x00000000, 0x00000000, M88K_PIA_NOTE_PROLOGUE_END }
518
};
519
 
520
/* Do a full analysis of the function prologue at PC and update CACHE
521
   accordingly.  Bail out early if LIMIT is reached.  Return the
522
   address where the analysis stopped.  If LIMIT points beyond the
523
   function prologue, the return address should be the end of the
524
   prologue.  */
525
 
526
static CORE_ADDR
527
m88k_analyze_prologue (CORE_ADDR pc, CORE_ADDR limit,
528
                       struct m88k_frame_cache *cache)
529
{
530
  CORE_ADDR end = limit;
531
 
532
  /* Provide a dummy cache if necessary.  */
533
  if (cache == NULL)
534
    {
535
      size_t sizeof_saved_regs =
536
        (M88K_R31_REGNUM + 1) * sizeof (struct trad_frame_saved_reg);
537
 
538
      cache = alloca (sizeof (struct m88k_frame_cache));
539
      cache->saved_regs = alloca (sizeof_saved_regs);
540
 
541
      /* We only initialize the members we care about.  */
542
      cache->saved_regs[M88K_R1_REGNUM].addr = -1;
543
      cache->fp_offset = -1;
544
    }
545
 
546
  while (pc < limit)
547
    {
548
      struct m88k_prologue_insn *pi = m88k_prologue_insn_table;
549
      unsigned long insn = m88k_fetch_instruction (pc);
550
 
551
      while ((insn & pi->mask) != pi->insn)
552
        pi++;
553
 
554
      switch (pi->action)
555
        {
556
        case M88K_PIA_SKIP:
557
          /* If we have a frame pointer, and R1 has been saved,
558
             consider this instruction as not being part of the
559
             prologue.  */
560
          if (cache->fp_offset != -1
561
              && cache->saved_regs[M88K_R1_REGNUM].addr != -1)
562
            return min (pc, end);
563
          break;
564
 
565
        case M88K_PIA_NOTE_ST:
566
        case M88K_PIA_NOTE_STD:
567
          /* If no frame has been allocated, the stores aren't part of
568
             the prologue.  */
569
          if (cache->sp_offset == 0)
570
            return min (pc, end);
571
 
572
          /* Record location of saved registers.  */
573
          {
574
            int regnum = ST_SRC (insn) + M88K_R0_REGNUM;
575
            ULONGEST offset = ST_OFFSET (insn);
576
 
577
            cache->saved_regs[regnum].addr = offset;
578
            if (pi->action == M88K_PIA_NOTE_STD && regnum < M88K_R31_REGNUM)
579
              cache->saved_regs[regnum + 1].addr = offset + 4;
580
          }
581
          break;
582
 
583
        case M88K_PIA_NOTE_SP_ADJUSTMENT:
584
          /* A second stack pointer adjustment isn't part of the
585
             prologue.  */
586
          if (cache->sp_offset != 0)
587
            return min (pc, end);
588
 
589
          /* Store stack pointer adjustment.  */
590
          cache->sp_offset = -SUBU_OFFSET (insn);
591
          break;
592
 
593
        case M88K_PIA_NOTE_FP_ASSIGNMENT:
594
          /* A second frame pointer assignment isn't part of the
595
             prologue.  */
596
          if (cache->fp_offset != -1)
597
            return min (pc, end);
598
 
599
          /* Record frame pointer assignment.  */
600
          cache->fp_offset = ADDU_OFFSET (insn);
601
          break;
602
 
603
        case M88K_PIA_NOTE_BRANCH:
604
          /* The branch instruction isn't part of the prologue, but
605
             the instruction in the delay slot might be.  Limit the
606
             prologue analysis to the delay slot and record the branch
607
             instruction as the end of the prologue.  */
608
          limit = min (limit, pc + 2 * M88K_INSN_SIZE);
609
          end = pc;
610
          break;
611
 
612
        case M88K_PIA_NOTE_PROLOGUE_END:
613
          return min (pc, end);
614
        }
615
 
616
      pc += M88K_INSN_SIZE;
617
    }
618
 
619
  return end;
620
}
621
 
622
/* An upper limit to the size of the prologue.  */
623
const int m88k_max_prologue_size = 128 * M88K_INSN_SIZE;
624
 
625
/* Return the address of first real instruction of the function
626
   starting at PC.  */
627
 
628
static CORE_ADDR
629
m88k_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
630
{
631
  struct symtab_and_line sal;
632
  CORE_ADDR func_start, func_end;
633
 
634
  /* This is the preferred method, find the end of the prologue by
635
     using the debugging information.  */
636
  if (find_pc_partial_function (pc, NULL, &func_start, &func_end))
637
    {
638
      sal = find_pc_line (func_start, 0);
639
 
640
      if (sal.end < func_end && pc <= sal.end)
641
        return sal.end;
642
    }
643
 
644
  return m88k_analyze_prologue (pc, pc + m88k_max_prologue_size, NULL);
645
}
646
 
647
struct m88k_frame_cache *
648
m88k_frame_cache (struct frame_info *next_frame, void **this_cache)
649
{
650
  struct m88k_frame_cache *cache;
651
  CORE_ADDR frame_sp;
652
 
653
  if (*this_cache)
654
    return *this_cache;
655
 
656
  cache = FRAME_OBSTACK_ZALLOC (struct m88k_frame_cache);
657
  cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
658
  cache->fp_offset = -1;
659
 
660
  cache->pc = frame_func_unwind (next_frame, NORMAL_FRAME);
661
  if (cache->pc != 0)
662
    m88k_analyze_prologue (cache->pc, frame_pc_unwind (next_frame), cache);
663
 
664
  /* Calculate the stack pointer used in the prologue.  */
665
  if (cache->fp_offset != -1)
666
    {
667
      CORE_ADDR fp;
668
 
669
      fp = frame_unwind_register_unsigned (next_frame, M88K_R30_REGNUM);
670
      frame_sp = fp - cache->fp_offset;
671
    }
672
  else
673
    {
674
      /* If we know where the return address is saved, we can take a
675
         solid guess at what the frame pointer should be.  */
676
      if (cache->saved_regs[M88K_R1_REGNUM].addr != -1)
677
        cache->fp_offset = cache->saved_regs[M88K_R1_REGNUM].addr - 4;
678
      frame_sp = frame_unwind_register_unsigned (next_frame, M88K_R31_REGNUM);
679
    }
680
 
681
  /* Now that we know the stack pointer, adjust the location of the
682
     saved registers.  */
683
  {
684
    int regnum;
685
 
686
    for (regnum = M88K_R0_REGNUM; regnum < M88K_R31_REGNUM; regnum ++)
687
      if (cache->saved_regs[regnum].addr != -1)
688
        cache->saved_regs[regnum].addr += frame_sp;
689
  }
690
 
691
  /* Calculate the frame's base.  */
692
  cache->base = frame_sp - cache->sp_offset;
693
  trad_frame_set_value (cache->saved_regs, M88K_R31_REGNUM, cache->base);
694
 
695
  /* Identify SXIP with the return address in R1.  */
696
  cache->saved_regs[M88K_SXIP_REGNUM] = cache->saved_regs[M88K_R1_REGNUM];
697
 
698
  *this_cache = cache;
699
  return cache;
700
}
701
 
702
static void
703
m88k_frame_this_id (struct frame_info *next_frame, void **this_cache,
704
                    struct frame_id *this_id)
705
{
706
  struct m88k_frame_cache *cache = m88k_frame_cache (next_frame, this_cache);
707
 
708
  /* This marks the outermost frame.  */
709
  if (cache->base == 0)
710
    return;
711
 
712
  (*this_id) = frame_id_build (cache->base, cache->pc);
713
}
714
 
715
static void
716
m88k_frame_prev_register (struct frame_info *next_frame, void **this_cache,
717
                          int regnum, int *optimizedp,
718
                          enum lval_type *lvalp, CORE_ADDR *addrp,
719
                          int *realnump, gdb_byte *valuep)
720
{
721
  struct m88k_frame_cache *cache = m88k_frame_cache (next_frame, this_cache);
722
 
723
  if (regnum == M88K_SNIP_REGNUM || regnum == M88K_SFIP_REGNUM)
724
    {
725
      if (valuep)
726
        {
727
          CORE_ADDR pc;
728
 
729
          trad_frame_get_prev_register (next_frame, cache->saved_regs,
730
                                        M88K_SXIP_REGNUM, optimizedp,
731
                                        lvalp, addrp, realnump, valuep);
732
 
733
          pc = extract_unsigned_integer (valuep, 4);
734
          if (regnum == M88K_SFIP_REGNUM)
735
            pc += 4;
736
          store_unsigned_integer (valuep, 4, pc + 4);
737
        }
738
 
739
      /* It's a computed value.  */
740
      *optimizedp = 0;
741
      *lvalp = not_lval;
742
      *addrp = 0;
743
      *realnump = -1;
744
      return;
745
    }
746
 
747
  trad_frame_get_prev_register (next_frame, cache->saved_regs, regnum,
748
                                optimizedp, lvalp, addrp, realnump, valuep);
749
}
750
 
751
static const struct frame_unwind m88k_frame_unwind =
752
{
753
  NORMAL_FRAME,
754
  m88k_frame_this_id,
755
  m88k_frame_prev_register
756
};
757
 
758
static const struct frame_unwind *
759
m88k_frame_sniffer (struct frame_info *next_frame)
760
{
761
  return &m88k_frame_unwind;
762
}
763
 
764
 
765
static CORE_ADDR
766
m88k_frame_base_address (struct frame_info *next_frame, void **this_cache)
767
{
768
  struct m88k_frame_cache *cache = m88k_frame_cache (next_frame, this_cache);
769
 
770
  if (cache->fp_offset != -1)
771
    return cache->base + cache->sp_offset + cache->fp_offset;
772
 
773
  return 0;
774
}
775
 
776
static const struct frame_base m88k_frame_base =
777
{
778
  &m88k_frame_unwind,
779
  m88k_frame_base_address,
780
  m88k_frame_base_address,
781
  m88k_frame_base_address
782
};
783
 
784
 
785
/* Core file support.  */
786
 
787
/* Supply register REGNUM from the buffer specified by GREGS and LEN
788
   in the general-purpose register set REGSET to register cache
789
   REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */
790
 
791
static void
792
m88k_supply_gregset (const struct regset *regset,
793
                     struct regcache *regcache,
794
                     int regnum, const void *gregs, size_t len)
795
{
796
  const gdb_byte *regs = gregs;
797
  int i;
798
 
799
  for (i = 0; i < M88K_NUM_REGS; i++)
800
    {
801
      if (regnum == i || regnum == -1)
802
        regcache_raw_supply (regcache, i, regs + i * 4);
803
    }
804
}
805
 
806
/* Motorola 88000 register set.  */
807
 
808
static struct regset m88k_gregset =
809
{
810
  NULL,
811
  m88k_supply_gregset
812
};
813
 
814
/* Return the appropriate register set for the core section identified
815
   by SECT_NAME and SECT_SIZE.  */
816
 
817
static const struct regset *
818
m88k_regset_from_core_section (struct gdbarch *gdbarch,
819
                               const char *sect_name, size_t sect_size)
820
{
821
  if (strcmp (sect_name, ".reg") == 0 && sect_size >= M88K_NUM_REGS * 4)
822
    return &m88k_gregset;
823
 
824
  return NULL;
825
}
826
 
827
 
828
static struct gdbarch *
829
m88k_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
830
{
831
  struct gdbarch *gdbarch;
832
 
833
  /* If there is already a candidate, use it.  */
834
  arches = gdbarch_list_lookup_by_info (arches, &info);
835
  if (arches != NULL)
836
    return arches->gdbarch;
837
 
838
  /* Allocate space for the new architecture.  */
839
  gdbarch = gdbarch_alloc (&info, NULL);
840
 
841
  /* There is no real `long double'.  */
842
  set_gdbarch_long_double_bit (gdbarch, 64);
843
  set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
844
 
845
  set_gdbarch_num_regs (gdbarch, M88K_NUM_REGS);
846
  set_gdbarch_register_name (gdbarch, m88k_register_name);
847
  set_gdbarch_register_type (gdbarch, m88k_register_type);
848
 
849
  /* Register numbers of various important registers.  */
850
  set_gdbarch_sp_regnum (gdbarch, M88K_R31_REGNUM);
851
  set_gdbarch_pc_regnum (gdbarch, M88K_SXIP_REGNUM);
852
 
853
  /* Core file support.  */
854
  set_gdbarch_regset_from_core_section
855
    (gdbarch, m88k_regset_from_core_section);
856
 
857
  set_gdbarch_print_insn (gdbarch, print_insn_m88k);
858
 
859
  set_gdbarch_skip_prologue (gdbarch, m88k_skip_prologue);
860
 
861
  /* Stack grows downward.  */
862
  set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
863
 
864
  /* Call dummy code.  */
865
  set_gdbarch_push_dummy_call (gdbarch, m88k_push_dummy_call);
866
  set_gdbarch_unwind_dummy_id (gdbarch, m88k_unwind_dummy_id);
867
 
868
  /* Return value info */
869
  set_gdbarch_return_value (gdbarch, m88k_return_value);
870
 
871
  set_gdbarch_addr_bits_remove (gdbarch, m88k_addr_bits_remove);
872
  set_gdbarch_breakpoint_from_pc (gdbarch, m88k_breakpoint_from_pc);
873
  set_gdbarch_unwind_pc (gdbarch, m88k_unwind_pc);
874
  set_gdbarch_write_pc (gdbarch, m88k_write_pc);
875
 
876
  frame_base_set_default (gdbarch, &m88k_frame_base);
877
  frame_unwind_append_sniffer (gdbarch, m88k_frame_sniffer);
878
 
879
  return gdbarch;
880
}
881
 
882
 
883
/* Provide a prototype to silence -Wmissing-prototypes.  */
884
void _initialize_m88k_tdep (void);
885
 
886
void
887
_initialize_m88k_tdep (void)
888
{
889
  gdbarch_register (bfd_arch_m88k, m88k_gdbarch_init, NULL);
890
}

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