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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [gdb/] [sparc-tdep.c] - Blame information for rev 157

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1 24 jeremybenn
/* Target-dependent code for SPARC.
2
 
3
   Copyright (C) 2003, 2004, 2005, 2006, 2007, 2008
4
   Free Software Foundation, Inc.
5
 
6
   This file is part of GDB.
7
 
8
   This program is free software; you can redistribute it and/or modify
9
   it under the terms of the GNU General Public License as published by
10
   the Free Software Foundation; either version 3 of the License, or
11
   (at your option) any later version.
12
 
13
   This program is distributed in the hope that it will be useful,
14
   but WITHOUT ANY WARRANTY; without even the implied warranty of
15
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
   GNU General Public License for more details.
17
 
18
   You should have received a copy of the GNU General Public License
19
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
20
 
21
#include "defs.h"
22
#include "arch-utils.h"
23
#include "dis-asm.h"
24
#include "dwarf2-frame.h"
25
#include "floatformat.h"
26
#include "frame.h"
27
#include "frame-base.h"
28
#include "frame-unwind.h"
29
#include "gdbcore.h"
30
#include "gdbtypes.h"
31
#include "inferior.h"
32
#include "symtab.h"
33
#include "objfiles.h"
34
#include "osabi.h"
35
#include "regcache.h"
36
#include "target.h"
37
#include "value.h"
38
 
39
#include "gdb_assert.h"
40
#include "gdb_string.h"
41
 
42
#include "sparc-tdep.h"
43
 
44
struct regset;
45
 
46
/* This file implements the SPARC 32-bit ABI as defined by the section
47
   "Low-Level System Information" of the SPARC Compliance Definition
48
   (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC.  The SCD
49
   lists changes with respect to the original 32-bit psABI as defined
50
   in the "System V ABI, SPARC Processor Supplement".
51
 
52
   Note that if we talk about SunOS, we mean SunOS 4.x, which was
53
   BSD-based, which is sometimes (retroactively?) referred to as
54
   Solaris 1.x.  If we talk about Solaris we mean Solaris 2.x and
55
   above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9
56
   suffering from severe version number inflation).  Solaris 2.x is
57
   also known as SunOS 5.x, since that's what uname(1) says.  Solaris
58
   2.x is SVR4-based.  */
59
 
60
/* Please use the sparc32_-prefix for 32-bit specific code, the
61
   sparc64_-prefix for 64-bit specific code and the sparc_-prefix for
62
   code that can handle both.  The 64-bit specific code lives in
63
   sparc64-tdep.c; don't add any here.  */
64
 
65
/* The SPARC Floating-Point Quad-Precision format is similar to
66
   big-endian IA-64 Quad-recision format.  */
67
#define floatformats_sparc_quad floatformats_ia64_quad
68
 
69
/* The stack pointer is offset from the stack frame by a BIAS of 2047
70
   (0x7ff) for 64-bit code.  BIAS is likely to be defined on SPARC
71
   hosts, so undefine it first.  */
72
#undef BIAS
73
#define BIAS 2047
74
 
75
/* Macros to extract fields from SPARC instructions.  */
76
#define X_OP(i) (((i) >> 30) & 0x3)
77
#define X_RD(i) (((i) >> 25) & 0x1f)
78
#define X_A(i) (((i) >> 29) & 1)
79
#define X_COND(i) (((i) >> 25) & 0xf)
80
#define X_OP2(i) (((i) >> 22) & 0x7)
81
#define X_IMM22(i) ((i) & 0x3fffff)
82
#define X_OP3(i) (((i) >> 19) & 0x3f)
83
#define X_RS1(i) (((i) >> 14) & 0x1f)
84
#define X_RS2(i) ((i) & 0x1f)
85
#define X_I(i) (((i) >> 13) & 1)
86
/* Sign extension macros.  */
87
#define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
88
#define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
89
#define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000)
90
 
91
/* Fetch the instruction at PC.  Instructions are always big-endian
92
   even if the processor operates in little-endian mode.  */
93
 
94
unsigned long
95
sparc_fetch_instruction (CORE_ADDR pc)
96
{
97
  gdb_byte buf[4];
98
  unsigned long insn;
99
  int i;
100
 
101
  /* If we can't read the instruction at PC, return zero.  */
102
  if (read_memory_nobpt (pc, buf, sizeof (buf)))
103
    return 0;
104
 
105
  insn = 0;
106
  for (i = 0; i < sizeof (buf); i++)
107
    insn = (insn << 8) | buf[i];
108
  return insn;
109
}
110
 
111
 
112
/* Return non-zero if the instruction corresponding to PC is an "unimp"
113
   instruction.  */
114
 
115
static int
116
sparc_is_unimp_insn (CORE_ADDR pc)
117
{
118
  const unsigned long insn = sparc_fetch_instruction (pc);
119
 
120
  return ((insn & 0xc1c00000) == 0);
121
}
122
 
123
/* OpenBSD/sparc includes StackGhost, which according to the author's
124
   website http://stackghost.cerias.purdue.edu "... transparently and
125
   automatically protects applications' stack frames; more
126
   specifically, it guards the return pointers.  The protection
127
   mechanisms require no application source or binary modification and
128
   imposes only a negligible performance penalty."
129
 
130
   The same website provides the following description of how
131
   StackGhost works:
132
 
133
   "StackGhost interfaces with the kernel trap handler that would
134
   normally write out registers to the stack and the handler that
135
   would read them back in.  By XORing a cookie into the
136
   return-address saved in the user stack when it is actually written
137
   to the stack, and then XOR it out when the return-address is pulled
138
   from the stack, StackGhost can cause attacker corrupted return
139
   pointers to behave in a manner the attacker cannot predict.
140
   StackGhost can also use several unused bits in the return pointer
141
   to detect a smashed return pointer and abort the process."
142
 
143
   For GDB this means that whenever we're reading %i7 from a stack
144
   frame's window save area, we'll have to XOR the cookie.
145
 
146
   More information on StackGuard can be found on in:
147
 
148
   Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated
149
   Stack Protection."  2001.  Published in USENIX Security Symposium
150
   '01.  */
151
 
152
/* Fetch StackGhost Per-Process XOR cookie.  */
153
 
154
ULONGEST
155
sparc_fetch_wcookie (void)
156
{
157
  struct target_ops *ops = &current_target;
158
  gdb_byte buf[8];
159
  int len;
160
 
161
  len = target_read (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8);
162
  if (len == -1)
163
    return 0;
164
 
165
  /* We should have either an 32-bit or an 64-bit cookie.  */
166
  gdb_assert (len == 4 || len == 8);
167
 
168
  return extract_unsigned_integer (buf, len);
169
}
170
 
171
 
172
/* The functions on this page are intended to be used to classify
173
   function arguments.  */
174
 
175
/* Check whether TYPE is "Integral or Pointer".  */
176
 
177
static int
178
sparc_integral_or_pointer_p (const struct type *type)
179
{
180
  int len = TYPE_LENGTH (type);
181
 
182
  switch (TYPE_CODE (type))
183
    {
184
    case TYPE_CODE_INT:
185
    case TYPE_CODE_BOOL:
186
    case TYPE_CODE_CHAR:
187
    case TYPE_CODE_ENUM:
188
    case TYPE_CODE_RANGE:
189
      /* We have byte, half-word, word and extended-word/doubleword
190
         integral types.  The doubleword is an extension to the
191
         original 32-bit ABI by the SCD 2.4.x.  */
192
      return (len == 1 || len == 2 || len == 4 || len == 8);
193
    case TYPE_CODE_PTR:
194
    case TYPE_CODE_REF:
195
      /* Allow either 32-bit or 64-bit pointers.  */
196
      return (len == 4 || len == 8);
197
    default:
198
      break;
199
    }
200
 
201
  return 0;
202
}
203
 
204
/* Check whether TYPE is "Floating".  */
205
 
206
static int
207
sparc_floating_p (const struct type *type)
208
{
209
  switch (TYPE_CODE (type))
210
    {
211
    case TYPE_CODE_FLT:
212
      {
213
        int len = TYPE_LENGTH (type);
214
        return (len == 4 || len == 8 || len == 16);
215
      }
216
    default:
217
      break;
218
    }
219
 
220
  return 0;
221
}
222
 
223
/* Check whether TYPE is "Structure or Union".  */
224
 
225
static int
226
sparc_structure_or_union_p (const struct type *type)
227
{
228
  switch (TYPE_CODE (type))
229
    {
230
    case TYPE_CODE_STRUCT:
231
    case TYPE_CODE_UNION:
232
      return 1;
233
    default:
234
      break;
235
    }
236
 
237
  return 0;
238
}
239
 
240
/* Register information.  */
241
 
242
static const char *sparc32_register_names[] =
243
{
244
  "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
245
  "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
246
  "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
247
  "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
248
 
249
  "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
250
  "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
251
  "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
252
  "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
253
 
254
  "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr"
255
};
256
 
257
/* Total number of registers.  */
258
#define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names)
259
 
260
/* We provide the aliases %d0..%d30 for the floating registers as
261
   "psuedo" registers.  */
262
 
263
static const char *sparc32_pseudo_register_names[] =
264
{
265
  "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14",
266
  "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30"
267
};
268
 
269
/* Total number of pseudo registers.  */
270
#define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names)
271
 
272
/* Return the name of register REGNUM.  */
273
 
274
static const char *
275
sparc32_register_name (struct gdbarch *gdbarch, int regnum)
276
{
277
  if (regnum >= 0 && regnum < SPARC32_NUM_REGS)
278
    return sparc32_register_names[regnum];
279
 
280
  if (regnum < SPARC32_NUM_REGS + SPARC32_NUM_PSEUDO_REGS)
281
    return sparc32_pseudo_register_names[regnum - SPARC32_NUM_REGS];
282
 
283
  return NULL;
284
}
285
 
286
 
287
/* Type for %psr.  */
288
struct type *sparc_psr_type;
289
 
290
/* Type for %fsr.  */
291
struct type *sparc_fsr_type;
292
 
293
/* Construct types for ISA-specific registers.  */
294
 
295
static void
296
sparc_init_types (void)
297
{
298
  struct type *type;
299
 
300
  type = init_flags_type ("builtin_type_sparc_psr", 4);
301
  append_flags_type_flag (type, 5, "ET");
302
  append_flags_type_flag (type, 6, "PS");
303
  append_flags_type_flag (type, 7, "S");
304
  append_flags_type_flag (type, 12, "EF");
305
  append_flags_type_flag (type, 13, "EC");
306
  sparc_psr_type = type;
307
 
308
  type = init_flags_type ("builtin_type_sparc_fsr", 4);
309
  append_flags_type_flag (type, 0, "NXA");
310
  append_flags_type_flag (type, 1, "DZA");
311
  append_flags_type_flag (type, 2, "UFA");
312
  append_flags_type_flag (type, 3, "OFA");
313
  append_flags_type_flag (type, 4, "NVA");
314
  append_flags_type_flag (type, 5, "NXC");
315
  append_flags_type_flag (type, 6, "DZC");
316
  append_flags_type_flag (type, 7, "UFC");
317
  append_flags_type_flag (type, 8, "OFC");
318
  append_flags_type_flag (type, 9, "NVC");
319
  append_flags_type_flag (type, 22, "NS");
320
  append_flags_type_flag (type, 23, "NXM");
321
  append_flags_type_flag (type, 24, "DZM");
322
  append_flags_type_flag (type, 25, "UFM");
323
  append_flags_type_flag (type, 26, "OFM");
324
  append_flags_type_flag (type, 27, "NVM");
325
  sparc_fsr_type = type;
326
}
327
 
328
/* Return the GDB type object for the "standard" data type of data in
329
   register REGNUM. */
330
 
331
static struct type *
332
sparc32_register_type (struct gdbarch *gdbarch, int regnum)
333
{
334
  if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM)
335
    return builtin_type_float;
336
 
337
  if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM)
338
    return builtin_type_double;
339
 
340
  if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM)
341
    return builtin_type_void_data_ptr;
342
 
343
  if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM)
344
    return builtin_type_void_func_ptr;
345
 
346
  if (regnum == SPARC32_PSR_REGNUM)
347
    return sparc_psr_type;
348
 
349
  if (regnum == SPARC32_FSR_REGNUM)
350
    return sparc_fsr_type;
351
 
352
  return builtin_type_int32;
353
}
354
 
355
static void
356
sparc32_pseudo_register_read (struct gdbarch *gdbarch,
357
                              struct regcache *regcache,
358
                              int regnum, gdb_byte *buf)
359
{
360
  gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM);
361
 
362
  regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM);
363
  regcache_raw_read (regcache, regnum, buf);
364
  regcache_raw_read (regcache, regnum + 1, buf + 4);
365
}
366
 
367
static void
368
sparc32_pseudo_register_write (struct gdbarch *gdbarch,
369
                               struct regcache *regcache,
370
                               int regnum, const gdb_byte *buf)
371
{
372
  gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM);
373
 
374
  regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM);
375
  regcache_raw_write (regcache, regnum, buf);
376
  regcache_raw_write (regcache, regnum + 1, buf + 4);
377
}
378
 
379
 
380
static CORE_ADDR
381
sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
382
                         CORE_ADDR funcaddr,
383
                         struct value **args, int nargs,
384
                         struct type *value_type,
385
                         CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
386
                         struct regcache *regcache)
387
{
388
  *bp_addr = sp - 4;
389
  *real_pc = funcaddr;
390
 
391
  if (using_struct_return (value_type))
392
    {
393
      gdb_byte buf[4];
394
 
395
      /* This is an UNIMP instruction.  */
396
      store_unsigned_integer (buf, 4, TYPE_LENGTH (value_type) & 0x1fff);
397
      write_memory (sp - 8, buf, 4);
398
      return sp - 8;
399
    }
400
 
401
  return sp - 4;
402
}
403
 
404
static CORE_ADDR
405
sparc32_store_arguments (struct regcache *regcache, int nargs,
406
                         struct value **args, CORE_ADDR sp,
407
                         int struct_return, CORE_ADDR struct_addr)
408
{
409
  /* Number of words in the "parameter array".  */
410
  int num_elements = 0;
411
  int element = 0;
412
  int i;
413
 
414
  for (i = 0; i < nargs; i++)
415
    {
416
      struct type *type = value_type (args[i]);
417
      int len = TYPE_LENGTH (type);
418
 
419
      if (sparc_structure_or_union_p (type)
420
          || (sparc_floating_p (type) && len == 16))
421
        {
422
          /* Structure, Union and Quad-Precision Arguments.  */
423
          sp -= len;
424
 
425
          /* Use doubleword alignment for these values.  That's always
426
             correct, and wasting a few bytes shouldn't be a problem.  */
427
          sp &= ~0x7;
428
 
429
          write_memory (sp, value_contents (args[i]), len);
430
          args[i] = value_from_pointer (lookup_pointer_type (type), sp);
431
          num_elements++;
432
        }
433
      else if (sparc_floating_p (type))
434
        {
435
          /* Floating arguments.  */
436
          gdb_assert (len == 4 || len == 8);
437
          num_elements += (len / 4);
438
        }
439
      else
440
        {
441
          /* Integral and pointer arguments.  */
442
          gdb_assert (sparc_integral_or_pointer_p (type));
443
 
444
          if (len < 4)
445
            args[i] = value_cast (builtin_type_int32, args[i]);
446
          num_elements += ((len + 3) / 4);
447
        }
448
    }
449
 
450
  /* Always allocate at least six words.  */
451
  sp -= max (6, num_elements) * 4;
452
 
453
  /* The psABI says that "Software convention requires space for the
454
     struct/union return value pointer, even if the word is unused."  */
455
  sp -= 4;
456
 
457
  /* The psABI says that "Although software convention and the
458
     operating system require every stack frame to be doubleword
459
     aligned."  */
460
  sp &= ~0x7;
461
 
462
  for (i = 0; i < nargs; i++)
463
    {
464
      const bfd_byte *valbuf = value_contents (args[i]);
465
      struct type *type = value_type (args[i]);
466
      int len = TYPE_LENGTH (type);
467
 
468
      gdb_assert (len == 4 || len == 8);
469
 
470
      if (element < 6)
471
        {
472
          int regnum = SPARC_O0_REGNUM + element;
473
 
474
          regcache_cooked_write (regcache, regnum, valbuf);
475
          if (len > 4 && element < 5)
476
            regcache_cooked_write (regcache, regnum + 1, valbuf + 4);
477
        }
478
 
479
      /* Always store the argument in memory.  */
480
      write_memory (sp + 4 + element * 4, valbuf, len);
481
      element += len / 4;
482
    }
483
 
484
  gdb_assert (element == num_elements);
485
 
486
  if (struct_return)
487
    {
488
      gdb_byte buf[4];
489
 
490
      store_unsigned_integer (buf, 4, struct_addr);
491
      write_memory (sp, buf, 4);
492
    }
493
 
494
  return sp;
495
}
496
 
497
static CORE_ADDR
498
sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
499
                         struct regcache *regcache, CORE_ADDR bp_addr,
500
                         int nargs, struct value **args, CORE_ADDR sp,
501
                         int struct_return, CORE_ADDR struct_addr)
502
{
503
  CORE_ADDR call_pc = (struct_return ? (bp_addr - 12) : (bp_addr - 8));
504
 
505
  /* Set return address.  */
506
  regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc);
507
 
508
  /* Set up function arguments.  */
509
  sp = sparc32_store_arguments (regcache, nargs, args, sp,
510
                                struct_return, struct_addr);
511
 
512
  /* Allocate the 16-word window save area.  */
513
  sp -= 16 * 4;
514
 
515
  /* Stack should be doubleword aligned at this point.  */
516
  gdb_assert (sp % 8 == 0);
517
 
518
  /* Finally, update the stack pointer.  */
519
  regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp);
520
 
521
  return sp;
522
}
523
 
524
 
525
/* Use the program counter to determine the contents and size of a
526
   breakpoint instruction.  Return a pointer to a string of bytes that
527
   encode a breakpoint instruction, store the length of the string in
528
   *LEN and optionally adjust *PC to point to the correct memory
529
   location for inserting the breakpoint.  */
530
 
531
static const gdb_byte *
532
sparc_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len)
533
{
534
  static const gdb_byte break_insn[] = { 0x91, 0xd0, 0x20, 0x01 };
535
 
536
  *len = sizeof (break_insn);
537
  return break_insn;
538
}
539
 
540
 
541
/* Allocate and initialize a frame cache.  */
542
 
543
static struct sparc_frame_cache *
544
sparc_alloc_frame_cache (void)
545
{
546
  struct sparc_frame_cache *cache;
547
  int i;
548
 
549
  cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache);
550
 
551
  /* Base address.  */
552
  cache->base = 0;
553
  cache->pc = 0;
554
 
555
  /* Frameless until proven otherwise.  */
556
  cache->frameless_p = 1;
557
 
558
  cache->struct_return_p = 0;
559
 
560
  return cache;
561
}
562
 
563
/* GCC generates several well-known sequences of instructions at the begining
564
   of each function prologue when compiling with -fstack-check.  If one of
565
   such sequences starts at START_PC, then return the address of the
566
   instruction immediately past this sequence.  Otherwise, return START_PC.  */
567
 
568
static CORE_ADDR
569
sparc_skip_stack_check (const CORE_ADDR start_pc)
570
{
571
  CORE_ADDR pc = start_pc;
572
  unsigned long insn;
573
  int offset_stack_checking_sequence = 0;
574
 
575
  /* With GCC, all stack checking sequences begin with the same two
576
     instructions.  */
577
 
578
  /* sethi <some immediate>,%g1 */
579
  insn = sparc_fetch_instruction (pc);
580
  pc = pc + 4;
581
  if (!(X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 1))
582
    return start_pc;
583
 
584
  /* sub %sp, %g1, %g1 */
585
  insn = sparc_fetch_instruction (pc);
586
  pc = pc + 4;
587
  if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn)
588
        && X_RD (insn) == 1 && X_RS1 (insn) == 14 && X_RS2 (insn) == 1))
589
    return start_pc;
590
 
591
  insn = sparc_fetch_instruction (pc);
592
  pc = pc + 4;
593
 
594
  /* First possible sequence:
595
         [first two instructions above]
596
         clr [%g1 - some immediate]  */
597
 
598
  /* clr [%g1 - some immediate]  */
599
  if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn)
600
      && X_RS1 (insn) == 1 && X_RD (insn) == 0)
601
    {
602
      /* Valid stack-check sequence, return the new PC.  */
603
      return pc;
604
    }
605
 
606
  /* Second possible sequence: A small number of probes.
607
         [first two instructions above]
608
         clr [%g1]
609
         add   %g1, -<some immediate>, %g1
610
         clr [%g1]
611
         [repeat the two instructions above any (small) number of times]
612
         clr [%g1 - some immediate]  */
613
 
614
  /* clr [%g1] */
615
  else if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn)
616
      && X_RS1 (insn) == 1 && X_RD (insn) == 0)
617
    {
618
      while (1)
619
        {
620
          /* add %g1, -<some immediate>, %g1 */
621
          insn = sparc_fetch_instruction (pc);
622
          pc = pc + 4;
623
          if (!(X_OP (insn) == 2  && X_OP3(insn) == 0 && X_I(insn)
624
                && X_RS1 (insn) == 1 && X_RD (insn) == 1))
625
            break;
626
 
627
          /* clr [%g1] */
628
          insn = sparc_fetch_instruction (pc);
629
          pc = pc + 4;
630
          if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn)
631
                && X_RD (insn) == 0 && X_RS1 (insn) == 1))
632
            return start_pc;
633
        }
634
 
635
      /* clr [%g1 - some immediate] */
636
      if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn)
637
            && X_RS1 (insn) == 1 && X_RD (insn) == 0))
638
        return start_pc;
639
 
640
      /* We found a valid stack-check sequence, return the new PC.  */
641
      return pc;
642
    }
643
 
644
  /* Third sequence: A probing loop.
645
         [first two instructions above]
646
         sethi  <some immediate>, %g4
647
         sub  %g1, %g4, %g4
648
         cmp  %g1, %g4
649
         be  <disp>
650
         add  %g1, -<some immediate>, %g1
651
         ba  <disp>
652
         clr  [%g1]
653
         clr [%g4 - some immediate]  */
654
 
655
  /* sethi  <some immediate>, %g4 */
656
  else if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4)
657
    {
658
      /* sub  %g1, %g4, %g4 */
659
      insn = sparc_fetch_instruction (pc);
660
      pc = pc + 4;
661
      if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn)
662
            && X_RD (insn) == 4 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4))
663
        return start_pc;
664
 
665
      /* cmp  %g1, %g4 */
666
      insn = sparc_fetch_instruction (pc);
667
      pc = pc + 4;
668
      if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x14 && !X_I(insn)
669
            && X_RD (insn) == 0 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4))
670
        return start_pc;
671
 
672
      /* be  <disp> */
673
      insn = sparc_fetch_instruction (pc);
674
      pc = pc + 4;
675
      if (!(X_OP (insn) == 0 && X_COND (insn) == 0x1))
676
        return start_pc;
677
 
678
      /* add  %g1, -<some immediate>, %g1 */
679
      insn = sparc_fetch_instruction (pc);
680
      pc = pc + 4;
681
      if (!(X_OP (insn) == 2  && X_OP3(insn) == 0 && X_I(insn)
682
            && X_RS1 (insn) == 1 && X_RD (insn) == 1))
683
        return start_pc;
684
 
685
      /* ba  <disp> */
686
      insn = sparc_fetch_instruction (pc);
687
      pc = pc + 4;
688
      if (!(X_OP (insn) == 0 && X_COND (insn) == 0x8))
689
        return start_pc;
690
 
691
      /* clr  [%g1] */
692
      insn = sparc_fetch_instruction (pc);
693
      pc = pc + 4;
694
      if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn)
695
            && X_RD (insn) == 0 && X_RS1 (insn) == 1))
696
        return start_pc;
697
 
698
      /* clr [%g4 - some immediate]  */
699
      insn = sparc_fetch_instruction (pc);
700
      pc = pc + 4;
701
      if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn)
702
            && X_RS1 (insn) == 4 && X_RD (insn) == 0))
703
        return start_pc;
704
 
705
      /* We found a valid stack-check sequence, return the new PC.  */
706
      return pc;
707
    }
708
 
709
  /* No stack check code in our prologue, return the start_pc.  */
710
  return start_pc;
711
}
712
 
713
CORE_ADDR
714
sparc_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
715
                        CORE_ADDR current_pc, struct sparc_frame_cache *cache)
716
{
717
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
718
  unsigned long insn;
719
  int offset = 0;
720
  int dest = -1;
721
 
722
  pc = sparc_skip_stack_check (pc);
723
 
724
  if (current_pc <= pc)
725
    return current_pc;
726
 
727
  /* We have to handle to "Procedure Linkage Table" (PLT) special.  On
728
     SPARC the linker usually defines a symbol (typically
729
     _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section.
730
     This symbol makes us end up here with PC pointing at the start of
731
     the PLT and CURRENT_PC probably pointing at a PLT entry.  If we
732
     would do our normal prologue analysis, we would probably conclude
733
     that we've got a frame when in reality we don't, since the
734
     dynamic linker patches up the first PLT with some code that
735
     starts with a SAVE instruction.  Patch up PC such that it points
736
     at the start of our PLT entry.  */
737
  if (tdep->plt_entry_size > 0 && in_plt_section (current_pc, NULL))
738
    pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size);
739
 
740
  insn = sparc_fetch_instruction (pc);
741
 
742
  /* Recognize a SETHI insn and record its destination.  */
743
  if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04)
744
    {
745
      dest = X_RD (insn);
746
      offset += 4;
747
 
748
      insn = sparc_fetch_instruction (pc + 4);
749
    }
750
 
751
  /* Allow for an arithmetic operation on DEST or %g1.  */
752
  if (X_OP (insn) == 2 && X_I (insn)
753
      && (X_RD (insn) == 1 || X_RD (insn) == dest))
754
    {
755
      offset += 4;
756
 
757
      insn = sparc_fetch_instruction (pc + 8);
758
    }
759
 
760
  /* Check for the SAVE instruction that sets up the frame.  */
761
  if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c)
762
    {
763
      cache->frameless_p = 0;
764
      return pc + offset + 4;
765
    }
766
 
767
  return pc;
768
}
769
 
770
static CORE_ADDR
771
sparc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
772
{
773
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
774
  return frame_unwind_register_unsigned (next_frame, tdep->pc_regnum);
775
}
776
 
777
/* Return PC of first real instruction of the function starting at
778
   START_PC.  */
779
 
780
static CORE_ADDR
781
sparc32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
782
{
783
  struct symtab_and_line sal;
784
  CORE_ADDR func_start, func_end;
785
  struct sparc_frame_cache cache;
786
 
787
  /* This is the preferred method, find the end of the prologue by
788
     using the debugging information.  */
789
  if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end))
790
    {
791
      sal = find_pc_line (func_start, 0);
792
 
793
      if (sal.end < func_end
794
          && start_pc <= sal.end)
795
        return sal.end;
796
    }
797
 
798
  start_pc = sparc_analyze_prologue (gdbarch, start_pc, 0xffffffffUL, &cache);
799
 
800
  /* The psABI says that "Although the first 6 words of arguments
801
     reside in registers, the standard stack frame reserves space for
802
     them.".  It also suggests that a function may use that space to
803
     "write incoming arguments 0 to 5" into that space, and that's
804
     indeed what GCC seems to be doing.  In that case GCC will
805
     generate debug information that points to the stack slots instead
806
     of the registers, so we should consider the instructions that
807
     write out these incoming arguments onto the stack.  Of course we
808
     only need to do this if we have a stack frame.  */
809
 
810
  while (!cache.frameless_p)
811
    {
812
      unsigned long insn = sparc_fetch_instruction (start_pc);
813
 
814
      /* Recognize instructions that store incoming arguments in
815
         %i0...%i5 into the corresponding stack slot.  */
816
      if (X_OP (insn) == 3 && (X_OP3 (insn) & 0x3c) == 0x04 && X_I (insn)
817
          && (X_RD (insn) >= 24 && X_RD (insn) <= 29) && X_RS1 (insn) == 30
818
          && X_SIMM13 (insn) == 68 + (X_RD (insn) - 24) * 4)
819
        {
820
          start_pc += 4;
821
          continue;
822
        }
823
 
824
      break;
825
    }
826
 
827
  return start_pc;
828
}
829
 
830
/* Normal frames.  */
831
 
832
struct sparc_frame_cache *
833
sparc_frame_cache (struct frame_info *next_frame, void **this_cache)
834
{
835
  struct sparc_frame_cache *cache;
836
 
837
  if (*this_cache)
838
    return *this_cache;
839
 
840
  cache = sparc_alloc_frame_cache ();
841
  *this_cache = cache;
842
 
843
  cache->pc = frame_func_unwind (next_frame, NORMAL_FRAME);
844
  if (cache->pc != 0)
845
    sparc_analyze_prologue (get_frame_arch (next_frame), cache->pc,
846
                            frame_pc_unwind (next_frame), cache);
847
 
848
  if (cache->frameless_p)
849
    {
850
      /* This function is frameless, so %fp (%i6) holds the frame
851
         pointer for our calling frame.  Use %sp (%o6) as this frame's
852
         base address.  */
853
      cache->base =
854
        frame_unwind_register_unsigned (next_frame, SPARC_SP_REGNUM);
855
    }
856
  else
857
    {
858
      /* For normal frames, %fp (%i6) holds the frame pointer, the
859
         base address for the current stack frame.  */
860
      cache->base =
861
        frame_unwind_register_unsigned (next_frame, SPARC_FP_REGNUM);
862
    }
863
 
864
  if (cache->base & 1)
865
    cache->base += BIAS;
866
 
867
  return cache;
868
}
869
 
870
static int
871
sparc32_struct_return_from_sym (struct symbol *sym)
872
{
873
  struct type *type = check_typedef (SYMBOL_TYPE (sym));
874
  enum type_code code = TYPE_CODE (type);
875
 
876
  if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD)
877
    {
878
      type = check_typedef (TYPE_TARGET_TYPE (type));
879
      if (sparc_structure_or_union_p (type)
880
          || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16))
881
        return 1;
882
    }
883
 
884
  return 0;
885
}
886
 
887
struct sparc_frame_cache *
888
sparc32_frame_cache (struct frame_info *next_frame, void **this_cache)
889
{
890
  struct sparc_frame_cache *cache;
891
  struct symbol *sym;
892
 
893
  if (*this_cache)
894
    return *this_cache;
895
 
896
  cache = sparc_frame_cache (next_frame, this_cache);
897
 
898
  sym = find_pc_function (cache->pc);
899
  if (sym)
900
    {
901
      cache->struct_return_p = sparc32_struct_return_from_sym (sym);
902
    }
903
  else
904
    {
905
      /* There is no debugging information for this function to
906
         help us determine whether this function returns a struct
907
         or not.  So we rely on another heuristic which is to check
908
         the instruction at the return address and see if this is
909
         an "unimp" instruction.  If it is, then it is a struct-return
910
         function.  */
911
      CORE_ADDR pc;
912
      int regnum = cache->frameless_p ? SPARC_O7_REGNUM : SPARC_I7_REGNUM;
913
 
914
      pc = frame_unwind_register_unsigned (next_frame, regnum) + 8;
915
      if (sparc_is_unimp_insn (pc))
916
        cache->struct_return_p = 1;
917
    }
918
 
919
  return cache;
920
}
921
 
922
static void
923
sparc32_frame_this_id (struct frame_info *next_frame, void **this_cache,
924
                       struct frame_id *this_id)
925
{
926
  struct sparc_frame_cache *cache =
927
    sparc32_frame_cache (next_frame, this_cache);
928
 
929
  /* This marks the outermost frame.  */
930
  if (cache->base == 0)
931
    return;
932
 
933
  (*this_id) = frame_id_build (cache->base, cache->pc);
934
}
935
 
936
static void
937
sparc32_frame_prev_register (struct frame_info *next_frame, void **this_cache,
938
                             int regnum, int *optimizedp,
939
                             enum lval_type *lvalp, CORE_ADDR *addrp,
940
                             int *realnump, gdb_byte *valuep)
941
{
942
  struct sparc_frame_cache *cache =
943
    sparc32_frame_cache (next_frame, this_cache);
944
 
945
  if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM)
946
    {
947
      *optimizedp = 0;
948
      *lvalp = not_lval;
949
      *addrp = 0;
950
      *realnump = -1;
951
      if (valuep)
952
        {
953
          CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0;
954
 
955
          /* If this functions has a Structure, Union or
956
             Quad-Precision return value, we have to skip the UNIMP
957
             instruction that encodes the size of the structure.  */
958
          if (cache->struct_return_p)
959
            pc += 4;
960
 
961
          regnum = cache->frameless_p ? SPARC_O7_REGNUM : SPARC_I7_REGNUM;
962
          pc += frame_unwind_register_unsigned (next_frame, regnum) + 8;
963
          store_unsigned_integer (valuep, 4, pc);
964
        }
965
      return;
966
    }
967
 
968
  /* Handle StackGhost.  */
969
  {
970
    ULONGEST wcookie = sparc_fetch_wcookie ();
971
 
972
    if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM)
973
      {
974
        *optimizedp = 0;
975
        *lvalp = not_lval;
976
        *addrp = 0;
977
        *realnump = -1;
978
        if (valuep)
979
          {
980
            CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4;
981
            ULONGEST i7;
982
 
983
            /* Read the value in from memory.  */
984
            i7 = get_frame_memory_unsigned (next_frame, addr, 4);
985
            store_unsigned_integer (valuep, 4, i7 ^ wcookie);
986
          }
987
        return;
988
      }
989
  }
990
 
991
  /* The previous frame's `local' and `in' registers have been saved
992
     in the register save area.  */
993
  if (!cache->frameless_p
994
      && regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM)
995
    {
996
      *optimizedp = 0;
997
      *lvalp = lval_memory;
998
      *addrp = cache->base + (regnum - SPARC_L0_REGNUM) * 4;
999
      *realnump = -1;
1000
      if (valuep)
1001
        {
1002
          struct gdbarch *gdbarch = get_frame_arch (next_frame);
1003
 
1004
          /* Read the value in from memory.  */
1005
          read_memory (*addrp, valuep, register_size (gdbarch, regnum));
1006
        }
1007
      return;
1008
    }
1009
 
1010
  /* The previous frame's `out' registers are accessable as the
1011
     current frame's `in' registers.  */
1012
  if (!cache->frameless_p
1013
      && regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM)
1014
    regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM);
1015
 
1016
  *optimizedp = 0;
1017
  *lvalp = lval_register;
1018
  *addrp = 0;
1019
  *realnump = regnum;
1020
  if (valuep)
1021
    frame_unwind_register (next_frame, (*realnump), valuep);
1022
}
1023
 
1024
static const struct frame_unwind sparc32_frame_unwind =
1025
{
1026
  NORMAL_FRAME,
1027
  sparc32_frame_this_id,
1028
  sparc32_frame_prev_register
1029
};
1030
 
1031
static const struct frame_unwind *
1032
sparc32_frame_sniffer (struct frame_info *next_frame)
1033
{
1034
  return &sparc32_frame_unwind;
1035
}
1036
 
1037
 
1038
static CORE_ADDR
1039
sparc32_frame_base_address (struct frame_info *next_frame, void **this_cache)
1040
{
1041
  struct sparc_frame_cache *cache =
1042
    sparc32_frame_cache (next_frame, this_cache);
1043
 
1044
  return cache->base;
1045
}
1046
 
1047
static const struct frame_base sparc32_frame_base =
1048
{
1049
  &sparc32_frame_unwind,
1050
  sparc32_frame_base_address,
1051
  sparc32_frame_base_address,
1052
  sparc32_frame_base_address
1053
};
1054
 
1055
static struct frame_id
1056
sparc_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1057
{
1058
  CORE_ADDR sp;
1059
 
1060
  sp = frame_unwind_register_unsigned (next_frame, SPARC_SP_REGNUM);
1061
  if (sp & 1)
1062
    sp += BIAS;
1063
  return frame_id_build (sp, frame_pc_unwind (next_frame));
1064
}
1065
 
1066
 
1067
/* Extract from an array REGBUF containing the (raw) register state, a
1068
   function return value of TYPE, and copy that into VALBUF.  */
1069
 
1070
static void
1071
sparc32_extract_return_value (struct type *type, struct regcache *regcache,
1072
                              gdb_byte *valbuf)
1073
{
1074
  int len = TYPE_LENGTH (type);
1075
  gdb_byte buf[8];
1076
 
1077
  gdb_assert (!sparc_structure_or_union_p (type));
1078
  gdb_assert (!(sparc_floating_p (type) && len == 16));
1079
 
1080
  if (sparc_floating_p (type))
1081
    {
1082
      /* Floating return values.  */
1083
      regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf);
1084
      if (len > 4)
1085
        regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4);
1086
      memcpy (valbuf, buf, len);
1087
    }
1088
  else
1089
    {
1090
      /* Integral and pointer return values.  */
1091
      gdb_assert (sparc_integral_or_pointer_p (type));
1092
 
1093
      regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf);
1094
      if (len > 4)
1095
        {
1096
          regcache_cooked_read (regcache, SPARC_O1_REGNUM, buf + 4);
1097
          gdb_assert (len == 8);
1098
          memcpy (valbuf, buf, 8);
1099
        }
1100
      else
1101
        {
1102
          /* Just stripping off any unused bytes should preserve the
1103
             signed-ness just fine.  */
1104
          memcpy (valbuf, buf + 4 - len, len);
1105
        }
1106
    }
1107
}
1108
 
1109
/* Write into the appropriate registers a function return value stored
1110
   in VALBUF of type TYPE.  */
1111
 
1112
static void
1113
sparc32_store_return_value (struct type *type, struct regcache *regcache,
1114
                            const gdb_byte *valbuf)
1115
{
1116
  int len = TYPE_LENGTH (type);
1117
  gdb_byte buf[8];
1118
 
1119
  gdb_assert (!sparc_structure_or_union_p (type));
1120
  gdb_assert (!(sparc_floating_p (type) && len == 16));
1121
 
1122
  if (sparc_floating_p (type))
1123
    {
1124
      /* Floating return values.  */
1125
      memcpy (buf, valbuf, len);
1126
      regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf);
1127
      if (len > 4)
1128
        regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4);
1129
    }
1130
  else
1131
    {
1132
      /* Integral and pointer return values.  */
1133
      gdb_assert (sparc_integral_or_pointer_p (type));
1134
 
1135
      if (len > 4)
1136
        {
1137
          gdb_assert (len == 8);
1138
          memcpy (buf, valbuf, 8);
1139
          regcache_cooked_write (regcache, SPARC_O1_REGNUM, buf + 4);
1140
        }
1141
      else
1142
        {
1143
          /* ??? Do we need to do any sign-extension here?  */
1144
          memcpy (buf + 4 - len, valbuf, len);
1145
        }
1146
      regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf);
1147
    }
1148
}
1149
 
1150
static enum return_value_convention
1151
sparc32_return_value (struct gdbarch *gdbarch, struct type *type,
1152
                      struct regcache *regcache, gdb_byte *readbuf,
1153
                      const gdb_byte *writebuf)
1154
{
1155
  /* The psABI says that "...every stack frame reserves the word at
1156
     %fp+64.  If a function returns a structure, union, or
1157
     quad-precision value, this word should hold the address of the
1158
     object into which the return value should be copied."  This
1159
     guarantees that we can always find the return value, not just
1160
     before the function returns.  */
1161
 
1162
  if (sparc_structure_or_union_p (type)
1163
      || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16))
1164
    {
1165
      if (readbuf)
1166
        {
1167
          ULONGEST sp;
1168
          CORE_ADDR addr;
1169
 
1170
          regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp);
1171
          addr = read_memory_unsigned_integer (sp + 64, 4);
1172
          read_memory (addr, readbuf, TYPE_LENGTH (type));
1173
        }
1174
 
1175
      return RETURN_VALUE_ABI_PRESERVES_ADDRESS;
1176
    }
1177
 
1178
  if (readbuf)
1179
    sparc32_extract_return_value (type, regcache, readbuf);
1180
  if (writebuf)
1181
    sparc32_store_return_value (type, regcache, writebuf);
1182
 
1183
  return RETURN_VALUE_REGISTER_CONVENTION;
1184
}
1185
 
1186
static int
1187
sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type)
1188
{
1189
  return (sparc_structure_or_union_p (type)
1190
          || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16));
1191
}
1192
 
1193
static int
1194
sparc32_dwarf2_struct_return_p (struct frame_info *next_frame)
1195
{
1196
  CORE_ADDR pc = frame_unwind_address_in_block (next_frame, NORMAL_FRAME);
1197
  struct symbol *sym = find_pc_function (pc);
1198
 
1199
  if (sym)
1200
    return sparc32_struct_return_from_sym (sym);
1201
  return 0;
1202
}
1203
 
1204
static void
1205
sparc32_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1206
                               struct dwarf2_frame_state_reg *reg,
1207
                               struct frame_info *next_frame)
1208
{
1209
  int off;
1210
 
1211
  switch (regnum)
1212
    {
1213
    case SPARC_G0_REGNUM:
1214
      /* Since %g0 is always zero, there is no point in saving it, and
1215
         people will be inclined omit it from the CFI.  Make sure we
1216
         don't warn about that.  */
1217
      reg->how = DWARF2_FRAME_REG_SAME_VALUE;
1218
      break;
1219
    case SPARC_SP_REGNUM:
1220
      reg->how = DWARF2_FRAME_REG_CFA;
1221
      break;
1222
    case SPARC32_PC_REGNUM:
1223
    case SPARC32_NPC_REGNUM:
1224
      reg->how = DWARF2_FRAME_REG_RA_OFFSET;
1225
      off = 8;
1226
      if (sparc32_dwarf2_struct_return_p (next_frame))
1227
        off += 4;
1228
      if (regnum == SPARC32_NPC_REGNUM)
1229
        off += 4;
1230
      reg->loc.offset = off;
1231
      break;
1232
    }
1233
}
1234
 
1235
 
1236
/* The SPARC Architecture doesn't have hardware single-step support,
1237
   and most operating systems don't implement it either, so we provide
1238
   software single-step mechanism.  */
1239
 
1240
static CORE_ADDR
1241
sparc_analyze_control_transfer (struct frame_info *frame,
1242
                                CORE_ADDR pc, CORE_ADDR *npc)
1243
{
1244
  unsigned long insn = sparc_fetch_instruction (pc);
1245
  int conditional_p = X_COND (insn) & 0x7;
1246
  int branch_p = 0;
1247
  long offset = 0;                       /* Must be signed for sign-extend.  */
1248
 
1249
  if (X_OP (insn) == 0 && X_OP2 (insn) == 3 && (insn & 0x1000000) == 0)
1250
    {
1251
      /* Branch on Integer Register with Prediction (BPr).  */
1252
      branch_p = 1;
1253
      conditional_p = 1;
1254
    }
1255
  else if (X_OP (insn) == 0 && X_OP2 (insn) == 6)
1256
    {
1257
      /* Branch on Floating-Point Condition Codes (FBfcc).  */
1258
      branch_p = 1;
1259
      offset = 4 * X_DISP22 (insn);
1260
    }
1261
  else if (X_OP (insn) == 0 && X_OP2 (insn) == 5)
1262
    {
1263
      /* Branch on Floating-Point Condition Codes with Prediction
1264
         (FBPfcc).  */
1265
      branch_p = 1;
1266
      offset = 4 * X_DISP19 (insn);
1267
    }
1268
  else if (X_OP (insn) == 0 && X_OP2 (insn) == 2)
1269
    {
1270
      /* Branch on Integer Condition Codes (Bicc).  */
1271
      branch_p = 1;
1272
      offset = 4 * X_DISP22 (insn);
1273
    }
1274
  else if (X_OP (insn) == 0 && X_OP2 (insn) == 1)
1275
    {
1276
      /* Branch on Integer Condition Codes with Prediction (BPcc).  */
1277
      branch_p = 1;
1278
      offset = 4 * X_DISP19 (insn);
1279
    }
1280
  else if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3a)
1281
    {
1282
      /* Trap instruction (TRAP).  */
1283
      return gdbarch_tdep (get_frame_arch (frame))->step_trap (frame, insn);
1284
    }
1285
 
1286
  /* FIXME: Handle DONE and RETRY instructions.  */
1287
 
1288
  if (branch_p)
1289
    {
1290
      if (conditional_p)
1291
        {
1292
          /* For conditional branches, return nPC + 4 iff the annul
1293
             bit is 1.  */
1294
          return (X_A (insn) ? *npc + 4 : 0);
1295
        }
1296
      else
1297
        {
1298
          /* For unconditional branches, return the target if its
1299
             specified condition is "always" and return nPC + 4 if the
1300
             condition is "never".  If the annul bit is 1, set *NPC to
1301
             zero.  */
1302
          if (X_COND (insn) == 0x0)
1303
            pc = *npc, offset = 4;
1304
          if (X_A (insn))
1305
            *npc = 0;
1306
 
1307
          gdb_assert (offset != 0);
1308
          return pc + offset;
1309
        }
1310
    }
1311
 
1312
  return 0;
1313
}
1314
 
1315
static CORE_ADDR
1316
sparc_step_trap (struct frame_info *frame, unsigned long insn)
1317
{
1318
  return 0;
1319
}
1320
 
1321
int
1322
sparc_software_single_step (struct frame_info *frame)
1323
{
1324
  struct gdbarch *arch = get_frame_arch (frame);
1325
  struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
1326
  CORE_ADDR npc, nnpc;
1327
 
1328
  CORE_ADDR pc, orig_npc;
1329
 
1330
  pc = get_frame_register_unsigned (frame, tdep->pc_regnum);
1331
  orig_npc = npc = get_frame_register_unsigned (frame, tdep->npc_regnum);
1332
 
1333
  /* Analyze the instruction at PC.  */
1334
  nnpc = sparc_analyze_control_transfer (frame, pc, &npc);
1335
  if (npc != 0)
1336
    insert_single_step_breakpoint (npc);
1337
 
1338
  if (nnpc != 0)
1339
    insert_single_step_breakpoint (nnpc);
1340
 
1341
  /* Assert that we have set at least one breakpoint, and that
1342
     they're not set at the same spot - unless we're going
1343
     from here straight to NULL, i.e. a call or jump to 0.  */
1344
  gdb_assert (npc != 0 || nnpc != 0 || orig_npc == 0);
1345
  gdb_assert (nnpc != npc || orig_npc == 0);
1346
 
1347
  return 1;
1348
}
1349
 
1350
static void
1351
sparc_write_pc (struct regcache *regcache, CORE_ADDR pc)
1352
{
1353
  struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
1354
 
1355
  regcache_cooked_write_unsigned (regcache, tdep->pc_regnum, pc);
1356
  regcache_cooked_write_unsigned (regcache, tdep->npc_regnum, pc + 4);
1357
}
1358
 
1359
 
1360
/* Return the appropriate register set for the core section identified
1361
   by SECT_NAME and SECT_SIZE.  */
1362
 
1363
const struct regset *
1364
sparc_regset_from_core_section (struct gdbarch *gdbarch,
1365
                                const char *sect_name, size_t sect_size)
1366
{
1367
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1368
 
1369
  if (strcmp (sect_name, ".reg") == 0 && sect_size >= tdep->sizeof_gregset)
1370
    return tdep->gregset;
1371
 
1372
  if (strcmp (sect_name, ".reg2") == 0 && sect_size >= tdep->sizeof_fpregset)
1373
    return tdep->fpregset;
1374
 
1375
  return NULL;
1376
}
1377
 
1378
 
1379
static struct gdbarch *
1380
sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1381
{
1382
  struct gdbarch_tdep *tdep;
1383
  struct gdbarch *gdbarch;
1384
 
1385
  /* If there is already a candidate, use it.  */
1386
  arches = gdbarch_list_lookup_by_info (arches, &info);
1387
  if (arches != NULL)
1388
    return arches->gdbarch;
1389
 
1390
  /* Allocate space for the new architecture.  */
1391
  tdep = XMALLOC (struct gdbarch_tdep);
1392
  gdbarch = gdbarch_alloc (&info, tdep);
1393
 
1394
  tdep->pc_regnum = SPARC32_PC_REGNUM;
1395
  tdep->npc_regnum = SPARC32_NPC_REGNUM;
1396
  tdep->gregset = NULL;
1397
  tdep->sizeof_gregset = 0;
1398
  tdep->fpregset = NULL;
1399
  tdep->sizeof_fpregset = 0;
1400
  tdep->plt_entry_size = 0;
1401
  tdep->step_trap = sparc_step_trap;
1402
 
1403
  set_gdbarch_long_double_bit (gdbarch, 128);
1404
  set_gdbarch_long_double_format (gdbarch, floatformats_sparc_quad);
1405
 
1406
  set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS);
1407
  set_gdbarch_register_name (gdbarch, sparc32_register_name);
1408
  set_gdbarch_register_type (gdbarch, sparc32_register_type);
1409
  set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS);
1410
  set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read);
1411
  set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write);
1412
 
1413
  /* Register numbers of various important registers.  */
1414
  set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */
1415
  set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */
1416
  set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */
1417
 
1418
  /* Call dummy code.  */
1419
  set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
1420
  set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code);
1421
  set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call);
1422
 
1423
  set_gdbarch_return_value (gdbarch, sparc32_return_value);
1424
  set_gdbarch_stabs_argument_has_addr
1425
    (gdbarch, sparc32_stabs_argument_has_addr);
1426
 
1427
  set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue);
1428
 
1429
  /* Stack grows downward.  */
1430
  set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1431
 
1432
  set_gdbarch_breakpoint_from_pc (gdbarch, sparc_breakpoint_from_pc);
1433
 
1434
  set_gdbarch_frame_args_skip (gdbarch, 8);
1435
 
1436
  set_gdbarch_print_insn (gdbarch, print_insn_sparc);
1437
 
1438
  set_gdbarch_software_single_step (gdbarch, sparc_software_single_step);
1439
  set_gdbarch_write_pc (gdbarch, sparc_write_pc);
1440
 
1441
  set_gdbarch_unwind_dummy_id (gdbarch, sparc_unwind_dummy_id);
1442
 
1443
  set_gdbarch_unwind_pc (gdbarch, sparc_unwind_pc);
1444
 
1445
  frame_base_set_default (gdbarch, &sparc32_frame_base);
1446
 
1447
  /* Hook in the DWARF CFI frame unwinder.  */
1448
  dwarf2_frame_set_init_reg (gdbarch, sparc32_dwarf2_frame_init_reg);
1449
  /* FIXME: kettenis/20050423: Don't enable the unwinder until the
1450
     StackGhost issues have been resolved.  */
1451
 
1452
  /* Hook in ABI-specific overrides, if they have been registered.  */
1453
  gdbarch_init_osabi (info, gdbarch);
1454
 
1455
  frame_unwind_append_sniffer (gdbarch, sparc32_frame_sniffer);
1456
 
1457
  /* If we have register sets, enable the generic core file support.  */
1458
  if (tdep->gregset)
1459
    set_gdbarch_regset_from_core_section (gdbarch,
1460
                                          sparc_regset_from_core_section);
1461
 
1462
  return gdbarch;
1463
}
1464
 
1465
/* Helper functions for dealing with register windows.  */
1466
 
1467
void
1468
sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum)
1469
{
1470
  int offset = 0;
1471
  gdb_byte buf[8];
1472
  int i;
1473
 
1474
  if (sp & 1)
1475
    {
1476
      /* Registers are 64-bit.  */
1477
      sp += BIAS;
1478
 
1479
      for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1480
        {
1481
          if (regnum == i || regnum == -1)
1482
            {
1483
              target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8);
1484
 
1485
              /* Handle StackGhost.  */
1486
              if (i == SPARC_I7_REGNUM)
1487
                {
1488
                  ULONGEST wcookie = sparc_fetch_wcookie ();
1489
                  ULONGEST i7 = extract_unsigned_integer (buf + offset, 8);
1490
 
1491
                  store_unsigned_integer (buf + offset, 8, i7 ^ wcookie);
1492
                }
1493
 
1494
              regcache_raw_supply (regcache, i, buf);
1495
            }
1496
        }
1497
    }
1498
  else
1499
    {
1500
      /* Registers are 32-bit.  Toss any sign-extension of the stack
1501
         pointer.  */
1502
      sp &= 0xffffffffUL;
1503
 
1504
      /* Clear out the top half of the temporary buffer, and put the
1505
         register value in the bottom half if we're in 64-bit mode.  */
1506
      if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64)
1507
        {
1508
          memset (buf, 0, 4);
1509
          offset = 4;
1510
        }
1511
 
1512
      for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1513
        {
1514
          if (regnum == i || regnum == -1)
1515
            {
1516
              target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4),
1517
                                  buf + offset, 4);
1518
 
1519
              /* Handle StackGhost.  */
1520
              if (i == SPARC_I7_REGNUM)
1521
                {
1522
                  ULONGEST wcookie = sparc_fetch_wcookie ();
1523
                  ULONGEST i7 = extract_unsigned_integer (buf + offset, 4);
1524
 
1525
                  store_unsigned_integer (buf + offset, 4, i7 ^ wcookie);
1526
                }
1527
 
1528
              regcache_raw_supply (regcache, i, buf);
1529
            }
1530
        }
1531
    }
1532
}
1533
 
1534
void
1535
sparc_collect_rwindow (const struct regcache *regcache,
1536
                       CORE_ADDR sp, int regnum)
1537
{
1538
  int offset = 0;
1539
  gdb_byte buf[8];
1540
  int i;
1541
 
1542
  if (sp & 1)
1543
    {
1544
      /* Registers are 64-bit.  */
1545
      sp += BIAS;
1546
 
1547
      for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1548
        {
1549
          if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i)
1550
            {
1551
              regcache_raw_collect (regcache, i, buf);
1552
 
1553
              /* Handle StackGhost.  */
1554
              if (i == SPARC_I7_REGNUM)
1555
                {
1556
                  ULONGEST wcookie = sparc_fetch_wcookie ();
1557
                  ULONGEST i7 = extract_unsigned_integer (buf + offset, 8);
1558
 
1559
                  store_unsigned_integer (buf, 8, i7 ^ wcookie);
1560
                }
1561
 
1562
              target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8);
1563
            }
1564
        }
1565
    }
1566
  else
1567
    {
1568
      /* Registers are 32-bit.  Toss any sign-extension of the stack
1569
         pointer.  */
1570
      sp &= 0xffffffffUL;
1571
 
1572
      /* Only use the bottom half if we're in 64-bit mode.  */
1573
      if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64)
1574
        offset = 4;
1575
 
1576
      for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1577
        {
1578
          if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i)
1579
            {
1580
              regcache_raw_collect (regcache, i, buf);
1581
 
1582
              /* Handle StackGhost.  */
1583
              if (i == SPARC_I7_REGNUM)
1584
                {
1585
                  ULONGEST wcookie = sparc_fetch_wcookie ();
1586
                  ULONGEST i7 = extract_unsigned_integer (buf + offset, 4);
1587
 
1588
                  store_unsigned_integer (buf + offset, 4, i7 ^ wcookie);
1589
                }
1590
 
1591
              target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4),
1592
                                   buf + offset, 4);
1593
            }
1594
        }
1595
    }
1596
}
1597
 
1598
/* Helper functions for dealing with register sets.  */
1599
 
1600
void
1601
sparc32_supply_gregset (const struct sparc_gregset *gregset,
1602
                        struct regcache *regcache,
1603
                        int regnum, const void *gregs)
1604
{
1605
  const gdb_byte *regs = gregs;
1606
  int i;
1607
 
1608
  if (regnum == SPARC32_PSR_REGNUM || regnum == -1)
1609
    regcache_raw_supply (regcache, SPARC32_PSR_REGNUM,
1610
                         regs + gregset->r_psr_offset);
1611
 
1612
  if (regnum == SPARC32_PC_REGNUM || regnum == -1)
1613
    regcache_raw_supply (regcache, SPARC32_PC_REGNUM,
1614
                         regs + gregset->r_pc_offset);
1615
 
1616
  if (regnum == SPARC32_NPC_REGNUM || regnum == -1)
1617
    regcache_raw_supply (regcache, SPARC32_NPC_REGNUM,
1618
                         regs + gregset->r_npc_offset);
1619
 
1620
  if (regnum == SPARC32_Y_REGNUM || regnum == -1)
1621
    regcache_raw_supply (regcache, SPARC32_Y_REGNUM,
1622
                         regs + gregset->r_y_offset);
1623
 
1624
  if (regnum == SPARC_G0_REGNUM || regnum == -1)
1625
    regcache_raw_supply (regcache, SPARC_G0_REGNUM, NULL);
1626
 
1627
  if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1)
1628
    {
1629
      int offset = gregset->r_g1_offset;
1630
 
1631
      for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++)
1632
        {
1633
          if (regnum == i || regnum == -1)
1634
            regcache_raw_supply (regcache, i, regs + offset);
1635
          offset += 4;
1636
        }
1637
    }
1638
 
1639
  if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1)
1640
    {
1641
      /* Not all of the register set variants include Locals and
1642
         Inputs.  For those that don't, we read them off the stack.  */
1643
      if (gregset->r_l0_offset == -1)
1644
        {
1645
          ULONGEST sp;
1646
 
1647
          regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp);
1648
          sparc_supply_rwindow (regcache, sp, regnum);
1649
        }
1650
      else
1651
        {
1652
          int offset = gregset->r_l0_offset;
1653
 
1654
          for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1655
            {
1656
              if (regnum == i || regnum == -1)
1657
                regcache_raw_supply (regcache, i, regs + offset);
1658
              offset += 4;
1659
            }
1660
        }
1661
    }
1662
}
1663
 
1664
void
1665
sparc32_collect_gregset (const struct sparc_gregset *gregset,
1666
                         const struct regcache *regcache,
1667
                         int regnum, void *gregs)
1668
{
1669
  gdb_byte *regs = gregs;
1670
  int i;
1671
 
1672
  if (regnum == SPARC32_PSR_REGNUM || regnum == -1)
1673
    regcache_raw_collect (regcache, SPARC32_PSR_REGNUM,
1674
                          regs + gregset->r_psr_offset);
1675
 
1676
  if (regnum == SPARC32_PC_REGNUM || regnum == -1)
1677
    regcache_raw_collect (regcache, SPARC32_PC_REGNUM,
1678
                          regs + gregset->r_pc_offset);
1679
 
1680
  if (regnum == SPARC32_NPC_REGNUM || regnum == -1)
1681
    regcache_raw_collect (regcache, SPARC32_NPC_REGNUM,
1682
                          regs + gregset->r_npc_offset);
1683
 
1684
  if (regnum == SPARC32_Y_REGNUM || regnum == -1)
1685
    regcache_raw_collect (regcache, SPARC32_Y_REGNUM,
1686
                          regs + gregset->r_y_offset);
1687
 
1688
  if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1)
1689
    {
1690
      int offset = gregset->r_g1_offset;
1691
 
1692
      /* %g0 is always zero.  */
1693
      for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++)
1694
        {
1695
          if (regnum == i || regnum == -1)
1696
            regcache_raw_collect (regcache, i, regs + offset);
1697
          offset += 4;
1698
        }
1699
    }
1700
 
1701
  if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1)
1702
    {
1703
      /* Not all of the register set variants include Locals and
1704
         Inputs.  For those that don't, we read them off the stack.  */
1705
      if (gregset->r_l0_offset != -1)
1706
        {
1707
          int offset = gregset->r_l0_offset;
1708
 
1709
          for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1710
            {
1711
              if (regnum == i || regnum == -1)
1712
                regcache_raw_collect (regcache, i, regs + offset);
1713
              offset += 4;
1714
            }
1715
        }
1716
    }
1717
}
1718
 
1719
void
1720
sparc32_supply_fpregset (struct regcache *regcache,
1721
                         int regnum, const void *fpregs)
1722
{
1723
  const gdb_byte *regs = fpregs;
1724
  int i;
1725
 
1726
  for (i = 0; i < 32; i++)
1727
    {
1728
      if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1)
1729
        regcache_raw_supply (regcache, SPARC_F0_REGNUM + i, regs + (i * 4));
1730
    }
1731
 
1732
  if (regnum == SPARC32_FSR_REGNUM || regnum == -1)
1733
    regcache_raw_supply (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4);
1734
}
1735
 
1736
void
1737
sparc32_collect_fpregset (const struct regcache *regcache,
1738
                          int regnum, void *fpregs)
1739
{
1740
  gdb_byte *regs = fpregs;
1741
  int i;
1742
 
1743
  for (i = 0; i < 32; i++)
1744
    {
1745
      if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1)
1746
        regcache_raw_collect (regcache, SPARC_F0_REGNUM + i, regs + (i * 4));
1747
    }
1748
 
1749
  if (regnum == SPARC32_FSR_REGNUM || regnum == -1)
1750
    regcache_raw_collect (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4);
1751
}
1752
 
1753
 
1754
/* SunOS 4.  */
1755
 
1756
/* From <machine/reg.h>.  */
1757
const struct sparc_gregset sparc32_sunos4_gregset =
1758
{
1759
 
1760
  1 * 4,                        /* %pc */
1761
  2 * 4,                        /* %npc */
1762
  3 * 4,                        /* %y */
1763
  -1,                           /* %wim */
1764
  -1,                           /* %tbr */
1765
  4 * 4,                        /* %g1 */
1766
  -1                            /* %l0 */
1767
};
1768
 
1769
 
1770
/* Provide a prototype to silence -Wmissing-prototypes.  */
1771
void _initialize_sparc_tdep (void);
1772
 
1773
void
1774
_initialize_sparc_tdep (void)
1775
{
1776
  register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init);
1777
 
1778
  /* Initialize the SPARC-specific register types.  */
1779
  sparc_init_types();
1780
}

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