OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [gdb/] [testsuite/] [gdb.arch/] [ppc64-atomic-inst.c] - Blame information for rev 294

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
/* This file is part of GDB, the GNU debugger.
2
 
3
   Copyright 2008 Free Software Foundation, Inc.
4
 
5
   This program is free software; you can redistribute it and/or modify
6
   it under the terms of the GNU General Public License as published by
7
   the Free Software Foundation; either version 3 of the License, or
8
   (at your option) any later version.
9
 
10
   This program is distributed in the hope that it will be useful,
11
   but WITHOUT ANY WARRANTY; without even the implied warranty of
12
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
   GNU General Public License for more details.
14
 
15
   You should have received a copy of the GNU General Public License
16
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
17
 
18
#include <stdio.h>
19
 
20
int main()
21
{
22
  unsigned int word = 0;
23
  unsigned int *word_addr = &word;
24
  unsigned long dword = 0;
25
  unsigned long *dword_addr = &dword;
26
 
27
  __asm __volatile ("1:     lwarx   %0,0,%2\n"              \
28
                    "       addi    %0,%0,1\n"              \
29
                    "       stwcx.  %0,0,%2\n"              \
30
                    "       bne-    1b"                     \
31
                    : "=&b" (word), "=m" (*word_addr)       \
32
                    : "b" (word_addr), "m" (*word_addr)     \
33
                    : "cr0", "memory");                     \
34
 
35
  __asm __volatile ("1:     ldarx   %0,0,%2\n"              \
36
                    "       addi    %0,%0,1\n"              \
37
                    "       stdcx.  %0,0,%2\n"              \
38
                    "       bne-    1b"                     \
39
                    : "=&b" (dword), "=m" (*dword_addr)     \
40
                    : "b" (dword_addr), "m" (*dword_addr)   \
41
                    : "cr0", "memory");                     \
42
 
43
  return 0;
44
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.