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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [include/] [opcode/] [arc.h] - Blame information for rev 301

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1 24 jeremybenn
/* Opcode table for the ARC.
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   Copyright 1994, 1995, 1997, 2001, 2002, 2003
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   Free Software Foundation, Inc.
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   Contributed by Doug Evans (dje@cygnus.com).
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   This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
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   the GNU Binutils.
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   GAS/GDB is free software; you can redistribute it and/or modify
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   it under the terms of the GNU General Public License as published by
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   the Free Software Foundation; either version 2, or (at your option)
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   any later version.
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   GAS/GDB is distributed in the hope that it will be useful,
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   but WITHOUT ANY WARRANTY; without even the implied warranty of
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   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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   GNU General Public License for more details.
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   You should have received a copy of the GNU General Public License
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   along with GAS or GDB; see the file COPYING. If not, write to
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   the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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   MA 02110-1301, USA.  */
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/* List of the various cpu types.
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   The tables currently use bit masks to say whether the instruction or
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   whatever is supported by a particular cpu.  This lets us have one entry
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   apply to several cpus.
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   The `base' cpu must be 0. The cpu type is treated independently of
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   endianness. The complete `mach' number includes endianness.
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   These values are internal to opcodes/bfd/binutils/gas.  */
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#define ARC_MACH_5 0
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#define ARC_MACH_6 1
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#define ARC_MACH_7 2
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#define ARC_MACH_8 4
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/* Additional cpu values can be inserted here and ARC_MACH_BIG moved down.  */
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#define ARC_MACH_BIG 16
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/* Mask of number of bits necessary to record cpu type.  */
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#define ARC_MACH_CPU_MASK (ARC_MACH_BIG - 1)
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/* Mask of number of bits necessary to record cpu type + endianness.  */
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#define ARC_MACH_MASK ((ARC_MACH_BIG << 1) - 1)
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/* Type to denote an ARC instruction (at least a 32 bit unsigned int).  */
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typedef unsigned int arc_insn;
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struct arc_opcode {
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  char *syntax;              /* syntax of insn  */
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  unsigned long mask, value; /* recognize insn if (op&mask) == value  */
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  int flags;                 /* various flag bits  */
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/* Values for `flags'.  */
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/* Return CPU number, given flag bits.  */
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#define ARC_OPCODE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK)
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/* Return MACH number, given flag bits.  */
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#define ARC_OPCODE_MACH(bits) ((bits) & ARC_MACH_MASK)
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/* First opcode flag bit available after machine mask.  */
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#define ARC_OPCODE_FLAG_START (ARC_MACH_MASK + 1)
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/* This insn is a conditional branch.  */
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#define ARC_OPCODE_COND_BRANCH (ARC_OPCODE_FLAG_START)
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#define SYNTAX_3OP             (ARC_OPCODE_COND_BRANCH << 1)
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#define SYNTAX_LENGTH          (SYNTAX_3OP                 )
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#define SYNTAX_2OP             (SYNTAX_3OP             << 1)
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#define OP1_MUST_BE_IMM        (SYNTAX_2OP             << 1)
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#define OP1_IMM_IMPLIED        (OP1_MUST_BE_IMM        << 1)
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#define SYNTAX_VALID           (OP1_IMM_IMPLIED        << 1)
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#define I(x) (((x) & 31) << 27)
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#define A(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGA)
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#define B(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGB)
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#define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC)
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#define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */
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/* These values are used to optimize assembly and disassembly.  Each insn
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   is on a list of related insns (same first letter for assembly, same
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   insn code for disassembly).  */
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  struct arc_opcode *next_asm;  /* Next instr to try during assembly.  */
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  struct arc_opcode *next_dis;  /* Next instr to try during disassembly.  */
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/* Macros to create the hash values for the lists.  */
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#define ARC_HASH_OPCODE(string) \
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  ((string)[0] >= 'a' && (string)[0] <= 'z' ? (string)[0] - 'a' : 26)
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#define ARC_HASH_ICODE(insn) \
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  ((unsigned int) (insn) >> 27)
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 /* Macros to access `next_asm', `next_dis' so users needn't care about the
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    underlying mechanism.  */
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#define ARC_OPCODE_NEXT_ASM(op) ((op)->next_asm)
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#define ARC_OPCODE_NEXT_DIS(op) ((op)->next_dis)
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};
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/* this is an "insert at front" linked list per Metaware spec
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   that new definitions override older ones.  */
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extern struct arc_opcode *arc_ext_opcodes;
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struct arc_operand_value {
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  char *name;          /* eg: "eq"  */
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  short value;         /* eg: 1  */
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  unsigned char type;  /* index into `arc_operands'  */
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  unsigned char flags; /* various flag bits  */
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/* Values for `flags'.  */
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/* Return CPU number, given flag bits.  */
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#define ARC_OPVAL_CPU(bits) ((bits) & ARC_MACH_CPU_MASK)
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/* Return MACH number, given flag bits.  */
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#define ARC_OPVAL_MACH(bits) ((bits) & ARC_MACH_MASK)
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};
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struct arc_ext_operand_value {
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  struct arc_ext_operand_value *next;
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  struct arc_operand_value operand;
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};
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extern struct arc_ext_operand_value *arc_ext_operands;
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126
struct arc_operand {
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/* One of the insn format chars.  */
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  unsigned char fmt;
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/* The number of bits in the operand (may be unused for a modifier).  */
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  unsigned char bits;
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133
/* How far the operand is left shifted in the instruction, or
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   the modifier's flag bit (may be unused for a modifier.  */
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  unsigned char shift;
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137
/* Various flag bits.  */
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  int flags;
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/* Values for `flags'.  */
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/* This operand is a suffix to the opcode.  */
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#define ARC_OPERAND_SUFFIX 1
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145
/* This operand is a relative branch displacement.  The disassembler
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   prints these symbolically if possible.  */
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#define ARC_OPERAND_RELATIVE_BRANCH 2
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/* This operand is an absolute branch address.  The disassembler
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   prints these symbolically if possible.  */
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#define ARC_OPERAND_ABSOLUTE_BRANCH 4
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/* This operand is an address.  The disassembler
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   prints these symbolically if possible.  */
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#define ARC_OPERAND_ADDRESS 8
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157
/* This operand is a long immediate value.  */
158
#define ARC_OPERAND_LIMM 0x10
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160
/* This operand takes signed values.  */
161
#define ARC_OPERAND_SIGNED 0x20
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163
/* This operand takes signed values, but also accepts a full positive
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   range of values.  That is, if bits is 16, it takes any value from
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   -0x8000 to 0xffff.  */
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#define ARC_OPERAND_SIGNOPT 0x40
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/* This operand should be regarded as a negative number for the
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   purposes of overflow checking (i.e., the normal most negative
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   number is disallowed and one more than the normal most positive
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   number is allowed).  This flag will only be set for a signed
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   operand.  */
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#define ARC_OPERAND_NEGATIVE 0x80
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/* This operand doesn't really exist.  The program uses these operands
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   in special ways.  */
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#define ARC_OPERAND_FAKE 0x100
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/* separate flags operand for j and jl instructions  */
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#define ARC_OPERAND_JUMPFLAGS 0x200
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182
/* allow warnings and errors to be issued after call to insert_xxxxxx  */
183
#define ARC_OPERAND_WARN  0x400
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#define ARC_OPERAND_ERROR 0x800
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/* this is a load operand */
187
#define ARC_OPERAND_LOAD  0x8000
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/* this is a store operand */
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#define ARC_OPERAND_STORE 0x10000
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192
/* Modifier values.  */
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/* A dot is required before a suffix.  Eg: .le  */
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#define ARC_MOD_DOT 0x1000
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/* A normal register is allowed (not used, but here for completeness).  */
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#define ARC_MOD_REG 0x2000
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199
/* An auxiliary register name is expected.  */
200
#define ARC_MOD_AUXREG 0x4000
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202
/* Sum of all ARC_MOD_XXX bits.  */
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#define ARC_MOD_BITS 0x7000
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205
/* Non-zero if the operand type is really a modifier.  */
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#define ARC_MOD_P(X) ((X) & ARC_MOD_BITS)
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/* enforce read/write only register restrictions  */
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#define ARC_REGISTER_READONLY    0x01
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#define ARC_REGISTER_WRITEONLY   0x02
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#define ARC_REGISTER_NOSHORT_CUT 0x04
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/* Insertion function.  This is used by the assembler.  To insert an
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   operand value into an instruction, check this field.
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216
   If it is NULL, execute
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   i |= (p & ((1 << o->bits) - 1)) << o->shift;
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   (I is the instruction which we are filling in, O is a pointer to
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   this structure, and OP is the opcode value; this assumes twos
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   complement arithmetic).
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   If this field is not NULL, then simply call it with the
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   instruction and the operand value.  It will return the new value
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   of the instruction.  If the ERRMSG argument is not NULL, then if
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   the operand value is illegal, *ERRMSG will be set to a warning
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   string (the operand will be inserted in any case).  If the
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   operand value is legal, *ERRMSG will be unchanged.
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   REG is non-NULL when inserting a register value.  */
230
 
231
  arc_insn (*insert)
232
    (arc_insn insn, const struct arc_operand *operand, int mods,
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     const struct arc_operand_value *reg, long value, const char **errmsg);
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235
/* Extraction function.  This is used by the disassembler.  To
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   extract this operand type from an instruction, check this field.
237
 
238
   If it is NULL, compute
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     op = ((i) >> o->shift) & ((1 << o->bits) - 1);
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     if ((o->flags & ARC_OPERAND_SIGNED) != 0
241
          && (op & (1 << (o->bits - 1))) != 0)
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       op -= 1 << o->bits;
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   (I is the instruction, O is a pointer to this structure, and OP
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   is the result; this assumes twos complement arithmetic).
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   If this field is not NULL, then simply call it with the
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   instruction value.  It will return the value of the operand.  If
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   the INVALID argument is not NULL, *INVALID will be set to
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   non-zero if this operand type can not actually be extracted from
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   this operand (i.e., the instruction does not match).  If the
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   operand is valid, *INVALID will not be changed.
252
 
253
   INSN is a pointer to an array of two `arc_insn's.  The first element is
254
   the insn, the second is the limm if present.
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256
   Operands that have a printable form like registers and suffixes have
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   their struct arc_operand_value pointer stored in OPVAL.  */
258
 
259
  long (*extract)
260
    (arc_insn *insn, const struct arc_operand *operand, int mods,
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     const struct arc_operand_value **opval, int *invalid);
262
};
263
 
264
/* Bits that say what version of cpu we have. These should be passed to
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   arc_init_opcode_tables. At present, all there is is the cpu type.  */
266
 
267
/* CPU number, given value passed to `arc_init_opcode_tables'.  */
268
#define ARC_HAVE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK)
269
/* MACH number, given value passed to `arc_init_opcode_tables'.  */
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#define ARC_HAVE_MACH(bits) ((bits) & ARC_MACH_MASK)
271
 
272
/* Special register values:  */
273
#define ARC_REG_SHIMM_UPDATE 61
274
#define ARC_REG_SHIMM 63
275
#define ARC_REG_LIMM 62
276
 
277
/* Non-zero if REG is a constant marker.  */
278
#define ARC_REG_CONSTANT_P(REG) ((REG) >= 61)
279
 
280
/* Positions and masks of various fields:  */
281
#define ARC_SHIFT_REGA 21
282
#define ARC_SHIFT_REGB 15
283
#define ARC_SHIFT_REGC 9
284
#define ARC_MASK_REG 63
285
 
286
/* Delay slot types.  */
287
#define ARC_DELAY_NONE 0   /* no delay slot */
288
#define ARC_DELAY_NORMAL 1 /* delay slot in both cases */
289
#define ARC_DELAY_JUMP 2   /* delay slot only if branch taken */
290
 
291
/* Non-zero if X will fit in a signed 9 bit field.  */
292
#define ARC_SHIMM_CONST_P(x) ((long) (x) >= -256 && (long) (x) <= 255)
293
 
294
extern const struct arc_operand arc_operands[];
295
extern const int arc_operand_count;
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extern struct arc_opcode arc_opcodes[];
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extern const int arc_opcodes_count;
298
extern const struct arc_operand_value arc_suffixes[];
299
extern const int arc_suffixes_count;
300
extern const struct arc_operand_value arc_reg_names[];
301
extern const int arc_reg_names_count;
302
extern unsigned char arc_operand_map[];
303
 
304
/* Utility fns in arc-opc.c.  */
305
int arc_get_opcode_mach (int, int);
306
 
307
/* `arc_opcode_init_tables' must be called before `arc_xxx_supported'.  */
308
void arc_opcode_init_tables (int);
309
void arc_opcode_init_insert (void);
310
void arc_opcode_init_extract (void);
311
const struct arc_opcode *arc_opcode_lookup_asm (const char *);
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const struct arc_opcode *arc_opcode_lookup_dis (unsigned int);
313
int arc_opcode_limm_p (long *);
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const struct arc_operand_value *arc_opcode_lookup_suffix
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  (const struct arc_operand *type, int value);
316
int arc_opcode_supported (const struct arc_opcode *);
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int arc_opval_supported (const struct arc_operand_value *);
318
int arc_limm_fixup_adjust (arc_insn);
319
int arc_insn_is_j (arc_insn);
320
int arc_insn_not_jl (arc_insn);
321
int arc_operand_type (int);
322
struct arc_operand_value *get_ext_suffix (char *);
323
int arc_get_noshortcut_flag (void);

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