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jeremybenn |
/* Header file for targets using CGEN: Cpu tools GENerator.
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Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005
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Free Software Foundation, Inc.
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This file is part of GDB, the GNU debugger, and the GNU Binutils.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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#ifndef CGEN_H
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#define CGEN_H
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#include "symcat.h"
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#include "cgen-bitset.h"
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/* ??? This file requires bfd.h but only to get bfd_vma.
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Seems like an awful lot to require just to get such a fundamental type.
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Perhaps the definition of bfd_vma can be moved outside of bfd.h.
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Or perhaps one could duplicate its definition in another file.
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Until such time, this file conditionally compiles definitions that require
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bfd_vma using __BFD_H_SEEN__. */
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/* Enums must be defined before they can be used.
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Allow them to be used in struct definitions, even though the enum must
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be defined elsewhere.
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If CGEN_ARCH isn't defined, this file is being included by something other
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than <arch>-desc.h. */
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/* Prepend the arch name, defined in <arch>-desc.h, and _cgen_ to symbol S.
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The lack of spaces in the arg list is important for non-stdc systems.
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This file is included by <arch>-desc.h.
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It can be included independently of <arch>-desc.h, in which case the arch
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dependent portions will be declared as "unknown_cgen_foo". */
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#ifndef CGEN_SYM
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#define CGEN_SYM(s) CONCAT3 (unknown,_cgen_,s)
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#endif
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/* This file contains the static (unchanging) pieces and as much other stuff
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as we can reasonably put here. It's generally cleaner to put stuff here
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rather than having it machine generated if possible. */
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/* The assembler syntax is made up of expressions (duh...).
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At the lowest level the values are mnemonics, register names, numbers, etc.
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Above that are subexpressions, if any (an example might be the
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"effective address" in m68k cpus). Subexpressions are wip.
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At the second highest level are the insns themselves. Above that are
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pseudo-insns, synthetic insns, and macros, if any. */
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/* Lots of cpu's have a fixed insn size, or one which rarely changes,
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and it's generally easier to handle these by treating the insn as an
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integer type, rather than an array of characters. So we allow targets
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to control this. When an integer type the value is in host byte order,
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when an array of characters the value is in target byte order. */
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typedef unsigned int CGEN_INSN_INT;
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#if CGEN_INT_INSN_P
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typedef CGEN_INSN_INT CGEN_INSN_BYTES;
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typedef CGEN_INSN_INT *CGEN_INSN_BYTES_PTR;
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#else
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typedef unsigned char *CGEN_INSN_BYTES;
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typedef unsigned char *CGEN_INSN_BYTES_PTR;
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#endif
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#ifdef __GNUC__
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#define CGEN_INLINE __inline__
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#else
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#define CGEN_INLINE
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#endif
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enum cgen_endian
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{
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CGEN_ENDIAN_UNKNOWN,
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CGEN_ENDIAN_LITTLE,
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CGEN_ENDIAN_BIG
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};
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/* Forward decl. */
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typedef struct cgen_insn CGEN_INSN;
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/* Opaque pointer version for use by external world. */
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typedef struct cgen_cpu_desc *CGEN_CPU_DESC;
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/* Attributes.
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Attributes are used to describe various random things associated with
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an object (ifield, hardware, operand, insn, whatever) and are specified
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as name/value pairs.
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Integer attributes computed at compile time are currently all that's
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supported, though adding string attributes and run-time computation is
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straightforward. Integer attribute values are always host int's
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(signed or unsigned). For portability, this means 32 bits.
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Integer attributes are further categorized as boolean, bitset, integer,
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and enum types. Boolean attributes appear frequently enough that they're
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recorded in one host int. This limits the maximum number of boolean
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attributes to 32, though that's a *lot* of attributes. */
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/* Type of attribute values. */
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typedef CGEN_BITSET CGEN_ATTR_VALUE_BITSET_TYPE;
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typedef int CGEN_ATTR_VALUE_ENUM_TYPE;
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typedef union
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{
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CGEN_ATTR_VALUE_BITSET_TYPE bitset;
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CGEN_ATTR_VALUE_ENUM_TYPE nonbitset;
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} CGEN_ATTR_VALUE_TYPE;
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/* Struct to record attribute information. */
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typedef struct
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{
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/* Boolean attributes. */
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unsigned int bool;
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/* Non-boolean integer attributes. */
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CGEN_ATTR_VALUE_TYPE nonbool[1];
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} CGEN_ATTR;
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/* Define a structure member for attributes with N non-boolean entries.
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There is no maximum number of non-boolean attributes.
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There is a maximum of 32 boolean attributes (since they are all recorded
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in one host int). */
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#define CGEN_ATTR_TYPE(n) \
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struct { unsigned int bool; \
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CGEN_ATTR_VALUE_TYPE nonbool[(n) ? (n) : 1]; }
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/* Return the boolean attributes. */
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#define CGEN_ATTR_BOOLS(a) ((a)->bool)
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/* Non-boolean attribute numbers are offset by this much. */
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#define CGEN_ATTR_NBOOL_OFFSET 32
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/* Given a boolean attribute number, return its mask. */
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#define CGEN_ATTR_MASK(attr) (1 << (attr))
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/* Return the value of boolean attribute ATTR in ATTRS. */
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#define CGEN_BOOL_ATTR(attrs, attr) ((CGEN_ATTR_MASK (attr) & (attrs)) != 0)
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/* Return value of attribute ATTR in ATTR_TABLE for OBJ.
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OBJ is a pointer to the entity that has the attributes
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(??? not used at present but is reserved for future purposes - eventually
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the goal is to allow recording attributes in source form and computing
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them lazily at runtime, not sure of the details yet). */
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#define CGEN_ATTR_VALUE(obj, attr_table, attr) \
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((unsigned int) (attr) < CGEN_ATTR_NBOOL_OFFSET \
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? ((CGEN_ATTR_BOOLS (attr_table) & CGEN_ATTR_MASK (attr)) != 0) \
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: ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET].nonbitset))
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#define CGEN_BITSET_ATTR_VALUE(obj, attr_table, attr) \
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((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET].bitset)
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/* Attribute name/value tables.
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These are used to assist parsing of descriptions at run-time. */
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typedef struct
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{
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const char * name;
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unsigned value;
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} CGEN_ATTR_ENTRY;
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/* For each domain (ifld,hw,operand,insn), list of attributes. */
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typedef struct
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{
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const char * name;
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const CGEN_ATTR_ENTRY * dfault;
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const CGEN_ATTR_ENTRY * vals;
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} CGEN_ATTR_TABLE;
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/* Instruction set variants. */
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typedef struct {
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const char *name;
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/* Default instruction size (in bits).
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This is used by the assembler when it encounters an unknown insn. */
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unsigned int default_insn_bitsize;
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/* Base instruction size (in bits).
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For non-LIW cpus this is generally the length of the smallest insn.
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For LIW cpus its wip (work-in-progress). For the m32r its 32. */
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unsigned int base_insn_bitsize;
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/* Minimum/maximum instruction size (in bits). */
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unsigned int min_insn_bitsize;
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unsigned int max_insn_bitsize;
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} CGEN_ISA;
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/* Machine variants. */
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typedef struct {
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const char *name;
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/* The argument to bfd_arch_info->scan. */
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const char *bfd_name;
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/* one of enum mach_attr */
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int num;
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/* parameter from mach->cpu */
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unsigned int insn_chunk_bitsize;
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} CGEN_MACH;
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/* Parse result (also extraction result).
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The result of parsing an insn is stored here.
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To generate the actual insn, this is passed to the insert handler.
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When printing an insn, the result of extraction is stored here.
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To print the insn, this is passed to the print handler.
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It is machine generated so we don't define it here,
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but we do need a forward decl for the handler fns.
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There is one member for each possible field in the insn.
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The type depends on the field.
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Also recorded here is the computed length of the insn for architectures
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where it varies.
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*/
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typedef struct cgen_fields CGEN_FIELDS;
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/* Total length of the insn, as recorded in the `fields' struct. */
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/* ??? The field insert handler has lots of opportunities for optimization
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if it ever gets inlined. On architectures where insns all have the same
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size, may wish to detect that and make this macro a constant - to allow
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further optimizations. */
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#define CGEN_FIELDS_BITSIZE(fields) ((fields)->length)
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/* Extraction support for variable length insn sets. */
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/* When disassembling we don't know the number of bytes to read at the start.
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So the first CGEN_BASE_INSN_SIZE bytes are read at the start and the rest
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are read when needed. This struct controls this. It is basically the
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disassemble_info stuff, except that we provide a cache for values already
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read (since bytes can typically be read several times to fetch multiple
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operands that may be in them), and that extraction of fields is needed
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in contexts other than disassembly. */
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typedef struct {
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/* A pointer to the disassemble_info struct.
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We don't require dis-asm.h so we use void * for the type here.
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If NULL, BYTES is full of valid data (VALID == -1). */
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void *dis_info;
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/* Points to a working buffer of sufficient size. */
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unsigned char *insn_bytes;
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/* Mask of bytes that are valid in INSN_BYTES. */
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unsigned int valid;
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} CGEN_EXTRACT_INFO;
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/* Associated with each insn or expression is a set of "handlers" for
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performing operations like parsing, printing, etc. These require a bfd_vma
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value to be passed around but we don't want all applications to need bfd.h.
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So this stuff is only provided if bfd.h has been included. */
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/* Parse handler.
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CD is a cpu table descriptor.
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INSN is a pointer to a struct describing the insn being parsed.
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STRP is a pointer to a pointer to the text being parsed.
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FIELDS is a pointer to a cgen_fields struct in which the results are placed.
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If the expression is successfully parsed, *STRP is updated.
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If not it is left alone.
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The result is NULL if success or an error message. */
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typedef const char * (cgen_parse_fn)
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(CGEN_CPU_DESC, const CGEN_INSN *insn_,
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const char **strp_, CGEN_FIELDS *fields_);
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/* Insert handler.
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CD is a cpu table descriptor.
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INSN is a pointer to a struct describing the insn being parsed.
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FIELDS is a pointer to a cgen_fields struct from which the values
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are fetched.
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INSNP is a pointer to a buffer in which to place the insn.
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PC is the pc value of the insn.
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The result is an error message or NULL if success. */
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#ifdef __BFD_H_SEEN__
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typedef const char * (cgen_insert_fn)
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(CGEN_CPU_DESC, const CGEN_INSN *insn_,
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CGEN_FIELDS *fields_, CGEN_INSN_BYTES_PTR insnp_,
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bfd_vma pc_);
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#else
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typedef const char * (cgen_insert_fn) ();
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#endif
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/* Extract handler.
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CD is a cpu table descriptor.
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INSN is a pointer to a struct describing the insn being parsed.
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The second argument is a pointer to a struct controlling extraction
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(only used for variable length insns).
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EX_INFO is a pointer to a struct for controlling reading of further
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bytes for the insn.
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BASE_INSN is the first CGEN_BASE_INSN_SIZE bytes (host order).
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FIELDS is a pointer to a cgen_fields struct in which the results are placed.
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PC is the pc value of the insn.
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The result is the length of the insn in bits or zero if not recognized. */
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#ifdef __BFD_H_SEEN__
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typedef int (cgen_extract_fn)
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(CGEN_CPU_DESC, const CGEN_INSN *insn_,
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CGEN_EXTRACT_INFO *ex_info_, CGEN_INSN_INT base_insn_,
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CGEN_FIELDS *fields_, bfd_vma pc_);
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#else
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typedef int (cgen_extract_fn) ();
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#endif
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/* Print handler.
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CD is a cpu table descriptor.
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INFO is a pointer to the disassembly info.
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Eg: disassemble_info. It's defined as `PTR' so this file can be included
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without dis-asm.h.
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INSN is a pointer to a struct describing the insn being printed.
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FIELDS is a pointer to a cgen_fields struct.
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PC is the pc value of the insn.
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LEN is the length of the insn, in bits. */
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#ifdef __BFD_H_SEEN__
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typedef void (cgen_print_fn)
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(CGEN_CPU_DESC, void * info_, const CGEN_INSN *insn_,
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CGEN_FIELDS *fields_, bfd_vma pc_, int len_);
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#else
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typedef void (cgen_print_fn) ();
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#endif
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/* Parse/insert/extract/print handlers.
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Indices into the handler tables.
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We could use pointers here instead, but 90% of them are generally identical
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and that's a lot of redundant data. Making these unsigned char indices
|
343 |
|
|
into tables of pointers saves a bit of space.
|
344 |
|
|
Using indices also keeps assembler code out of the disassembler and
|
345 |
|
|
vice versa. */
|
346 |
|
|
|
347 |
|
|
struct cgen_opcode_handler
|
348 |
|
|
{
|
349 |
|
|
unsigned char parse, insert, extract, print;
|
350 |
|
|
};
|
351 |
|
|
|
352 |
|
|
/* Assembler interface.
|
353 |
|
|
|
354 |
|
|
The interface to the assembler is intended to be clean in the sense that
|
355 |
|
|
libopcodes.a is a standalone entity and could be used with any assembler.
|
356 |
|
|
Not that one would necessarily want to do that but rather that it helps
|
357 |
|
|
keep a clean interface. The interface will obviously be slanted towards
|
358 |
|
|
GAS, but at least it's a start.
|
359 |
|
|
??? Note that one possible user of the assembler besides GAS is GDB.
|
360 |
|
|
|
361 |
|
|
Parsing is controlled by the assembler which calls
|
362 |
|
|
CGEN_SYM (assemble_insn). If it can parse and build the entire insn
|
363 |
|
|
it doesn't call back to the assembler. If it needs/wants to call back
|
364 |
|
|
to the assembler, cgen_parse_operand_fn is called which can either
|
365 |
|
|
|
366 |
|
|
- return a number to be inserted in the insn
|
367 |
|
|
- return a "register" value to be inserted
|
368 |
|
|
(the register might not be a register per pe)
|
369 |
|
|
- queue the argument and return a marker saying the expression has been
|
370 |
|
|
queued (eg: a fix-up)
|
371 |
|
|
- return an error message indicating the expression wasn't recognizable
|
372 |
|
|
|
373 |
|
|
The result is an error message or NULL for success.
|
374 |
|
|
The parsed value is stored in the bfd_vma *. */
|
375 |
|
|
|
376 |
|
|
/* Values for indicating what the caller wants. */
|
377 |
|
|
|
378 |
|
|
enum cgen_parse_operand_type
|
379 |
|
|
{
|
380 |
|
|
CGEN_PARSE_OPERAND_INIT,
|
381 |
|
|
CGEN_PARSE_OPERAND_INTEGER,
|
382 |
|
|
CGEN_PARSE_OPERAND_ADDRESS,
|
383 |
|
|
CGEN_PARSE_OPERAND_SYMBOLIC
|
384 |
|
|
};
|
385 |
|
|
|
386 |
|
|
/* Values for indicating what was parsed. */
|
387 |
|
|
|
388 |
|
|
enum cgen_parse_operand_result
|
389 |
|
|
{
|
390 |
|
|
CGEN_PARSE_OPERAND_RESULT_NUMBER,
|
391 |
|
|
CGEN_PARSE_OPERAND_RESULT_REGISTER,
|
392 |
|
|
CGEN_PARSE_OPERAND_RESULT_QUEUED,
|
393 |
|
|
CGEN_PARSE_OPERAND_RESULT_ERROR
|
394 |
|
|
};
|
395 |
|
|
|
396 |
|
|
#ifdef __BFD_H_SEEN__ /* Don't require bfd.h unnecessarily. */
|
397 |
|
|
typedef const char * (cgen_parse_operand_fn)
|
398 |
|
|
(CGEN_CPU_DESC,
|
399 |
|
|
enum cgen_parse_operand_type, const char **, int, int,
|
400 |
|
|
enum cgen_parse_operand_result *, bfd_vma *);
|
401 |
|
|
#else
|
402 |
|
|
typedef const char * (cgen_parse_operand_fn) ();
|
403 |
|
|
#endif
|
404 |
|
|
|
405 |
|
|
/* Set the cgen_parse_operand_fn callback. */
|
406 |
|
|
|
407 |
|
|
extern void cgen_set_parse_operand_fn
|
408 |
|
|
(CGEN_CPU_DESC, cgen_parse_operand_fn);
|
409 |
|
|
|
410 |
|
|
/* Called before trying to match a table entry with the insn. */
|
411 |
|
|
|
412 |
|
|
extern void cgen_init_parse_operand (CGEN_CPU_DESC);
|
413 |
|
|
|
414 |
|
|
/* Operand values (keywords, integers, symbols, etc.) */
|
415 |
|
|
|
416 |
|
|
/* Types of assembler elements. */
|
417 |
|
|
|
418 |
|
|
enum cgen_asm_type
|
419 |
|
|
{
|
420 |
|
|
CGEN_ASM_NONE, CGEN_ASM_KEYWORD, CGEN_ASM_MAX
|
421 |
|
|
};
|
422 |
|
|
|
423 |
|
|
#ifndef CGEN_ARCH
|
424 |
|
|
enum cgen_hw_type { CGEN_HW_MAX };
|
425 |
|
|
#endif
|
426 |
|
|
|
427 |
|
|
/* List of hardware elements. */
|
428 |
|
|
|
429 |
|
|
typedef struct
|
430 |
|
|
{
|
431 |
|
|
char *name;
|
432 |
|
|
enum cgen_hw_type type;
|
433 |
|
|
/* There is currently no example where both index specs and value specs
|
434 |
|
|
are required, so for now both are clumped under "asm_data". */
|
435 |
|
|
enum cgen_asm_type asm_type;
|
436 |
|
|
void *asm_data;
|
437 |
|
|
#ifndef CGEN_HW_NBOOL_ATTRS
|
438 |
|
|
#define CGEN_HW_NBOOL_ATTRS 1
|
439 |
|
|
#endif
|
440 |
|
|
CGEN_ATTR_TYPE (CGEN_HW_NBOOL_ATTRS) attrs;
|
441 |
|
|
#define CGEN_HW_ATTRS(hw) (&(hw)->attrs)
|
442 |
|
|
} CGEN_HW_ENTRY;
|
443 |
|
|
|
444 |
|
|
/* Return value of attribute ATTR in HW. */
|
445 |
|
|
|
446 |
|
|
#define CGEN_HW_ATTR_VALUE(hw, attr) \
|
447 |
|
|
CGEN_ATTR_VALUE ((hw), CGEN_HW_ATTRS (hw), (attr))
|
448 |
|
|
|
449 |
|
|
/* Table of hardware elements for selected mach, computed at runtime.
|
450 |
|
|
enum cgen_hw_type is an index into this table (specifically `entries'). */
|
451 |
|
|
|
452 |
|
|
typedef struct {
|
453 |
|
|
/* Pointer to null terminated table of all compiled in entries. */
|
454 |
|
|
const CGEN_HW_ENTRY *init_entries;
|
455 |
|
|
unsigned int entry_size; /* since the attribute member is variable sized */
|
456 |
|
|
/* Array of all entries, initial and run-time added. */
|
457 |
|
|
const CGEN_HW_ENTRY **entries;
|
458 |
|
|
/* Number of elements in `entries'. */
|
459 |
|
|
unsigned int num_entries;
|
460 |
|
|
/* For now, xrealloc is called each time a new entry is added at runtime.
|
461 |
|
|
??? May wish to keep track of some slop to reduce the number of calls to
|
462 |
|
|
xrealloc, except that there's unlikely to be many and not expected to be
|
463 |
|
|
in speed critical code. */
|
464 |
|
|
} CGEN_HW_TABLE;
|
465 |
|
|
|
466 |
|
|
extern const CGEN_HW_ENTRY * cgen_hw_lookup_by_name
|
467 |
|
|
(CGEN_CPU_DESC, const char *);
|
468 |
|
|
extern const CGEN_HW_ENTRY * cgen_hw_lookup_by_num
|
469 |
|
|
(CGEN_CPU_DESC, unsigned int);
|
470 |
|
|
|
471 |
|
|
/* This struct is used to describe things like register names, etc. */
|
472 |
|
|
|
473 |
|
|
typedef struct cgen_keyword_entry
|
474 |
|
|
{
|
475 |
|
|
/* Name (as in register name). */
|
476 |
|
|
char * name;
|
477 |
|
|
|
478 |
|
|
/* Value (as in register number).
|
479 |
|
|
The value cannot be -1 as that is used to indicate "not found".
|
480 |
|
|
IDEA: Have "FUNCTION" attribute? [function is called to fetch value]. */
|
481 |
|
|
int value;
|
482 |
|
|
|
483 |
|
|
/* Attributes.
|
484 |
|
|
This should, but technically needn't, appear last. It is a variable sized
|
485 |
|
|
array in that one architecture may have 1 nonbool attribute and another
|
486 |
|
|
may have more. Having this last means the non-architecture specific code
|
487 |
|
|
needn't care. The goal is to eventually record
|
488 |
|
|
attributes in their raw form, evaluate them at run-time, and cache the
|
489 |
|
|
values, so this worry will go away anyway. */
|
490 |
|
|
/* ??? Moving this last should be done by treating keywords like insn lists
|
491 |
|
|
and moving the `next' fields into a CGEN_KEYWORD_LIST struct. */
|
492 |
|
|
/* FIXME: Not used yet. */
|
493 |
|
|
#ifndef CGEN_KEYWORD_NBOOL_ATTRS
|
494 |
|
|
#define CGEN_KEYWORD_NBOOL_ATTRS 1
|
495 |
|
|
#endif
|
496 |
|
|
CGEN_ATTR_TYPE (CGEN_KEYWORD_NBOOL_ATTRS) attrs;
|
497 |
|
|
|
498 |
|
|
/* ??? Putting these here means compiled in entries can't be const.
|
499 |
|
|
Not a really big deal, but something to consider. */
|
500 |
|
|
/* Next name hash table entry. */
|
501 |
|
|
struct cgen_keyword_entry *next_name;
|
502 |
|
|
/* Next value hash table entry. */
|
503 |
|
|
struct cgen_keyword_entry *next_value;
|
504 |
|
|
} CGEN_KEYWORD_ENTRY;
|
505 |
|
|
|
506 |
|
|
/* Top level struct for describing a set of related keywords
|
507 |
|
|
(e.g. register names).
|
508 |
|
|
|
509 |
|
|
This struct supports run-time entry of new values, and hashed lookups. */
|
510 |
|
|
|
511 |
|
|
typedef struct cgen_keyword
|
512 |
|
|
{
|
513 |
|
|
/* Pointer to initial [compiled in] values. */
|
514 |
|
|
CGEN_KEYWORD_ENTRY *init_entries;
|
515 |
|
|
|
516 |
|
|
/* Number of entries in `init_entries'. */
|
517 |
|
|
unsigned int num_init_entries;
|
518 |
|
|
|
519 |
|
|
/* Hash table used for name lookup. */
|
520 |
|
|
CGEN_KEYWORD_ENTRY **name_hash_table;
|
521 |
|
|
|
522 |
|
|
/* Hash table used for value lookup. */
|
523 |
|
|
CGEN_KEYWORD_ENTRY **value_hash_table;
|
524 |
|
|
|
525 |
|
|
/* Number of entries in the hash_tables. */
|
526 |
|
|
unsigned int hash_table_size;
|
527 |
|
|
|
528 |
|
|
/* Pointer to null keyword "" entry if present. */
|
529 |
|
|
const CGEN_KEYWORD_ENTRY *null_entry;
|
530 |
|
|
|
531 |
|
|
/* String containing non-alphanumeric characters used
|
532 |
|
|
in keywords.
|
533 |
|
|
At present, the highest number of entries used is 1. */
|
534 |
|
|
char nonalpha_chars[8];
|
535 |
|
|
} CGEN_KEYWORD;
|
536 |
|
|
|
537 |
|
|
/* Structure used for searching. */
|
538 |
|
|
|
539 |
|
|
typedef struct
|
540 |
|
|
{
|
541 |
|
|
/* Table being searched. */
|
542 |
|
|
const CGEN_KEYWORD *table;
|
543 |
|
|
|
544 |
|
|
/* Specification of what is being searched for. */
|
545 |
|
|
const char *spec;
|
546 |
|
|
|
547 |
|
|
/* Current index in hash table. */
|
548 |
|
|
unsigned int current_hash;
|
549 |
|
|
|
550 |
|
|
/* Current element in current hash chain. */
|
551 |
|
|
CGEN_KEYWORD_ENTRY *current_entry;
|
552 |
|
|
} CGEN_KEYWORD_SEARCH;
|
553 |
|
|
|
554 |
|
|
/* Lookup a keyword from its name. */
|
555 |
|
|
|
556 |
|
|
const CGEN_KEYWORD_ENTRY *cgen_keyword_lookup_name
|
557 |
|
|
(CGEN_KEYWORD *, const char *);
|
558 |
|
|
|
559 |
|
|
/* Lookup a keyword from its value. */
|
560 |
|
|
|
561 |
|
|
const CGEN_KEYWORD_ENTRY *cgen_keyword_lookup_value
|
562 |
|
|
(CGEN_KEYWORD *, int);
|
563 |
|
|
|
564 |
|
|
/* Add a keyword. */
|
565 |
|
|
|
566 |
|
|
void cgen_keyword_add (CGEN_KEYWORD *, CGEN_KEYWORD_ENTRY *);
|
567 |
|
|
|
568 |
|
|
/* Keyword searching.
|
569 |
|
|
This can be used to retrieve every keyword, or a subset. */
|
570 |
|
|
|
571 |
|
|
CGEN_KEYWORD_SEARCH cgen_keyword_search_init
|
572 |
|
|
(CGEN_KEYWORD *, const char *);
|
573 |
|
|
const CGEN_KEYWORD_ENTRY *cgen_keyword_search_next
|
574 |
|
|
(CGEN_KEYWORD_SEARCH *);
|
575 |
|
|
|
576 |
|
|
/* Operand value support routines. */
|
577 |
|
|
|
578 |
|
|
extern const char *cgen_parse_keyword
|
579 |
|
|
(CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *);
|
580 |
|
|
#ifdef __BFD_H_SEEN__ /* Don't require bfd.h unnecessarily. */
|
581 |
|
|
extern const char *cgen_parse_signed_integer
|
582 |
|
|
(CGEN_CPU_DESC, const char **, int, long *);
|
583 |
|
|
extern const char *cgen_parse_unsigned_integer
|
584 |
|
|
(CGEN_CPU_DESC, const char **, int, unsigned long *);
|
585 |
|
|
extern const char *cgen_parse_address
|
586 |
|
|
(CGEN_CPU_DESC, const char **, int, int,
|
587 |
|
|
enum cgen_parse_operand_result *, bfd_vma *);
|
588 |
|
|
extern const char *cgen_validate_signed_integer
|
589 |
|
|
(long, long, long);
|
590 |
|
|
extern const char *cgen_validate_unsigned_integer
|
591 |
|
|
(unsigned long, unsigned long, unsigned long);
|
592 |
|
|
#endif
|
593 |
|
|
|
594 |
|
|
/* Operand modes. */
|
595 |
|
|
|
596 |
|
|
/* ??? This duplicates the values in arch.h. Revisit.
|
597 |
|
|
These however need the CGEN_ prefix [as does everything in this file]. */
|
598 |
|
|
/* ??? Targets may need to add their own modes so we may wish to move this
|
599 |
|
|
to <arch>-opc.h, or add a hook. */
|
600 |
|
|
|
601 |
|
|
enum cgen_mode {
|
602 |
|
|
CGEN_MODE_VOID, /* ??? rename simulator's VM to VOID? */
|
603 |
|
|
CGEN_MODE_BI, CGEN_MODE_QI, CGEN_MODE_HI, CGEN_MODE_SI, CGEN_MODE_DI,
|
604 |
|
|
CGEN_MODE_UBI, CGEN_MODE_UQI, CGEN_MODE_UHI, CGEN_MODE_USI, CGEN_MODE_UDI,
|
605 |
|
|
CGEN_MODE_SF, CGEN_MODE_DF, CGEN_MODE_XF, CGEN_MODE_TF,
|
606 |
|
|
CGEN_MODE_TARGET_MAX,
|
607 |
|
|
CGEN_MODE_INT, CGEN_MODE_UINT,
|
608 |
|
|
CGEN_MODE_MAX
|
609 |
|
|
};
|
610 |
|
|
|
611 |
|
|
/* FIXME: Until simulator is updated. */
|
612 |
|
|
|
613 |
|
|
#define CGEN_MODE_VM CGEN_MODE_VOID
|
614 |
|
|
|
615 |
|
|
/* Operands. */
|
616 |
|
|
|
617 |
|
|
#ifndef CGEN_ARCH
|
618 |
|
|
enum cgen_operand_type { CGEN_OPERAND_MAX };
|
619 |
|
|
#endif
|
620 |
|
|
|
621 |
|
|
/* "nil" indicator for the operand instance table */
|
622 |
|
|
#define CGEN_OPERAND_NIL CGEN_OPERAND_MAX
|
623 |
|
|
|
624 |
|
|
/* A tree of these structs represents the multi-ifield
|
625 |
|
|
structure of an operand's hw-index value, if it exists. */
|
626 |
|
|
|
627 |
|
|
struct cgen_ifld;
|
628 |
|
|
|
629 |
|
|
typedef struct cgen_maybe_multi_ifield
|
630 |
|
|
{
|
631 |
|
|
int count; /* 0: indexed by single cgen_ifld (possibly null: dead entry);
|
632 |
|
|
n: indexed by array of more cgen_maybe_multi_ifields. */
|
633 |
|
|
union
|
634 |
|
|
{
|
635 |
|
|
const void *p;
|
636 |
|
|
const struct cgen_maybe_multi_ifield * multi;
|
637 |
|
|
const struct cgen_ifld * leaf;
|
638 |
|
|
} val;
|
639 |
|
|
}
|
640 |
|
|
CGEN_MAYBE_MULTI_IFLD;
|
641 |
|
|
|
642 |
|
|
/* This struct defines each entry in the operand table. */
|
643 |
|
|
|
644 |
|
|
typedef struct
|
645 |
|
|
{
|
646 |
|
|
/* Name as it appears in the syntax string. */
|
647 |
|
|
char *name;
|
648 |
|
|
|
649 |
|
|
/* Operand type. */
|
650 |
|
|
enum cgen_operand_type type;
|
651 |
|
|
|
652 |
|
|
/* The hardware element associated with this operand. */
|
653 |
|
|
enum cgen_hw_type hw_type;
|
654 |
|
|
|
655 |
|
|
/* FIXME: We don't yet record ifield definitions, which we should.
|
656 |
|
|
When we do it might make sense to delete start/length (since they will
|
657 |
|
|
be duplicated in the ifield's definition) and replace them with a
|
658 |
|
|
pointer to the ifield entry. */
|
659 |
|
|
|
660 |
|
|
/* Bit position.
|
661 |
|
|
This is just a hint, and may be unused in more complex operands.
|
662 |
|
|
May be unused for a modifier. */
|
663 |
|
|
unsigned char start;
|
664 |
|
|
|
665 |
|
|
/* The number of bits in the operand.
|
666 |
|
|
This is just a hint, and may be unused in more complex operands.
|
667 |
|
|
May be unused for a modifier. */
|
668 |
|
|
unsigned char length;
|
669 |
|
|
|
670 |
|
|
/* The (possibly-multi) ifield used as an index for this operand, if it
|
671 |
|
|
is indexed by a field at all. This substitutes / extends the start and
|
672 |
|
|
length fields above, but unsure at this time whether they are used
|
673 |
|
|
anywhere. */
|
674 |
|
|
CGEN_MAYBE_MULTI_IFLD index_fields;
|
675 |
|
|
#if 0 /* ??? Interesting idea but relocs tend to get too complicated,
|
676 |
|
|
and ABI dependent, for simple table lookups to work. */
|
677 |
|
|
/* Ideally this would be the internal (external?) reloc type. */
|
678 |
|
|
int reloc_type;
|
679 |
|
|
#endif
|
680 |
|
|
|
681 |
|
|
/* Attributes.
|
682 |
|
|
This should, but technically needn't, appear last. It is a variable sized
|
683 |
|
|
array in that one architecture may have 1 nonbool attribute and another
|
684 |
|
|
may have more. Having this last means the non-architecture specific code
|
685 |
|
|
needn't care, now or tomorrow. The goal is to eventually record
|
686 |
|
|
attributes in their raw form, evaluate them at run-time, and cache the
|
687 |
|
|
values, so this worry will go away anyway. */
|
688 |
|
|
#ifndef CGEN_OPERAND_NBOOL_ATTRS
|
689 |
|
|
#define CGEN_OPERAND_NBOOL_ATTRS 1
|
690 |
|
|
#endif
|
691 |
|
|
CGEN_ATTR_TYPE (CGEN_OPERAND_NBOOL_ATTRS) attrs;
|
692 |
|
|
#define CGEN_OPERAND_ATTRS(operand) (&(operand)->attrs)
|
693 |
|
|
} CGEN_OPERAND;
|
694 |
|
|
|
695 |
|
|
/* Return value of attribute ATTR in OPERAND. */
|
696 |
|
|
|
697 |
|
|
#define CGEN_OPERAND_ATTR_VALUE(operand, attr) \
|
698 |
|
|
CGEN_ATTR_VALUE ((operand), CGEN_OPERAND_ATTRS (operand), (attr))
|
699 |
|
|
|
700 |
|
|
/* Table of operands for selected mach/isa, computed at runtime.
|
701 |
|
|
enum cgen_operand_type is an index into this table (specifically
|
702 |
|
|
`entries'). */
|
703 |
|
|
|
704 |
|
|
typedef struct {
|
705 |
|
|
/* Pointer to null terminated table of all compiled in entries. */
|
706 |
|
|
const CGEN_OPERAND *init_entries;
|
707 |
|
|
unsigned int entry_size; /* since the attribute member is variable sized */
|
708 |
|
|
/* Array of all entries, initial and run-time added. */
|
709 |
|
|
const CGEN_OPERAND **entries;
|
710 |
|
|
/* Number of elements in `entries'. */
|
711 |
|
|
unsigned int num_entries;
|
712 |
|
|
/* For now, xrealloc is called each time a new entry is added at runtime.
|
713 |
|
|
??? May wish to keep track of some slop to reduce the number of calls to
|
714 |
|
|
xrealloc, except that there's unlikely to be many and not expected to be
|
715 |
|
|
in speed critical code. */
|
716 |
|
|
} CGEN_OPERAND_TABLE;
|
717 |
|
|
|
718 |
|
|
extern const CGEN_OPERAND * cgen_operand_lookup_by_name
|
719 |
|
|
(CGEN_CPU_DESC, const char *);
|
720 |
|
|
extern const CGEN_OPERAND * cgen_operand_lookup_by_num
|
721 |
|
|
(CGEN_CPU_DESC, int);
|
722 |
|
|
|
723 |
|
|
/* Instruction operand instances.
|
724 |
|
|
|
725 |
|
|
For each instruction, a list of the hardware elements that are read and
|
726 |
|
|
written are recorded. */
|
727 |
|
|
|
728 |
|
|
/* The type of the instance. */
|
729 |
|
|
|
730 |
|
|
enum cgen_opinst_type {
|
731 |
|
|
/* End of table marker. */
|
732 |
|
|
CGEN_OPINST_END = 0,
|
733 |
|
|
CGEN_OPINST_INPUT, CGEN_OPINST_OUTPUT
|
734 |
|
|
};
|
735 |
|
|
|
736 |
|
|
typedef struct
|
737 |
|
|
{
|
738 |
|
|
/* Input or output indicator. */
|
739 |
|
|
enum cgen_opinst_type type;
|
740 |
|
|
|
741 |
|
|
/* Name of operand. */
|
742 |
|
|
const char *name;
|
743 |
|
|
|
744 |
|
|
/* The hardware element referenced. */
|
745 |
|
|
enum cgen_hw_type hw_type;
|
746 |
|
|
|
747 |
|
|
/* The mode in which the operand is being used. */
|
748 |
|
|
enum cgen_mode mode;
|
749 |
|
|
|
750 |
|
|
/* The operand table entry CGEN_OPERAND_NIL if there is none
|
751 |
|
|
(i.e. an explicit hardware reference). */
|
752 |
|
|
enum cgen_operand_type op_type;
|
753 |
|
|
|
754 |
|
|
/* If `operand' is "nil", the index (e.g. into array of registers). */
|
755 |
|
|
int index;
|
756 |
|
|
|
757 |
|
|
/* Attributes.
|
758 |
|
|
??? This perhaps should be a real attribute struct but there's
|
759 |
|
|
no current need, so we save a bit of space and just have a set of
|
760 |
|
|
flags. The interface is such that this can easily be made attributes
|
761 |
|
|
should it prove useful. */
|
762 |
|
|
unsigned int attrs;
|
763 |
|
|
#define CGEN_OPINST_ATTRS(opinst) ((opinst)->attrs)
|
764 |
|
|
/* Return value of attribute ATTR in OPINST. */
|
765 |
|
|
#define CGEN_OPINST_ATTR(opinst, attr) \
|
766 |
|
|
((CGEN_OPINST_ATTRS (opinst) & (attr)) != 0)
|
767 |
|
|
/* Operand is conditionally referenced (read/written). */
|
768 |
|
|
#define CGEN_OPINST_COND_REF 1
|
769 |
|
|
} CGEN_OPINST;
|
770 |
|
|
|
771 |
|
|
/* Syntax string.
|
772 |
|
|
|
773 |
|
|
Each insn format and subexpression has one of these.
|
774 |
|
|
|
775 |
|
|
The syntax "string" consists of characters (n > 0 && n < 128), and operand
|
776 |
|
|
values (n >= 128), and is terminated by 0. Operand values are 128 + index
|
777 |
|
|
into the operand table. The operand table doesn't exist in C, per se, as
|
778 |
|
|
the data is recorded in the parse/insert/extract/print switch statements. */
|
779 |
|
|
|
780 |
|
|
/* This should be at least as large as necessary for any target. */
|
781 |
|
|
#define CGEN_MAX_SYNTAX_ELEMENTS 48
|
782 |
|
|
|
783 |
|
|
/* A target may know its own precise maximum. Assert that it falls below
|
784 |
|
|
the above limit. */
|
785 |
|
|
#ifdef CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS
|
786 |
|
|
#if CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS > CGEN_MAX_SYNTAX_ELEMENTS
|
787 |
|
|
#error "CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS too high - enlarge CGEN_MAX_SYNTAX_ELEMENTS"
|
788 |
|
|
#endif
|
789 |
|
|
#endif
|
790 |
|
|
|
791 |
|
|
typedef unsigned short CGEN_SYNTAX_CHAR_TYPE;
|
792 |
|
|
|
793 |
|
|
typedef struct
|
794 |
|
|
{
|
795 |
|
|
CGEN_SYNTAX_CHAR_TYPE syntax[CGEN_MAX_SYNTAX_ELEMENTS];
|
796 |
|
|
} CGEN_SYNTAX;
|
797 |
|
|
|
798 |
|
|
#define CGEN_SYNTAX_STRING(syn) (syn->syntax)
|
799 |
|
|
#define CGEN_SYNTAX_CHAR_P(c) ((c) < 128)
|
800 |
|
|
#define CGEN_SYNTAX_CHAR(c) ((unsigned char)c)
|
801 |
|
|
#define CGEN_SYNTAX_FIELD(c) ((c) - 128)
|
802 |
|
|
#define CGEN_SYNTAX_MAKE_FIELD(c) ((c) + 128)
|
803 |
|
|
|
804 |
|
|
/* ??? I can't currently think of any case where the mnemonic doesn't come
|
805 |
|
|
first [and if one ever doesn't building the hash tables will be tricky].
|
806 |
|
|
However, we treat mnemonics as just another operand of the instruction.
|
807 |
|
|
A value of 1 means "this is where the mnemonic appears". 1 isn't
|
808 |
|
|
special other than it's a non-printable ASCII char. */
|
809 |
|
|
|
810 |
|
|
#define CGEN_SYNTAX_MNEMONIC 1
|
811 |
|
|
#define CGEN_SYNTAX_MNEMONIC_P(ch) ((ch) == CGEN_SYNTAX_MNEMONIC)
|
812 |
|
|
|
813 |
|
|
/* Instruction fields.
|
814 |
|
|
|
815 |
|
|
??? We currently don't allow adding fields at run-time.
|
816 |
|
|
Easy to fix when needed. */
|
817 |
|
|
|
818 |
|
|
typedef struct cgen_ifld {
|
819 |
|
|
/* Enum of ifield. */
|
820 |
|
|
int num;
|
821 |
|
|
#define CGEN_IFLD_NUM(f) ((f)->num)
|
822 |
|
|
|
823 |
|
|
/* Name of the field, distinguishes it from all other fields. */
|
824 |
|
|
const char *name;
|
825 |
|
|
#define CGEN_IFLD_NAME(f) ((f)->name)
|
826 |
|
|
|
827 |
|
|
/* Default offset, in bits, from the start of the insn to the word
|
828 |
|
|
containing the field. */
|
829 |
|
|
int word_offset;
|
830 |
|
|
#define CGEN_IFLD_WORD_OFFSET(f) ((f)->word_offset)
|
831 |
|
|
|
832 |
|
|
/* Default length of the word containing the field. */
|
833 |
|
|
int word_size;
|
834 |
|
|
#define CGEN_IFLD_WORD_SIZE(f) ((f)->word_size)
|
835 |
|
|
|
836 |
|
|
/* Default starting bit number.
|
837 |
|
|
Whether lsb=0 or msb=0 is determined by CGEN_INSN_LSB0_P. */
|
838 |
|
|
int start;
|
839 |
|
|
#define CGEN_IFLD_START(f) ((f)->start)
|
840 |
|
|
|
841 |
|
|
/* Length of the field, in bits. */
|
842 |
|
|
int length;
|
843 |
|
|
#define CGEN_IFLD_LENGTH(f) ((f)->length)
|
844 |
|
|
|
845 |
|
|
#ifndef CGEN_IFLD_NBOOL_ATTRS
|
846 |
|
|
#define CGEN_IFLD_NBOOL_ATTRS 1
|
847 |
|
|
#endif
|
848 |
|
|
CGEN_ATTR_TYPE (CGEN_IFLD_NBOOL_ATTRS) attrs;
|
849 |
|
|
#define CGEN_IFLD_ATTRS(f) (&(f)->attrs)
|
850 |
|
|
} CGEN_IFLD;
|
851 |
|
|
|
852 |
|
|
/* Return value of attribute ATTR in IFLD. */
|
853 |
|
|
#define CGEN_IFLD_ATTR_VALUE(ifld, attr) \
|
854 |
|
|
CGEN_ATTR_VALUE ((ifld), CGEN_IFLD_ATTRS (ifld), (attr))
|
855 |
|
|
|
856 |
|
|
/* Instruction data. */
|
857 |
|
|
|
858 |
|
|
/* Instruction formats.
|
859 |
|
|
|
860 |
|
|
Instructions are grouped by format. Associated with an instruction is its
|
861 |
|
|
format. Each insn's opcode table entry contains a format table entry.
|
862 |
|
|
??? There is usually very few formats compared with the number of insns,
|
863 |
|
|
so one can reduce the size of the opcode table by recording the format table
|
864 |
|
|
as a separate entity. Given that we currently don't, format table entries
|
865 |
|
|
are also distinguished by their operands. This increases the size of the
|
866 |
|
|
table, but reduces the number of tables. It's all minutiae anyway so it
|
867 |
|
|
doesn't really matter [at this point in time].
|
868 |
|
|
|
869 |
|
|
??? Support for variable length ISA's is wip. */
|
870 |
|
|
|
871 |
|
|
/* Accompanying each iformat description is a list of its fields. */
|
872 |
|
|
|
873 |
|
|
typedef struct {
|
874 |
|
|
const CGEN_IFLD *ifld;
|
875 |
|
|
#define CGEN_IFMT_IFLD_IFLD(ii) ((ii)->ifld)
|
876 |
|
|
} CGEN_IFMT_IFLD;
|
877 |
|
|
|
878 |
|
|
/* This should be at least as large as necessary for any target. */
|
879 |
|
|
#define CGEN_MAX_IFMT_OPERANDS 16
|
880 |
|
|
|
881 |
|
|
/* A target may know its own precise maximum. Assert that it falls below
|
882 |
|
|
the above limit. */
|
883 |
|
|
#ifdef CGEN_ACTUAL_MAX_IFMT_OPERANDS
|
884 |
|
|
#if CGEN_ACTUAL_MAX_IFMT_OPERANDS > CGEN_MAX_IFMT_OPERANDS
|
885 |
|
|
#error "CGEN_ACTUAL_MAX_IFMT_OPERANDS too high - enlarge CGEN_MAX_IFMT_OPERANDS"
|
886 |
|
|
#endif
|
887 |
|
|
#endif
|
888 |
|
|
|
889 |
|
|
|
890 |
|
|
typedef struct
|
891 |
|
|
{
|
892 |
|
|
/* Length that MASK and VALUE have been calculated to
|
893 |
|
|
[VALUE is recorded elsewhere].
|
894 |
|
|
Normally it is base_insn_bitsize. On [V]LIW architectures where the base
|
895 |
|
|
insn size may be larger than the size of an insn, this field is less than
|
896 |
|
|
base_insn_bitsize. */
|
897 |
|
|
unsigned char mask_length;
|
898 |
|
|
#define CGEN_IFMT_MASK_LENGTH(ifmt) ((ifmt)->mask_length)
|
899 |
|
|
|
900 |
|
|
/* Total length of instruction, in bits. */
|
901 |
|
|
unsigned char length;
|
902 |
|
|
#define CGEN_IFMT_LENGTH(ifmt) ((ifmt)->length)
|
903 |
|
|
|
904 |
|
|
/* Mask to apply to the first MASK_LENGTH bits.
|
905 |
|
|
Each insn's value is stored with the insn.
|
906 |
|
|
The first step in recognizing an insn for disassembly is
|
907 |
|
|
(opcode & mask) == value. */
|
908 |
|
|
CGEN_INSN_INT mask;
|
909 |
|
|
#define CGEN_IFMT_MASK(ifmt) ((ifmt)->mask)
|
910 |
|
|
|
911 |
|
|
/* Instruction fields.
|
912 |
|
|
+1 for trailing NULL. */
|
913 |
|
|
CGEN_IFMT_IFLD iflds[CGEN_MAX_IFMT_OPERANDS + 1];
|
914 |
|
|
#define CGEN_IFMT_IFLDS(ifmt) ((ifmt)->iflds)
|
915 |
|
|
} CGEN_IFMT;
|
916 |
|
|
|
917 |
|
|
/* Instruction values. */
|
918 |
|
|
|
919 |
|
|
typedef struct
|
920 |
|
|
{
|
921 |
|
|
/* The opcode portion of the base insn. */
|
922 |
|
|
CGEN_INSN_INT base_value;
|
923 |
|
|
|
924 |
|
|
#ifdef CGEN_MAX_EXTRA_OPCODE_OPERANDS
|
925 |
|
|
/* Extra opcode values beyond base_value. */
|
926 |
|
|
unsigned long ifield_values[CGEN_MAX_EXTRA_OPCODE_OPERANDS];
|
927 |
|
|
#endif
|
928 |
|
|
} CGEN_IVALUE;
|
929 |
|
|
|
930 |
|
|
/* Instruction opcode table.
|
931 |
|
|
This contains the syntax and format data of an instruction. */
|
932 |
|
|
|
933 |
|
|
/* ??? Some ports already have an opcode table yet still need to use the rest
|
934 |
|
|
of what cgen_insn has. Plus keeping the opcode data with the operand
|
935 |
|
|
instance data can create a pretty big file. So we keep them separately.
|
936 |
|
|
Not sure this is a good idea in the long run. */
|
937 |
|
|
|
938 |
|
|
typedef struct
|
939 |
|
|
{
|
940 |
|
|
/* Indices into parse/insert/extract/print handler tables. */
|
941 |
|
|
struct cgen_opcode_handler handlers;
|
942 |
|
|
#define CGEN_OPCODE_HANDLERS(opc) (& (opc)->handlers)
|
943 |
|
|
|
944 |
|
|
/* Syntax string. */
|
945 |
|
|
CGEN_SYNTAX syntax;
|
946 |
|
|
#define CGEN_OPCODE_SYNTAX(opc) (& (opc)->syntax)
|
947 |
|
|
|
948 |
|
|
/* Format entry. */
|
949 |
|
|
const CGEN_IFMT *format;
|
950 |
|
|
#define CGEN_OPCODE_FORMAT(opc) ((opc)->format)
|
951 |
|
|
#define CGEN_OPCODE_MASK_BITSIZE(opc) CGEN_IFMT_MASK_LENGTH (CGEN_OPCODE_FORMAT (opc))
|
952 |
|
|
#define CGEN_OPCODE_BITSIZE(opc) CGEN_IFMT_LENGTH (CGEN_OPCODE_FORMAT (opc))
|
953 |
|
|
#define CGEN_OPCODE_IFLDS(opc) CGEN_IFMT_IFLDS (CGEN_OPCODE_FORMAT (opc))
|
954 |
|
|
|
955 |
|
|
/* Instruction opcode value. */
|
956 |
|
|
CGEN_IVALUE value;
|
957 |
|
|
#define CGEN_OPCODE_VALUE(opc) (& (opc)->value)
|
958 |
|
|
#define CGEN_OPCODE_BASE_VALUE(opc) (CGEN_OPCODE_VALUE (opc)->base_value)
|
959 |
|
|
#define CGEN_OPCODE_BASE_MASK(opc) CGEN_IFMT_MASK (CGEN_OPCODE_FORMAT (opc))
|
960 |
|
|
} CGEN_OPCODE;
|
961 |
|
|
|
962 |
|
|
/* Instruction attributes.
|
963 |
|
|
This is made a published type as applications can cache a pointer to
|
964 |
|
|
the attributes for speed. */
|
965 |
|
|
|
966 |
|
|
#ifndef CGEN_INSN_NBOOL_ATTRS
|
967 |
|
|
#define CGEN_INSN_NBOOL_ATTRS 1
|
968 |
|
|
#endif
|
969 |
|
|
typedef CGEN_ATTR_TYPE (CGEN_INSN_NBOOL_ATTRS) CGEN_INSN_ATTR_TYPE;
|
970 |
|
|
|
971 |
|
|
/* Enum of architecture independent attributes. */
|
972 |
|
|
|
973 |
|
|
#ifndef CGEN_ARCH
|
974 |
|
|
/* ??? Numbers here are recorded in two places. */
|
975 |
|
|
typedef enum cgen_insn_attr {
|
976 |
|
|
CGEN_INSN_ALIAS = 0
|
977 |
|
|
} CGEN_INSN_ATTR;
|
978 |
|
|
#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) ((attrs)->bool & (1 << CGEN_INSN_ALIAS))
|
979 |
|
|
#endif
|
980 |
|
|
|
981 |
|
|
/* This struct defines each entry in the instruction table. */
|
982 |
|
|
|
983 |
|
|
typedef struct
|
984 |
|
|
{
|
985 |
|
|
/* Each real instruction is enumerated. */
|
986 |
|
|
/* ??? This may go away in time. */
|
987 |
|
|
int num;
|
988 |
|
|
#define CGEN_INSN_NUM(insn) ((insn)->base->num)
|
989 |
|
|
|
990 |
|
|
/* Name of entry (that distinguishes it from all other entries). */
|
991 |
|
|
/* ??? If mnemonics have operands, try to print full mnemonic. */
|
992 |
|
|
const char *name;
|
993 |
|
|
#define CGEN_INSN_NAME(insn) ((insn)->base->name)
|
994 |
|
|
|
995 |
|
|
/* Mnemonic. This is used when parsing and printing the insn.
|
996 |
|
|
In the case of insns that have operands on the mnemonics, this is
|
997 |
|
|
only the constant part. E.g. for conditional execution of an `add' insn,
|
998 |
|
|
where the full mnemonic is addeq, addne, etc., and the condition is
|
999 |
|
|
treated as an operand, this is only "add". */
|
1000 |
|
|
const char *mnemonic;
|
1001 |
|
|
#define CGEN_INSN_MNEMONIC(insn) ((insn)->base->mnemonic)
|
1002 |
|
|
|
1003 |
|
|
/* Total length of instruction, in bits. */
|
1004 |
|
|
int bitsize;
|
1005 |
|
|
#define CGEN_INSN_BITSIZE(insn) ((insn)->base->bitsize)
|
1006 |
|
|
|
1007 |
|
|
#if 0 /* ??? Disabled for now as there is a problem with embedded newlines
|
1008 |
|
|
and the table is already pretty big. Should perhaps be moved
|
1009 |
|
|
to a file of its own. */
|
1010 |
|
|
/* Semantics, as RTL. */
|
1011 |
|
|
/* ??? Plain text or bytecodes? */
|
1012 |
|
|
/* ??? Note that the operand instance table could be computed at run-time
|
1013 |
|
|
if we parse this and cache the results. Something to eventually do. */
|
1014 |
|
|
const char *rtx;
|
1015 |
|
|
#define CGEN_INSN_RTX(insn) ((insn)->base->rtx)
|
1016 |
|
|
#endif
|
1017 |
|
|
|
1018 |
|
|
/* Attributes.
|
1019 |
|
|
This must appear last. It is a variable sized array in that one
|
1020 |
|
|
architecture may have 1 nonbool attribute and another may have more.
|
1021 |
|
|
Having this last means the non-architecture specific code needn't
|
1022 |
|
|
care. The goal is to eventually record attributes in their raw form,
|
1023 |
|
|
evaluate them at run-time, and cache the values, so this worry will go
|
1024 |
|
|
away anyway. */
|
1025 |
|
|
CGEN_INSN_ATTR_TYPE attrs;
|
1026 |
|
|
#define CGEN_INSN_ATTRS(insn) (&(insn)->base->attrs)
|
1027 |
|
|
/* Return value of attribute ATTR in INSN. */
|
1028 |
|
|
#define CGEN_INSN_ATTR_VALUE(insn, attr) \
|
1029 |
|
|
CGEN_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr))
|
1030 |
|
|
#define CGEN_INSN_BITSET_ATTR_VALUE(insn, attr) \
|
1031 |
|
|
CGEN_BITSET_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr))
|
1032 |
|
|
} CGEN_IBASE;
|
1033 |
|
|
|
1034 |
|
|
/* Return non-zero if INSN is the "invalid" insn marker. */
|
1035 |
|
|
|
1036 |
|
|
#define CGEN_INSN_INVALID_P(insn) (CGEN_INSN_MNEMONIC (insn) == 0)
|
1037 |
|
|
|
1038 |
|
|
/* Main struct contain instruction information.
|
1039 |
|
|
BASE is always present, the rest is present only if asked for. */
|
1040 |
|
|
|
1041 |
|
|
struct cgen_insn
|
1042 |
|
|
{
|
1043 |
|
|
/* ??? May be of use to put a type indicator here.
|
1044 |
|
|
Then this struct could different info for different classes of insns. */
|
1045 |
|
|
/* ??? A speedup can be had by moving `base' into this struct.
|
1046 |
|
|
Maybe later. */
|
1047 |
|
|
const CGEN_IBASE *base;
|
1048 |
|
|
const CGEN_OPCODE *opcode;
|
1049 |
|
|
const CGEN_OPINST *opinst;
|
1050 |
|
|
|
1051 |
|
|
/* Regex to disambiguate overloaded opcodes */
|
1052 |
|
|
void *rx;
|
1053 |
|
|
#define CGEN_INSN_RX(insn) ((insn)->rx)
|
1054 |
|
|
#define CGEN_MAX_RX_ELEMENTS (CGEN_MAX_SYNTAX_ELEMENTS * 5)
|
1055 |
|
|
};
|
1056 |
|
|
|
1057 |
|
|
/* Instruction lists.
|
1058 |
|
|
This is used for adding new entries and for creating the hash lists. */
|
1059 |
|
|
|
1060 |
|
|
typedef struct cgen_insn_list
|
1061 |
|
|
{
|
1062 |
|
|
struct cgen_insn_list *next;
|
1063 |
|
|
const CGEN_INSN *insn;
|
1064 |
|
|
} CGEN_INSN_LIST;
|
1065 |
|
|
|
1066 |
|
|
/* Table of instructions. */
|
1067 |
|
|
|
1068 |
|
|
typedef struct
|
1069 |
|
|
{
|
1070 |
|
|
const CGEN_INSN *init_entries;
|
1071 |
|
|
unsigned int entry_size; /* since the attribute member is variable sized */
|
1072 |
|
|
unsigned int num_init_entries;
|
1073 |
|
|
CGEN_INSN_LIST *new_entries;
|
1074 |
|
|
} CGEN_INSN_TABLE;
|
1075 |
|
|
|
1076 |
|
|
/* Return number of instructions. This includes any added at run-time. */
|
1077 |
|
|
|
1078 |
|
|
extern int cgen_insn_count (CGEN_CPU_DESC);
|
1079 |
|
|
extern int cgen_macro_insn_count (CGEN_CPU_DESC);
|
1080 |
|
|
|
1081 |
|
|
/* Macros to access the other insn elements not recorded in CGEN_IBASE. */
|
1082 |
|
|
|
1083 |
|
|
/* Fetch INSN's operand instance table. */
|
1084 |
|
|
/* ??? Doesn't handle insns added at runtime. */
|
1085 |
|
|
#define CGEN_INSN_OPERANDS(insn) ((insn)->opinst)
|
1086 |
|
|
|
1087 |
|
|
/* Return INSN's opcode table entry. */
|
1088 |
|
|
#define CGEN_INSN_OPCODE(insn) ((insn)->opcode)
|
1089 |
|
|
|
1090 |
|
|
/* Return INSN's handler data. */
|
1091 |
|
|
#define CGEN_INSN_HANDLERS(insn) CGEN_OPCODE_HANDLERS (CGEN_INSN_OPCODE (insn))
|
1092 |
|
|
|
1093 |
|
|
/* Return INSN's syntax. */
|
1094 |
|
|
#define CGEN_INSN_SYNTAX(insn) CGEN_OPCODE_SYNTAX (CGEN_INSN_OPCODE (insn))
|
1095 |
|
|
|
1096 |
|
|
/* Return size of base mask in bits. */
|
1097 |
|
|
#define CGEN_INSN_MASK_BITSIZE(insn) \
|
1098 |
|
|
CGEN_OPCODE_MASK_BITSIZE (CGEN_INSN_OPCODE (insn))
|
1099 |
|
|
|
1100 |
|
|
/* Return mask of base part of INSN. */
|
1101 |
|
|
#define CGEN_INSN_BASE_MASK(insn) \
|
1102 |
|
|
CGEN_OPCODE_BASE_MASK (CGEN_INSN_OPCODE (insn))
|
1103 |
|
|
|
1104 |
|
|
/* Return value of base part of INSN. */
|
1105 |
|
|
#define CGEN_INSN_BASE_VALUE(insn) \
|
1106 |
|
|
CGEN_OPCODE_BASE_VALUE (CGEN_INSN_OPCODE (insn))
|
1107 |
|
|
|
1108 |
|
|
/* Standard way to test whether INSN is supported by MACH.
|
1109 |
|
|
MACH is one of enum mach_attr.
|
1110 |
|
|
The "|1" is because the base mach is always selected. */
|
1111 |
|
|
#define CGEN_INSN_MACH_HAS_P(insn, mach) \
|
1112 |
|
|
((CGEN_INSN_ATTR_VALUE ((insn), CGEN_INSN_MACH) & ((1 << (mach)) | 1)) != 0)
|
1113 |
|
|
|
1114 |
|
|
/* Macro instructions.
|
1115 |
|
|
Macro insns aren't real insns, they map to one or more real insns.
|
1116 |
|
|
E.g. An architecture's "nop" insn may actually be an "mv r0,r0" or
|
1117 |
|
|
some such.
|
1118 |
|
|
|
1119 |
|
|
Macro insns can expand to nothing (e.g. a nop that is optimized away).
|
1120 |
|
|
This is useful in multi-insn macros that build a constant in a register.
|
1121 |
|
|
Of course this isn't the default behaviour and must be explicitly enabled.
|
1122 |
|
|
|
1123 |
|
|
Assembly of macro-insns is relatively straightforward. Disassembly isn't.
|
1124 |
|
|
However, disassembly of at least some kinds of macro insns is important
|
1125 |
|
|
in order that the disassembled code preserve the readability of the original
|
1126 |
|
|
insn. What is attempted here is to disassemble all "simple" macro-insns,
|
1127 |
|
|
where "simple" is currently defined to mean "expands to one real insn".
|
1128 |
|
|
|
1129 |
|
|
Simple macro-insns are handled specially. They are emitted as ALIAS's
|
1130 |
|
|
of real insns. This simplifies their handling since there's usually more
|
1131 |
|
|
of them than any other kind of macro-insn, and proper disassembly of them
|
1132 |
|
|
falls out for free. */
|
1133 |
|
|
|
1134 |
|
|
/* For each macro-insn there may be multiple expansion possibilities,
|
1135 |
|
|
depending on the arguments. This structure is accessed via the `data'
|
1136 |
|
|
member of CGEN_INSN. */
|
1137 |
|
|
|
1138 |
|
|
typedef struct cgen_minsn_expansion {
|
1139 |
|
|
/* Function to do the expansion.
|
1140 |
|
|
If the expansion fails (e.g. "no match") NULL is returned.
|
1141 |
|
|
Space for the expansion is obtained with malloc.
|
1142 |
|
|
It is up to the caller to free it. */
|
1143 |
|
|
const char * (* fn)
|
1144 |
|
|
(const struct cgen_minsn_expansion *,
|
1145 |
|
|
const char *, const char **, int *,
|
1146 |
|
|
CGEN_OPERAND **);
|
1147 |
|
|
#define CGEN_MIEXPN_FN(ex) ((ex)->fn)
|
1148 |
|
|
|
1149 |
|
|
/* Instruction(s) the macro expands to.
|
1150 |
|
|
The format of STR is defined by FN.
|
1151 |
|
|
It is typically the assembly code of the real insn, but it could also be
|
1152 |
|
|
the original Scheme expression or a tokenized form of it (with FN being
|
1153 |
|
|
an appropriate interpreter). */
|
1154 |
|
|
const char * str;
|
1155 |
|
|
#define CGEN_MIEXPN_STR(ex) ((ex)->str)
|
1156 |
|
|
} CGEN_MINSN_EXPANSION;
|
1157 |
|
|
|
1158 |
|
|
/* Normal expander.
|
1159 |
|
|
When supported, this function will convert the input string to another
|
1160 |
|
|
string and the parser will be invoked recursively. The output string
|
1161 |
|
|
may contain further macro invocations. */
|
1162 |
|
|
|
1163 |
|
|
extern const char * cgen_expand_macro_insn
|
1164 |
|
|
(CGEN_CPU_DESC, const struct cgen_minsn_expansion *,
|
1165 |
|
|
const char *, const char **, int *, CGEN_OPERAND **);
|
1166 |
|
|
|
1167 |
|
|
/* The assembler insn table is hashed based on some function of the mnemonic
|
1168 |
|
|
(the actually hashing done is up to the target, but we provide a few
|
1169 |
|
|
examples like the first letter or a function of the entire mnemonic). */
|
1170 |
|
|
|
1171 |
|
|
extern CGEN_INSN_LIST * cgen_asm_lookup_insn
|
1172 |
|
|
(CGEN_CPU_DESC, const char *);
|
1173 |
|
|
#define CGEN_ASM_LOOKUP_INSN(cd, string) cgen_asm_lookup_insn ((cd), (string))
|
1174 |
|
|
#define CGEN_ASM_NEXT_INSN(insn) ((insn)->next)
|
1175 |
|
|
|
1176 |
|
|
/* The disassembler insn table is hashed based on some function of machine
|
1177 |
|
|
instruction (the actually hashing done is up to the target). */
|
1178 |
|
|
|
1179 |
|
|
extern CGEN_INSN_LIST * cgen_dis_lookup_insn
|
1180 |
|
|
(CGEN_CPU_DESC, const char *, CGEN_INSN_INT);
|
1181 |
|
|
/* FIXME: delete these two */
|
1182 |
|
|
#define CGEN_DIS_LOOKUP_INSN(cd, buf, value) cgen_dis_lookup_insn ((cd), (buf), (value))
|
1183 |
|
|
#define CGEN_DIS_NEXT_INSN(insn) ((insn)->next)
|
1184 |
|
|
|
1185 |
|
|
/* The CPU description.
|
1186 |
|
|
A copy of this is created when the cpu table is "opened".
|
1187 |
|
|
All global state information is recorded here.
|
1188 |
|
|
Access macros are provided for "public" members. */
|
1189 |
|
|
|
1190 |
|
|
typedef struct cgen_cpu_desc
|
1191 |
|
|
{
|
1192 |
|
|
/* Bitmap of selected machine(s) (a la BFD machine number). */
|
1193 |
|
|
int machs;
|
1194 |
|
|
|
1195 |
|
|
/* Bitmap of selected isa(s). */
|
1196 |
|
|
CGEN_BITSET *isas;
|
1197 |
|
|
#define CGEN_CPU_ISAS(cd) ((cd)->isas)
|
1198 |
|
|
|
1199 |
|
|
/* Current endian. */
|
1200 |
|
|
enum cgen_endian endian;
|
1201 |
|
|
#define CGEN_CPU_ENDIAN(cd) ((cd)->endian)
|
1202 |
|
|
|
1203 |
|
|
/* Current insn endian. */
|
1204 |
|
|
enum cgen_endian insn_endian;
|
1205 |
|
|
#define CGEN_CPU_INSN_ENDIAN(cd) ((cd)->insn_endian)
|
1206 |
|
|
|
1207 |
|
|
/* Word size (in bits). */
|
1208 |
|
|
/* ??? Or maybe maximum word size - might we ever need to allow a cpu table
|
1209 |
|
|
to be opened for both sparc32/sparc64?
|
1210 |
|
|
??? Another alternative is to create a table of selected machs and
|
1211 |
|
|
lazily fetch the data from there. */
|
1212 |
|
|
unsigned int word_bitsize;
|
1213 |
|
|
|
1214 |
|
|
/* Instruction chunk size (in bits), for purposes of endianness
|
1215 |
|
|
conversion. */
|
1216 |
|
|
unsigned int insn_chunk_bitsize;
|
1217 |
|
|
|
1218 |
|
|
/* Indicator if sizes are unknown.
|
1219 |
|
|
This is used by default_insn_bitsize,base_insn_bitsize if there is a
|
1220 |
|
|
difference between the selected isa's. */
|
1221 |
|
|
#define CGEN_SIZE_UNKNOWN 65535
|
1222 |
|
|
|
1223 |
|
|
/* Default instruction size (in bits).
|
1224 |
|
|
This is used by the assembler when it encounters an unknown insn. */
|
1225 |
|
|
unsigned int default_insn_bitsize;
|
1226 |
|
|
|
1227 |
|
|
/* Base instruction size (in bits).
|
1228 |
|
|
For non-LIW cpus this is generally the length of the smallest insn.
|
1229 |
|
|
For LIW cpus its wip (work-in-progress). For the m32r its 32. */
|
1230 |
|
|
unsigned int base_insn_bitsize;
|
1231 |
|
|
|
1232 |
|
|
/* Minimum/maximum instruction size (in bits). */
|
1233 |
|
|
unsigned int min_insn_bitsize;
|
1234 |
|
|
unsigned int max_insn_bitsize;
|
1235 |
|
|
|
1236 |
|
|
/* Instruction set variants. */
|
1237 |
|
|
const CGEN_ISA *isa_table;
|
1238 |
|
|
|
1239 |
|
|
/* Machine variants. */
|
1240 |
|
|
const CGEN_MACH *mach_table;
|
1241 |
|
|
|
1242 |
|
|
/* Hardware elements. */
|
1243 |
|
|
CGEN_HW_TABLE hw_table;
|
1244 |
|
|
|
1245 |
|
|
/* Instruction fields. */
|
1246 |
|
|
const CGEN_IFLD *ifld_table;
|
1247 |
|
|
|
1248 |
|
|
/* Operands. */
|
1249 |
|
|
CGEN_OPERAND_TABLE operand_table;
|
1250 |
|
|
|
1251 |
|
|
/* Main instruction table. */
|
1252 |
|
|
CGEN_INSN_TABLE insn_table;
|
1253 |
|
|
#define CGEN_CPU_INSN_TABLE(cd) (& (cd)->insn_table)
|
1254 |
|
|
|
1255 |
|
|
/* Macro instructions are defined separately and are combined with real
|
1256 |
|
|
insns during hash table computation. */
|
1257 |
|
|
CGEN_INSN_TABLE macro_insn_table;
|
1258 |
|
|
|
1259 |
|
|
/* Copy of CGEN_INT_INSN_P. */
|
1260 |
|
|
int int_insn_p;
|
1261 |
|
|
|
1262 |
|
|
/* Called to rebuild the tables after something has changed. */
|
1263 |
|
|
void (*rebuild_tables) (CGEN_CPU_DESC);
|
1264 |
|
|
|
1265 |
|
|
/* Operand parser callback. */
|
1266 |
|
|
cgen_parse_operand_fn * parse_operand_fn;
|
1267 |
|
|
|
1268 |
|
|
/* Parse/insert/extract/print cover fns for operands. */
|
1269 |
|
|
const char * (*parse_operand)
|
1270 |
|
|
(CGEN_CPU_DESC, int opindex_, const char **, CGEN_FIELDS *fields_);
|
1271 |
|
|
#ifdef __BFD_H_SEEN__
|
1272 |
|
|
const char * (*insert_operand)
|
1273 |
|
|
(CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_,
|
1274 |
|
|
CGEN_INSN_BYTES_PTR, bfd_vma pc_);
|
1275 |
|
|
int (*extract_operand)
|
1276 |
|
|
(CGEN_CPU_DESC, int opindex_, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
|
1277 |
|
|
CGEN_FIELDS *fields_, bfd_vma pc_);
|
1278 |
|
|
void (*print_operand)
|
1279 |
|
|
(CGEN_CPU_DESC, int opindex_, void * info_, CGEN_FIELDS * fields_,
|
1280 |
|
|
void const *attrs_, bfd_vma pc_, int length_);
|
1281 |
|
|
#else
|
1282 |
|
|
const char * (*insert_operand) ();
|
1283 |
|
|
int (*extract_operand) ();
|
1284 |
|
|
void (*print_operand) ();
|
1285 |
|
|
#endif
|
1286 |
|
|
#define CGEN_CPU_PARSE_OPERAND(cd) ((cd)->parse_operand)
|
1287 |
|
|
#define CGEN_CPU_INSERT_OPERAND(cd) ((cd)->insert_operand)
|
1288 |
|
|
#define CGEN_CPU_EXTRACT_OPERAND(cd) ((cd)->extract_operand)
|
1289 |
|
|
#define CGEN_CPU_PRINT_OPERAND(cd) ((cd)->print_operand)
|
1290 |
|
|
|
1291 |
|
|
/* Size of CGEN_FIELDS struct. */
|
1292 |
|
|
unsigned int sizeof_fields;
|
1293 |
|
|
#define CGEN_CPU_SIZEOF_FIELDS(cd) ((cd)->sizeof_fields)
|
1294 |
|
|
|
1295 |
|
|
/* Set the bitsize field. */
|
1296 |
|
|
void (*set_fields_bitsize) (CGEN_FIELDS *fields_, int size_);
|
1297 |
|
|
#define CGEN_CPU_SET_FIELDS_BITSIZE(cd) ((cd)->set_fields_bitsize)
|
1298 |
|
|
|
1299 |
|
|
/* CGEN_FIELDS accessors. */
|
1300 |
|
|
int (*get_int_operand)
|
1301 |
|
|
(CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_);
|
1302 |
|
|
void (*set_int_operand)
|
1303 |
|
|
(CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, int value_);
|
1304 |
|
|
#ifdef __BFD_H_SEEN__
|
1305 |
|
|
bfd_vma (*get_vma_operand)
|
1306 |
|
|
(CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_);
|
1307 |
|
|
void (*set_vma_operand)
|
1308 |
|
|
(CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, bfd_vma value_);
|
1309 |
|
|
#else
|
1310 |
|
|
long (*get_vma_operand) ();
|
1311 |
|
|
void (*set_vma_operand) ();
|
1312 |
|
|
#endif
|
1313 |
|
|
#define CGEN_CPU_GET_INT_OPERAND(cd) ((cd)->get_int_operand)
|
1314 |
|
|
#define CGEN_CPU_SET_INT_OPERAND(cd) ((cd)->set_int_operand)
|
1315 |
|
|
#define CGEN_CPU_GET_VMA_OPERAND(cd) ((cd)->get_vma_operand)
|
1316 |
|
|
#define CGEN_CPU_SET_VMA_OPERAND(cd) ((cd)->set_vma_operand)
|
1317 |
|
|
|
1318 |
|
|
/* Instruction parse/insert/extract/print handlers. */
|
1319 |
|
|
/* FIXME: make these types uppercase. */
|
1320 |
|
|
cgen_parse_fn * const *parse_handlers;
|
1321 |
|
|
cgen_insert_fn * const *insert_handlers;
|
1322 |
|
|
cgen_extract_fn * const *extract_handlers;
|
1323 |
|
|
cgen_print_fn * const *print_handlers;
|
1324 |
|
|
#define CGEN_PARSE_FN(cd, insn) (cd->parse_handlers[(insn)->opcode->handlers.parse])
|
1325 |
|
|
#define CGEN_INSERT_FN(cd, insn) (cd->insert_handlers[(insn)->opcode->handlers.insert])
|
1326 |
|
|
#define CGEN_EXTRACT_FN(cd, insn) (cd->extract_handlers[(insn)->opcode->handlers.extract])
|
1327 |
|
|
#define CGEN_PRINT_FN(cd, insn) (cd->print_handlers[(insn)->opcode->handlers.print])
|
1328 |
|
|
|
1329 |
|
|
/* Return non-zero if insn should be added to hash table. */
|
1330 |
|
|
int (* asm_hash_p) (const CGEN_INSN *);
|
1331 |
|
|
|
1332 |
|
|
/* Assembler hash function. */
|
1333 |
|
|
unsigned int (* asm_hash) (const char *);
|
1334 |
|
|
|
1335 |
|
|
/* Number of entries in assembler hash table. */
|
1336 |
|
|
unsigned int asm_hash_size;
|
1337 |
|
|
|
1338 |
|
|
/* Return non-zero if insn should be added to hash table. */
|
1339 |
|
|
int (* dis_hash_p) (const CGEN_INSN *);
|
1340 |
|
|
|
1341 |
|
|
/* Disassembler hash function. */
|
1342 |
|
|
unsigned int (* dis_hash) (const char *, CGEN_INSN_INT);
|
1343 |
|
|
|
1344 |
|
|
/* Number of entries in disassembler hash table. */
|
1345 |
|
|
unsigned int dis_hash_size;
|
1346 |
|
|
|
1347 |
|
|
/* Assembler instruction hash table. */
|
1348 |
|
|
CGEN_INSN_LIST **asm_hash_table;
|
1349 |
|
|
CGEN_INSN_LIST *asm_hash_table_entries;
|
1350 |
|
|
|
1351 |
|
|
/* Disassembler instruction hash table. */
|
1352 |
|
|
CGEN_INSN_LIST **dis_hash_table;
|
1353 |
|
|
CGEN_INSN_LIST *dis_hash_table_entries;
|
1354 |
|
|
|
1355 |
|
|
/* This field could be turned into a bitfield if room for other flags is needed. */
|
1356 |
|
|
unsigned int signed_overflow_ok_p;
|
1357 |
|
|
|
1358 |
|
|
} CGEN_CPU_TABLE;
|
1359 |
|
|
|
1360 |
|
|
/* wip */
|
1361 |
|
|
#ifndef CGEN_WORD_ENDIAN
|
1362 |
|
|
#define CGEN_WORD_ENDIAN(cd) CGEN_CPU_ENDIAN (cd)
|
1363 |
|
|
#endif
|
1364 |
|
|
#ifndef CGEN_INSN_WORD_ENDIAN
|
1365 |
|
|
#define CGEN_INSN_WORD_ENDIAN(cd) CGEN_CPU_INSN_ENDIAN (cd)
|
1366 |
|
|
#endif
|
1367 |
|
|
|
1368 |
|
|
/* Prototypes of major functions. */
|
1369 |
|
|
/* FIXME: Move more CGEN_SYM-defined functions into CGEN_CPU_DESC.
|
1370 |
|
|
Not the init fns though, as that would drag in things that mightn't be
|
1371 |
|
|
used and might not even exist. */
|
1372 |
|
|
|
1373 |
|
|
/* Argument types to cpu_open. */
|
1374 |
|
|
|
1375 |
|
|
enum cgen_cpu_open_arg {
|
1376 |
|
|
CGEN_CPU_OPEN_END,
|
1377 |
|
|
/* Select instruction set(s), arg is bitmap or 0 meaning "unspecified". */
|
1378 |
|
|
CGEN_CPU_OPEN_ISAS,
|
1379 |
|
|
/* Select machine(s), arg is bitmap or 0 meaning "unspecified". */
|
1380 |
|
|
CGEN_CPU_OPEN_MACHS,
|
1381 |
|
|
/* Select machine, arg is mach's bfd name.
|
1382 |
|
|
Multiple machines can be specified by repeated use. */
|
1383 |
|
|
CGEN_CPU_OPEN_BFDMACH,
|
1384 |
|
|
/* Select endian, arg is CGEN_ENDIAN_*. */
|
1385 |
|
|
CGEN_CPU_OPEN_ENDIAN
|
1386 |
|
|
};
|
1387 |
|
|
|
1388 |
|
|
/* Open a cpu descriptor table for use.
|
1389 |
|
|
??? We only support ISO C stdargs here, not K&R.
|
1390 |
|
|
Laziness, plus experiment to see if anything requires K&R - eventually
|
1391 |
|
|
K&R will no longer be supported - e.g. GDB is currently trying this. */
|
1392 |
|
|
|
1393 |
|
|
extern CGEN_CPU_DESC CGEN_SYM (cpu_open) (enum cgen_cpu_open_arg, ...);
|
1394 |
|
|
|
1395 |
|
|
/* Cover fn to handle simple case. */
|
1396 |
|
|
|
1397 |
|
|
extern CGEN_CPU_DESC CGEN_SYM (cpu_open_1)
|
1398 |
|
|
(const char *mach_name_, enum cgen_endian endian_);
|
1399 |
|
|
|
1400 |
|
|
/* Close it. */
|
1401 |
|
|
|
1402 |
|
|
extern void CGEN_SYM (cpu_close) (CGEN_CPU_DESC);
|
1403 |
|
|
|
1404 |
|
|
/* Initialize the opcode table for use.
|
1405 |
|
|
Called by init_asm/init_dis. */
|
1406 |
|
|
|
1407 |
|
|
extern void CGEN_SYM (init_opcode_table) (CGEN_CPU_DESC cd_);
|
1408 |
|
|
|
1409 |
|
|
/* build the insn selection regex.
|
1410 |
|
|
called by init_opcode_table */
|
1411 |
|
|
|
1412 |
|
|
extern char * CGEN_SYM(build_insn_regex) (CGEN_INSN *insn_);
|
1413 |
|
|
|
1414 |
|
|
/* Initialize the ibld table for use.
|
1415 |
|
|
Called by init_asm/init_dis. */
|
1416 |
|
|
|
1417 |
|
|
extern void CGEN_SYM (init_ibld_table) (CGEN_CPU_DESC cd_);
|
1418 |
|
|
|
1419 |
|
|
/* Initialize an cpu table for assembler or disassembler use.
|
1420 |
|
|
These must be called immediately after cpu_open. */
|
1421 |
|
|
|
1422 |
|
|
extern void CGEN_SYM (init_asm) (CGEN_CPU_DESC);
|
1423 |
|
|
extern void CGEN_SYM (init_dis) (CGEN_CPU_DESC);
|
1424 |
|
|
|
1425 |
|
|
/* Initialize the operand instance table for use. */
|
1426 |
|
|
|
1427 |
|
|
extern void CGEN_SYM (init_opinst_table) (CGEN_CPU_DESC cd_);
|
1428 |
|
|
|
1429 |
|
|
/* Assemble an instruction. */
|
1430 |
|
|
|
1431 |
|
|
extern const CGEN_INSN * CGEN_SYM (assemble_insn)
|
1432 |
|
|
(CGEN_CPU_DESC, const char *, CGEN_FIELDS *,
|
1433 |
|
|
CGEN_INSN_BYTES_PTR, char **);
|
1434 |
|
|
|
1435 |
|
|
extern const CGEN_KEYWORD CGEN_SYM (operand_mach);
|
1436 |
|
|
extern int CGEN_SYM (get_mach) (const char *);
|
1437 |
|
|
|
1438 |
|
|
/* Operand index computation. */
|
1439 |
|
|
extern const CGEN_INSN * cgen_lookup_insn
|
1440 |
|
|
(CGEN_CPU_DESC, const CGEN_INSN * insn_,
|
1441 |
|
|
CGEN_INSN_INT int_value_, unsigned char *bytes_value_,
|
1442 |
|
|
int length_, CGEN_FIELDS *fields_, int alias_p_);
|
1443 |
|
|
extern void cgen_get_insn_operands
|
1444 |
|
|
(CGEN_CPU_DESC, const CGEN_INSN * insn_,
|
1445 |
|
|
const CGEN_FIELDS *fields_, int *indices_);
|
1446 |
|
|
extern const CGEN_INSN * cgen_lookup_get_insn_operands
|
1447 |
|
|
(CGEN_CPU_DESC, const CGEN_INSN *insn_,
|
1448 |
|
|
CGEN_INSN_INT int_value_, unsigned char *bytes_value_,
|
1449 |
|
|
int length_, int *indices_, CGEN_FIELDS *fields_);
|
1450 |
|
|
|
1451 |
|
|
/* Cover fns to bfd_get/set. */
|
1452 |
|
|
|
1453 |
|
|
extern CGEN_INSN_INT cgen_get_insn_value
|
1454 |
|
|
(CGEN_CPU_DESC, unsigned char *, int);
|
1455 |
|
|
extern void cgen_put_insn_value
|
1456 |
|
|
(CGEN_CPU_DESC, unsigned char *, int, CGEN_INSN_INT);
|
1457 |
|
|
|
1458 |
|
|
/* Read in a cpu description file.
|
1459 |
|
|
??? For future concerns, including adding instructions to the assembler/
|
1460 |
|
|
disassembler at run-time. */
|
1461 |
|
|
|
1462 |
|
|
extern const char * cgen_read_cpu_file (CGEN_CPU_DESC, const char * filename_);
|
1463 |
|
|
|
1464 |
|
|
/* Allow signed overflow of instruction fields. */
|
1465 |
|
|
extern void cgen_set_signed_overflow_ok (CGEN_CPU_DESC);
|
1466 |
|
|
|
1467 |
|
|
/* Generate an error message if a signed field in an instruction overflows. */
|
1468 |
|
|
extern void cgen_clear_signed_overflow_ok (CGEN_CPU_DESC);
|
1469 |
|
|
|
1470 |
|
|
/* Will an error message be generated if a signed field in an instruction overflows ? */
|
1471 |
|
|
extern unsigned int cgen_signed_overflow_ok_p (CGEN_CPU_DESC);
|
1472 |
|
|
|
1473 |
|
|
#endif /* CGEN_H */
|