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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [include/] [opcode/] [ppc.h] - Blame information for rev 174

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1 24 jeremybenn
/* ppc.h -- Header file for PowerPC opcode table
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   Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
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   2007 Free Software Foundation, Inc.
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   Written by Ian Lance Taylor, Cygnus Support
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This file is part of GDB, GAS, and the GNU binutils.
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GDB, GAS, and the GNU binutils are free software; you can redistribute
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them and/or modify them under the terms of the GNU General Public
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License as published by the Free Software Foundation; either version
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1, or (at your option) any later version.
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GDB, GAS, and the GNU binutils are distributed in the hope that they
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will be useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
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the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING.  If not, write to the Free
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Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
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#ifndef PPC_H
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#define PPC_H
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/* The opcode table is an array of struct powerpc_opcode.  */
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struct powerpc_opcode
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{
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  /* The opcode name.  */
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  const char *name;
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  /* The opcode itself.  Those bits which will be filled in with
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     operands are zeroes.  */
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  unsigned long opcode;
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  /* The opcode mask.  This is used by the disassembler.  This is a
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     mask containing ones indicating those bits which must match the
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     opcode field, and zeroes indicating those bits which need not
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     match (and are presumably filled in by operands).  */
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  unsigned long mask;
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  /* One bit flags for the opcode.  These are used to indicate which
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     specific processors support the instructions.  The defined values
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     are listed below.  */
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  unsigned long flags;
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  /* An array of operand codes.  Each code is an index into the
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     operand table.  They appear in the order which the operands must
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     appear in assembly code, and are terminated by a zero.  */
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  unsigned char operands[8];
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};
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/* The table itself is sorted by major opcode number, and is otherwise
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   in the order in which the disassembler should consider
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   instructions.  */
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extern const struct powerpc_opcode powerpc_opcodes[];
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extern const int powerpc_num_opcodes;
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/* Values defined for the flags field of a struct powerpc_opcode.  */
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/* Opcode is defined for the PowerPC architecture.  */
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#define PPC_OPCODE_PPC                   1
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/* Opcode is defined for the POWER (RS/6000) architecture.  */
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#define PPC_OPCODE_POWER                 2
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/* Opcode is defined for the POWER2 (Rios 2) architecture.  */
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#define PPC_OPCODE_POWER2                4
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/* Opcode is only defined on 32 bit architectures.  */
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#define PPC_OPCODE_32                    8
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/* Opcode is only defined on 64 bit architectures.  */
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#define PPC_OPCODE_64                 0x10
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/* Opcode is supported by the Motorola PowerPC 601 processor.  The 601
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   is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
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   but it also supports many additional POWER instructions.  */
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#define PPC_OPCODE_601                0x20
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/* Opcode is supported in both the Power and PowerPC architectures
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   (ie, compiler's -mcpu=common or assembler's -mcom).  */
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#define PPC_OPCODE_COMMON             0x40
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/* Opcode is supported for any Power or PowerPC platform (this is
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   for the assembler's -many option, and it eliminates duplicates).  */
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#define PPC_OPCODE_ANY                0x80
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/* Opcode is supported as part of the 64-bit bridge.  */
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#define PPC_OPCODE_64_BRIDGE         0x100
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/* Opcode is supported by Altivec Vector Unit */
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#define PPC_OPCODE_ALTIVEC           0x200
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/* Opcode is supported by PowerPC 403 processor.  */
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#define PPC_OPCODE_403               0x400
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/* Opcode is supported by PowerPC BookE processor.  */
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#define PPC_OPCODE_BOOKE             0x800
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/* Opcode is only supported by 64-bit PowerPC BookE processor.  */
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#define PPC_OPCODE_BOOKE64          0x1000
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/* Opcode is supported by PowerPC 440 processor.  */
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#define PPC_OPCODE_440              0x2000
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/* Opcode is only supported by Power4 architecture.  */
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#define PPC_OPCODE_POWER4           0x4000
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/* Opcode isn't supported by Power4 architecture.  */
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#define PPC_OPCODE_NOPOWER4         0x8000
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/* Opcode is only supported by POWERPC Classic architecture.  */
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#define PPC_OPCODE_CLASSIC         0x10000
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/* Opcode is only supported by e500x2 Core.  */
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#define PPC_OPCODE_SPE             0x20000
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/* Opcode is supported by e500x2 Integer select APU.  */
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#define PPC_OPCODE_ISEL            0x40000
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/* Opcode is an e500 SPE floating point instruction.  */
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#define PPC_OPCODE_EFS             0x80000
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/* Opcode is supported by branch locking APU.  */
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#define PPC_OPCODE_BRLOCK         0x100000
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/* Opcode is supported by performance monitor APU.  */
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#define PPC_OPCODE_PMR            0x200000
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/* Opcode is supported by cache locking APU.  */
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#define PPC_OPCODE_CACHELCK       0x400000
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134
/* Opcode is supported by machine check APU.  */
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#define PPC_OPCODE_RFMCI          0x800000
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/* Opcode is only supported by Power5 architecture.  */
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#define PPC_OPCODE_POWER5        0x1000000
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140
/* Opcode is supported by PowerPC e300 family.  */
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#define PPC_OPCODE_E300          0x2000000
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143
/* Opcode is only supported by Power6 architecture.  */
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#define PPC_OPCODE_POWER6        0x4000000
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/* Opcode is only supported by PowerPC Cell family.  */
147
#define PPC_OPCODE_CELL          0x8000000
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149
/* Opcode is supported by CPUs with paired singles support.  */
150
#define PPC_OPCODE_PPCPS         0x10000000
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152
/* A macro to extract the major opcode from an instruction.  */
153
#define PPC_OP(i) (((i) >> 26) & 0x3f)
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155
/* The operands table is an array of struct powerpc_operand.  */
156
 
157
struct powerpc_operand
158
{
159
  /* A bitmask of bits in the operand.  */
160
  unsigned int bitm;
161
 
162
  /* How far the operand is left shifted in the instruction.
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     -1 to indicate that BITM and SHIFT cannot be used to determine
164
     where the operand goes in the insn.  */
165
  int shift;
166
 
167
  /* Insertion function.  This is used by the assembler.  To insert an
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     operand value into an instruction, check this field.
169
 
170
     If it is NULL, execute
171
         i |= (op & o->bitm) << o->shift;
172
     (i is the instruction which we are filling in, o is a pointer to
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     this structure, and op is the operand value).
174
 
175
     If this field is not NULL, then simply call it with the
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     instruction and the operand value.  It will return the new value
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     of the instruction.  If the ERRMSG argument is not NULL, then if
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     the operand value is illegal, *ERRMSG will be set to a warning
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     string (the operand will be inserted in any case).  If the
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     operand value is legal, *ERRMSG will be unchanged (most operands
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     can accept any value).  */
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  unsigned long (*insert)
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    (unsigned long instruction, long op, int dialect, const char **errmsg);
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  /* Extraction function.  This is used by the disassembler.  To
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     extract this operand type from an instruction, check this field.
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     If it is NULL, compute
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         op = (i >> o->shift) & o->bitm;
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         if ((o->flags & PPC_OPERAND_SIGNED) != 0)
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           sign_extend (op);
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     (i is the instruction, o is a pointer to this structure, and op
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     is the result).
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     If this field is not NULL, then simply call it with the
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     instruction value.  It will return the value of the operand.  If
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     the INVALID argument is not NULL, *INVALID will be set to
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     non-zero if this operand type can not actually be extracted from
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     this operand (i.e., the instruction does not match).  If the
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     operand is valid, *INVALID will not be changed.  */
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  long (*extract) (unsigned long instruction, int dialect, int *invalid);
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  /* One bit syntax flags.  */
204
  unsigned long flags;
205
};
206
 
207
/* Elements in the table are retrieved by indexing with values from
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   the operands field of the powerpc_opcodes table.  */
209
 
210
extern const struct powerpc_operand powerpc_operands[];
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extern const unsigned int num_powerpc_operands;
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/* Values defined for the flags field of a struct powerpc_operand.  */
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/* This operand takes signed values.  */
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#define PPC_OPERAND_SIGNED (0x1)
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/* This operand takes signed values, but also accepts a full positive
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   range of values when running in 32 bit mode.  That is, if bits is
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   16, it takes any value from -0x8000 to 0xffff.  In 64 bit mode,
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   this flag is ignored.  */
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#define PPC_OPERAND_SIGNOPT (0x2)
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/* This operand does not actually exist in the assembler input.  This
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   is used to support extended mnemonics such as mr, for which two
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   operands fields are identical.  The assembler should call the
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   insert function with any op value.  The disassembler should call
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   the extract function, ignore the return value, and check the value
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   placed in the valid argument.  */
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#define PPC_OPERAND_FAKE (0x4)
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232
/* The next operand should be wrapped in parentheses rather than
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   separated from this one by a comma.  This is used for the load and
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   store instructions which want their operands to look like
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       reg,displacement(reg)
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   */
237
#define PPC_OPERAND_PARENS (0x8)
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239
/* This operand may use the symbolic names for the CR fields, which
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   are
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       lt  0    gt  1   eq  2   so  3   un  3
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       cr0 0    cr1 1   cr2 2   cr3 3
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       cr4 4    cr5 5   cr6 6   cr7 7
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   These may be combined arithmetically, as in cr2*4+gt.  These are
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   only supported on the PowerPC, not the POWER.  */
246
#define PPC_OPERAND_CR (0x10)
247
 
248
/* This operand names a register.  The disassembler uses this to print
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   register names with a leading 'r'.  */
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#define PPC_OPERAND_GPR (0x20)
251
 
252
/* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0.  */
253
#define PPC_OPERAND_GPR_0 (0x40)
254
 
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/* This operand names a floating point register.  The disassembler
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   prints these with a leading 'f'.  */
257
#define PPC_OPERAND_FPR (0x80)
258
 
259
/* This operand is a relative branch displacement.  The disassembler
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   prints these symbolically if possible.  */
261
#define PPC_OPERAND_RELATIVE (0x100)
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263
/* This operand is an absolute branch address.  The disassembler
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   prints these symbolically if possible.  */
265
#define PPC_OPERAND_ABSOLUTE (0x200)
266
 
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/* This operand is optional, and is zero if omitted.  This is used for
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   example, in the optional BF field in the comparison instructions.  The
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   assembler must count the number of operands remaining on the line,
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   and the number of operands remaining for the opcode, and decide
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   whether this operand is present or not.  The disassembler should
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   print this operand out only if it is not zero.  */
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#define PPC_OPERAND_OPTIONAL (0x400)
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275
/* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
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   is omitted, then for the next operand use this operand value plus
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   1, ignoring the next operand field for the opcode.  This wretched
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   hack is needed because the Power rotate instructions can take
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   either 4 or 5 operands.  The disassembler should print this operand
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   out regardless of the PPC_OPERAND_OPTIONAL field.  */
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#define PPC_OPERAND_NEXT (0x800)
282
 
283
/* This operand should be regarded as a negative number for the
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   purposes of overflow checking (i.e., the normal most negative
285
   number is disallowed and one more than the normal most positive
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   number is allowed).  This flag will only be set for a signed
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   operand.  */
288
#define PPC_OPERAND_NEGATIVE (0x1000)
289
 
290
/* This operand names a vector unit register.  The disassembler
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   prints these with a leading 'v'.  */
292
#define PPC_OPERAND_VR (0x2000)
293
 
294
/* This operand is for the DS field in a DS form instruction.  */
295
#define PPC_OPERAND_DS (0x4000)
296
 
297
/* This operand is for the DQ field in a DQ form instruction.  */
298
#define PPC_OPERAND_DQ (0x8000)
299
 
300
/* Valid range of operand is 0..n rather than 0..n-1.  */
301
#define PPC_OPERAND_PLUS1 (0x10000)
302
 
303
/* The POWER and PowerPC assemblers use a few macros.  We keep them
304
   with the operands table for simplicity.  The macro table is an
305
   array of struct powerpc_macro.  */
306
 
307
struct powerpc_macro
308
{
309
  /* The macro name.  */
310
  const char *name;
311
 
312
  /* The number of operands the macro takes.  */
313
  unsigned int operands;
314
 
315
  /* One bit flags for the opcode.  These are used to indicate which
316
     specific processors support the instructions.  The values are the
317
     same as those for the struct powerpc_opcode flags field.  */
318
  unsigned long flags;
319
 
320
  /* A format string to turn the macro into a normal instruction.
321
     Each %N in the string is replaced with operand number N (zero
322
     based).  */
323
  const char *format;
324
};
325
 
326
extern const struct powerpc_macro powerpc_macros[];
327
extern const int powerpc_num_macros;
328
 
329
#endif /* PPC_H */

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