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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [opcodes/] [bfin-dis.c] - Blame information for rev 203

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1 24 jeremybenn 
/* Disassemble ADI Blackfin Instructions.
2 
   Copyright 2005, 2007 Free Software Foundation, Inc.
3 
 
4 
   This file is part of libopcodes.
5 
 
6 
   This library is free software; you can redistribute it and/or modify
7 
   it under the terms of the GNU General Public License as published by
8 
   the Free Software Foundation; either version 3, or (at your option)
9 
   any later version.
10 
 
11 
   It is distributed in the hope that it will be useful, but WITHOUT
12 
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
14 
   License for more details.
15 
 
16 
   You should have received a copy of the GNU General Public License
17 
   along with this program; if not, write to the Free Software
18 
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 
   MA 02110-1301, USA.  */
20 
 
21 
#include <stdio.h>
22 
#include <stdlib.h>
23 
#include <string.h>
24 
 
25 
#include "opcode/bfin.h"
26 
 
27 
#define M_S2RND 1
28 
#define M_T     2
29 
#define M_W32   3
30 
#define M_FU    4
31 
#define M_TFU   6
32 
#define M_IS    8
33 
#define M_ISS2  9
34 
#define M_IH    11
35 
#define M_IU    12
36 
 
37 
#ifndef PRINTF
38 
#define PRINTF printf
39 
#endif
40 
 
41 
#ifndef EXIT
42 
#define EXIT exit
43 
#endif
44 
 
45 
typedef long TIword;
46 
 
47 
#define HOST_LONG_WORD_SIZE (sizeof (long) * 8)
48 
#define XFIELD(w,p,s)       (((w) & ((1 << (s)) - 1) << (p)) >> (p))
49 
#define SIGNEXTEND(v, n)    ((v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n)))
50 
#define MASKBITS(val, bits) (val & ((1 << bits) - 1))
51 
 
52 
#include "dis-asm.h"
53 
 
54 
typedef enum
55 
{
56 
  c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4,
57 
  c_imm4, c_uimm4s4, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_uimm5, c_imm6,
58 
  c_imm7, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10,
59 
  c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4,
60 
  c_uimm16, c_pcrel24,
61 
} const_forms_t;
62 
 
63 
static struct
64 
{
65 
  char *name;
66 
  int nbits;
67 
  char reloc;
68 
  char issigned;
69 
  char pcrel;
70 
  char scale;
71 
  char offset;
72 
  char negative;
73 
  char positive;
74 
} constant_formats[] =
75 
{
76 
  { "0", 0, 0, 1, 0, 0, 0, 0, 0},
77 
  { "1", 0, 0, 1, 0, 0, 0, 0, 0},
78 
  { "4", 0, 0, 1, 0, 0, 0, 0, 0},
79 
  { "2", 0, 0, 1, 0, 0, 0, 0, 0},
80 
  { "uimm2", 2, 0, 0, 0, 0, 0, 0, 0},
81 
  { "uimm3", 3, 0, 0, 0, 0, 0, 0, 0},
82 
  { "imm3", 3, 0, 1, 0, 0, 0, 0, 0},
83 
  { "pcrel4", 4, 1, 0, 1, 1, 0, 0, 0},
84 
  { "imm4", 4, 0, 1, 0, 0, 0, 0, 0},
85 
  { "uimm4s4", 4, 0, 0, 0, 2, 0, 0, 1},
86 
  { "uimm4", 4, 0, 0, 0, 0, 0, 0, 0},
87 
  { "uimm4s2", 4, 0, 0, 0, 1, 0, 0, 1},
88 
  { "negimm5s4", 5, 0, 1, 0, 2, 0, 1, 0},
89 
  { "imm5", 5, 0, 1, 0, 0, 0, 0, 0},
90 
  { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0},
91 
  { "imm6", 6, 0, 1, 0, 0, 0, 0, 0},
92 
  { "imm7", 7, 0, 1, 0, 0, 0, 0, 0},
93 
  { "imm8", 8, 0, 1, 0, 0, 0, 0, 0},
94 
  { "uimm8", 8, 0, 0, 0, 0, 0, 0, 0},
95 
  { "pcrel8", 8, 1, 0, 1, 1, 0, 0, 0},
96 
  { "uimm8s4", 8, 0, 0, 0, 2, 0, 0, 0},
97 
  { "pcrel8s4", 8, 1, 1, 1, 2, 0, 0, 0},
98 
  { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0},
99 
  { "pcrel10", 10, 1, 1, 1, 1, 0, 0, 0},
100 
  { "pcrel12", 12, 1, 1, 1, 1, 0, 0, 0},
101 
  { "imm16s4", 16, 0, 1, 0, 2, 0, 0, 0},
102 
  { "luimm16", 16, 1, 0, 0, 0, 0, 0, 0},
103 
  { "imm16", 16, 0, 1, 0, 0, 0, 0, 0},
104 
  { "huimm16", 16, 1, 0, 0, 0, 0, 0, 0},
105 
  { "rimm16", 16, 1, 1, 0, 0, 0, 0, 0},
106 
  { "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0},
107 
  { "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0},
108 
  { "uimm16", 16, 0, 0, 0, 0, 0, 0, 0},
109 
  { "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0}
110 
};
111 
 
112 
int _print_insn_bfin (bfd_vma pc, disassemble_info * outf);
113 
int print_insn_bfin (bfd_vma pc, disassemble_info * outf);
114 
 
115 
static char *
116 
fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info * outf)
117 
{
118 
  static char buf[60];
119 
 
120 
  if (constant_formats[cf].reloc)
121 
    {
122 
      bfd_vma ea = (((constant_formats[cf].pcrel ? SIGNEXTEND (x, constant_formats[cf].nbits)
123 
                      : x) + constant_formats[cf].offset) << constant_formats[cf].scale);
124 
      if (constant_formats[cf].pcrel)
125 
        ea += pc;
126 
 
127 
      outf->print_address_func (ea, outf);
128 
      return "";
129 
    }
130 
 
131 
  /* Negative constants have an implied sign bit.  */
132 
  if (constant_formats[cf].negative)
133 
    {
134 
      int nb = constant_formats[cf].nbits + 1;
135 
 
136 
      x = x | (1 << constant_formats[cf].nbits);
137 
      x = SIGNEXTEND (x, nb);
138 
    }
139 
  else
140 
    x = constant_formats[cf].issigned ? SIGNEXTEND (x, constant_formats[cf].nbits) : x;
141 
 
142 
  if (constant_formats[cf].offset)
143 
    x += constant_formats[cf].offset;
144 
 
145 
  if (constant_formats[cf].scale)
146 
    x <<= constant_formats[cf].scale;
147 
 
148 
  if (constant_formats[cf].issigned && x < 0)
149 
    sprintf (buf, "%ld", x);
150 
  else
151 
    sprintf (buf, "0x%lx", x);
152 
 
153 
  return buf;
154 
}
155 
 
156 
enum machine_registers
157 
{
158 
  REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
159 
  REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
160 
  REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
161 
  REG_R1_0, REG_R3_2, REG_R5_4, REG_R7_6, REG_P0, REG_P1, REG_P2, REG_P3,
162 
  REG_P4, REG_P5, REG_SP, REG_FP, REG_A0x, REG_A1x, REG_A0w, REG_A1w,
163 
  REG_A0, REG_A1, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1,
164 
  REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1,
165 
  REG_L2, REG_L3,
166 
  REG_AZ, REG_AN, REG_AC0, REG_AC1, REG_AV0, REG_AV1, REG_AV0S, REG_AV1S,
167 
  REG_AQ, REG_V, REG_VS,
168 
  REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, REG_CC, REG_LC0,
169 
  REG_LC1, REG_GP, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1,
170 
  REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN,
171 
  REG_RETE, REG_EMUDAT, REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6,
172 
  REG_BR7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
173 
  REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
174 
  REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
175 
  REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
176 
  REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
177 
  REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
178 
  REG_LASTREG,
179 
};
180 
 
181 
enum reg_class
182 
{
183 
  rc_dregs_lo, rc_dregs_hi, rc_dregs, rc_dregs_pair, rc_pregs, rc_spfp, rc_dregs_hilo, rc_accum_ext,
184 
  rc_accum_word, rc_accum, rc_iregs, rc_mregs, rc_bregs, rc_lregs, rc_dpregs, rc_gregs,
185 
  rc_regs, rc_statbits, rc_ignore_bits, rc_ccstat, rc_counters, rc_dregs2_sysregs1, rc_open, rc_sysregs2,
186 
  rc_sysregs3, rc_allregs,
187 
  LIM_REG_CLASSES
188 
};
189 
 
190 
static char *reg_names[] =
191 
{
192 
  "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L",
193 
  "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H",
194 
  "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
195 
  "R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3",
196 
  "P4", "P5", "SP", "FP", "A0.x", "A1.x", "A0.w", "A1.w",
197 
  "A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1",
198 
  "M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1",
199 
  "L2", "L3",
200 
  "AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S",
201 
  "AQ", "V", "VS",
202 
  "sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0",
203 
  "LC1", "GP", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1",
204 
  "CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN",
205 
  "RETE", "EMUDAT",
206 
  "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B",
207 
  "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L",
208 
  "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H",
209 
  "I0.L", "I1.L", "I2.L", "I3.L", "M0.L", "M1.L", "M2.L", "M3.L",
210 
  "B0.L", "B1.L", "B2.L", "B3.L", "L0.L", "L1.L", "L2.L", "L3.L",
211 
  "I0.H", "I1.H", "I2.H", "I3.H", "M0.H", "M1.H", "M2.H", "M3.H",
212 
  "B0.H", "B1.H", "B2.H", "B3.H", "L0.H", "L1.H", "L2.H", "L3.H",
213 
  "LASTREG",
214 
 
215 
};
216 
 
217 
#define REGNAME(x) ((x) < REG_LASTREG ? (reg_names[x]) : "...... Illegal register .......")
218 
 
219 
/* RL(0..7).  */
220 
static enum machine_registers decode_dregs_lo[] =
221 
{
222 
  REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
223 
};
224 
 
225 
#define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7])
226 
 
227 
/* RH(0..7).  */
228 
static enum machine_registers decode_dregs_hi[] =
229 
{
230 
  REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
231 
};
232 
 
233 
#define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7])
234 
 
235 
/* R(0..7).  */
236 
static enum machine_registers decode_dregs[] =
237 
{
238 
  REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
239 
};
240 
 
241 
#define dregs(x) REGNAME (decode_dregs[(x) & 7])
242 
 
243 
/* R BYTE(0..7).  */
244 
static enum machine_registers decode_dregs_byte[] =
245 
{
246 
  REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7,
247 
};
248 
 
249 
#define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
250 
#define dregs_pair(x) REGNAME (decode_dregs_pair[(x) & 7])
251 
 
252 
/* P(0..5) SP FP.  */
253 
static enum machine_registers decode_pregs[] =
254 
{
255 
  REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
256 
};
257 
 
258 
#define pregs(x)        REGNAME (decode_pregs[(x) & 7])
259 
#define spfp(x)         REGNAME (decode_spfp[(x) & 1])
260 
#define dregs_hilo(x,i) REGNAME (decode_dregs_hilo[((i) << 3)|x])
261 
#define accum_ext(x)    REGNAME (decode_accum_ext[(x) & 1])
262 
#define accum_word(x)   REGNAME (decode_accum_word[(x) & 1])
263 
#define accum(x)        REGNAME (decode_accum[(x) & 1])
264 
 
265 
/* I(0..3).  */
266 
static enum machine_registers decode_iregs[] =
267 
{
268 
  REG_I0, REG_I1, REG_I2, REG_I3,
269 
};
270 
 
271 
#define iregs(x) REGNAME (decode_iregs[(x) & 3])
272 
 
273 
/* M(0..3).  */
274 
static enum machine_registers decode_mregs[] =
275 
{
276 
  REG_M0, REG_M1, REG_M2, REG_M3,
277 
};
278 
 
279 
#define mregs(x) REGNAME (decode_mregs[(x) & 3])
280 
#define bregs(x) REGNAME (decode_bregs[(x) & 3])
281 
#define lregs(x) REGNAME (decode_lregs[(x) & 3])
282 
 
283 
/* dregs pregs.  */
284 
static enum machine_registers decode_dpregs[] =
285 
{
286 
  REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
287 
  REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
288 
};
289 
 
290 
#define dpregs(x) REGNAME (decode_dpregs[(x) & 15])
291 
 
292 
/* [dregs pregs].  */
293 
static enum machine_registers decode_gregs[] =
294 
{
295 
  REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
296 
  REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
297 
};
298 
 
299 
#define gregs(x,i) REGNAME (decode_gregs[((i) << 3)|x])
300 
 
301 
/* [dregs pregs (iregs mregs) (bregs lregs)].  */
302 
static enum machine_registers decode_regs[] =
303 
{
304 
  REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
305 
  REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
306 
  REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
307 
  REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
308 
};
309 
 
310 
#define regs(x,i) REGNAME (decode_regs[((i) << 3)|x])
311 
 
312 
/* [dregs pregs (iregs mregs) (bregs lregs) Low Half].  */
313 
static enum machine_registers decode_regs_lo[] =
314 
{
315 
  REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
316 
  REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
317 
  REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
318 
  REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
319 
};
320 
 
321 
#define regs_lo(x,i) REGNAME (decode_regs_lo[((i) << 3)|x])
322 
/* [dregs pregs (iregs mregs) (bregs lregs) High Half].  */
323 
static enum machine_registers decode_regs_hi[] =
324 
{
325 
  REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
326 
  REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
327 
  REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_LH2, REG_MH3,
328 
  REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
329 
};
330 
 
331 
#define regs_hi(x,i) REGNAME (decode_regs_hi[((i) << 3)|x])
332 
 
333 
static enum machine_registers decode_statbits[] =
334 
{
335 
  REG_AZ, REG_AN, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_AQ, REG_LASTREG,
336 
  REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_AC0, REG_AC1, REG_LASTREG, REG_LASTREG,
337 
  REG_AV0, REG_AV0S, REG_AV1, REG_AV1S, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
338 
  REG_V, REG_VS, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
339 
};
340 
 
341 
#define statbits(x)     REGNAME (decode_statbits[(x) & 31])
342 
#define ignore_bits(x)  REGNAME (decode_ignore_bits[(x) & 7])
343 
#define ccstat(x)       REGNAME (decode_ccstat[(x) & 0])
344 
 
345 
/* LC0 LC1.  */
346 
static enum machine_registers decode_counters[] =
347 
{
348 
  REG_LC0, REG_LC1,
349 
};
350 
 
351 
#define counters(x)        REGNAME (decode_counters[(x) & 1])
352 
#define dregs2_sysregs1(x) REGNAME (decode_dregs2_sysregs1[(x) & 7])
353 
 
354 
/* [dregs pregs (iregs mregs) (bregs lregs)
355 
   dregs2_sysregs1 open sysregs2 sysregs3].  */
356 
static enum machine_registers decode_allregs[] =
357 
{
358 
  REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
359 
  REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
360 
  REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
361 
  REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
362 
  REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_GP, REG_LASTREG, REG_ASTAT, REG_RETS,
363 
  REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
364 
  REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2,
365 
  REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT, REG_LASTREG,
366 
};
367 
 
368 
#define allregs(x,i)    REGNAME (decode_allregs[((i) << 3) | x])
369 
#define uimm16s4(x)     fmtconst (c_uimm16s4, x, 0, outf)
370 
#define pcrel4(x)       fmtconst (c_pcrel4, x, pc, outf)
371 
#define pcrel8(x)       fmtconst (c_pcrel8, x, pc, outf)
372 
#define pcrel8s4(x)     fmtconst (c_pcrel8s4, x, pc, outf)
373 
#define pcrel10(x)      fmtconst (c_pcrel10, x, pc, outf)
374 
#define pcrel12(x)      fmtconst (c_pcrel12, x, pc, outf)
375 
#define negimm5s4(x)    fmtconst (c_negimm5s4, x, 0, outf)
376 
#define rimm16(x)       fmtconst (c_rimm16, x, 0, outf)
377 
#define huimm16(x)      fmtconst (c_huimm16, x, 0, outf)
378 
#define imm16(x)        fmtconst (c_imm16, x, 0, outf)
379 
#define uimm2(x)        fmtconst (c_uimm2, x, 0, outf)
380 
#define uimm3(x)        fmtconst (c_uimm3, x, 0, outf)
381 
#define luimm16(x)      fmtconst (c_luimm16, x, 0, outf)
382 
#define uimm4(x)        fmtconst (c_uimm4, x, 0, outf)
383 
#define uimm5(x)        fmtconst (c_uimm5, x, 0, outf)
384 
#define imm16s2(x)      fmtconst (c_imm16s2, x, 0, outf)
385 
#define uimm8(x)        fmtconst (c_uimm8, x, 0, outf)
386 
#define imm16s4(x)      fmtconst (c_imm16s4, x, 0, outf)
387 
#define uimm4s2(x)      fmtconst (c_uimm4s2, x, 0, outf)
388 
#define uimm4s4(x)      fmtconst (c_uimm4s4, x, 0, outf)
389 
#define lppcrel10(x)    fmtconst (c_lppcrel10, x, pc, outf)
390 
#define imm3(x)         fmtconst (c_imm3, x, 0, outf)
391 
#define imm4(x)         fmtconst (c_imm4, x, 0, outf)
392 
#define uimm8s4(x)      fmtconst (c_uimm8s4, x, 0, outf)
393 
#define imm5(x)         fmtconst (c_imm5, x, 0, outf)
394 
#define imm6(x)         fmtconst (c_imm6, x, 0, outf)
395 
#define imm7(x)         fmtconst (c_imm7, x, 0, outf)
396 
#define imm8(x)         fmtconst (c_imm8, x, 0, outf)
397 
#define pcrel24(x)      fmtconst (c_pcrel24, x, pc, outf)
398 
#define uimm16(x)       fmtconst (c_uimm16, x, 0, outf)
399 
 
400 
/* (arch.pm)arch_disassembler_functions.  */
401 
#ifndef OUTS
402 
#define OUTS(p, txt) ((p) ? (((txt)[0]) ? (p->fprintf_func)(p->stream, txt) :0) :0)
403 
#endif
404 
 
405 
static void
406 
amod0 (int s0, int x0, disassemble_info *outf)
407 
{
408 
  if (s0 == 1 && x0 == 0)
409 
    OUTS (outf, "(S)");
410 
  else if (s0 == 0 && x0 == 1)
411 
    OUTS (outf, "(CO)");
412 
  else if (s0 == 1 && x0 == 1)
413 
    OUTS (outf, "(SCO)");
414 
}
415 
 
416 
static void
417 
amod1 (int s0, int x0, disassemble_info *outf)
418 
{
419 
  if (s0 == 0 && x0 == 0)
420 
    OUTS (outf, "(NS)");
421 
  else if (s0 == 1 && x0 == 0)
422 
    OUTS (outf, "(S)");
423 
}
424 
 
425 
static void
426 
amod0amod2 (int s0, int x0, int aop0, disassemble_info *outf)
427 
{
428 
  if (s0 == 1 && x0 == 0 && aop0 == 0)
429 
    OUTS (outf, "(S)");
430 
  else if (s0 == 0 && x0 == 1 && aop0 == 0)
431 
    OUTS (outf, "(CO)");
432 
  else if (s0 == 1 && x0 == 1 && aop0 == 0)
433 
    OUTS (outf, "(SCO)");
434 
  else if (s0 == 0 && x0 == 0 && aop0 == 2)
435 
    OUTS (outf, "(ASR)");
436 
  else if (s0 == 1 && x0 == 0 && aop0 == 2)
437 
    OUTS (outf, "(S,ASR)");
438 
  else if (s0 == 0 && x0 == 1 && aop0 == 2)
439 
    OUTS (outf, "(CO,ASR)");
440 
  else if (s0 == 1 && x0 == 1 && aop0 == 2)
441 
    OUTS (outf, "(SCO,ASR)");
442 
  else if (s0 == 0 && x0 == 0 && aop0 == 3)
443 
    OUTS (outf, "(ASL)");
444 
  else if (s0 == 1 && x0 == 0 && aop0 == 3)
445 
    OUTS (outf, "(S,ASL)");
446 
  else if (s0 == 0 && x0 == 1 && aop0 == 3)
447 
    OUTS (outf, "(CO,ASL)");
448 
  else if (s0 == 1 && x0 == 1 && aop0 == 3)
449 
    OUTS (outf, "(SCO,ASL)");
450 
}
451 
 
452 
static void
453 
searchmod (int r0, disassemble_info *outf)
454 
{
455 
  if (r0 == 0)
456 
    OUTS (outf, "GT");
457 
  else if (r0 == 1)
458 
    OUTS (outf, "GE");
459 
  else if (r0 == 2)
460 
    OUTS (outf, "LT");
461 
  else if (r0 == 3)
462 
    OUTS (outf, "LE");
463 
}
464 
 
465 
static void
466 
aligndir (int r0, disassemble_info *outf)
467 
{
468 
  if (r0 == 1)
469 
    OUTS (outf, "(R)");
470 
}
471 
 
472 
static int
473 
decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info * outf)
474 
{
475 
  char *s0, *s1;
476 
 
477 
  if (h0)
478 
    s0 = dregs_hi (src0);
479 
  else
480 
    s0 = dregs_lo (src0);
481 
 
482 
  if (h1)
483 
    s1 = dregs_hi (src1);
484 
  else
485 
    s1 = dregs_lo (src1);
486 
 
487 
  OUTS (outf, s0);
488 
  OUTS (outf, " * ");
489 
  OUTS (outf, s1);
490 
  return 0;
491 
}
492 
 
493 
static int
494 
decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info * outf)
495 
{
496 
  char *a;
497 
  char *sop = "<unknown op>";
498 
 
499 
  if (which)
500 
    a = "a1";
501 
  else
502 
    a = "a0";
503 
 
504 
  if (op == 3)
505 
    {
506 
      OUTS (outf, a);
507 
      return 0;
508 
    }
509 
 
510 
  switch (op)
511 
    {
512 
    case 0: sop = "=";   break;
513 
    case 1: sop = "+=";  break;
514 
    case 2: sop = "-=";  break;
515 
    default: break;
516 
    }
517 
 
518 
  OUTS (outf, a);
519 
  OUTS (outf, " ");
520 
  OUTS (outf, sop);
521 
  OUTS (outf, " ");
522 
  decode_multfunc (h0, h1, src0, src1, outf);
523 
 
524 
  return 0;
525 
}
526 
 
527 
static void
528 
decode_optmode (int mod, int MM, disassemble_info *outf)
529 
{
530 
  if (mod == 0 && MM == 0)
531 
    return;
532 
 
533 
  OUTS (outf, " (");
534 
 
535 
  if (MM && !mod)
536 
    {
537 
      OUTS (outf, "M)");
538 
      return;
539 
    }
540 
 
541 
  if (MM)
542 
    OUTS (outf, "M, ");
543 
 
544 
  if (mod == M_S2RND)
545 
    OUTS (outf, "S2RND");
546 
  else if (mod == M_T)
547 
    OUTS (outf, "T");
548 
  else if (mod == M_W32)
549 
    OUTS (outf, "W32");
550 
  else if (mod == M_FU)
551 
    OUTS (outf, "FU");
552 
  else if (mod == M_TFU)
553 
    OUTS (outf, "TFU");
554 
  else if (mod == M_IS)
555 
    OUTS (outf, "IS");
556 
  else if (mod == M_ISS2)
557 
    OUTS (outf, "ISS2");
558 
  else if (mod == M_IH)
559 
    OUTS (outf, "IH");
560 
  else if (mod == M_IU)
561 
    OUTS (outf, "IU");
562 
  else
563 
    abort ();
564 
 
565 
  OUTS (outf, ")");
566 
}
567 
 
568 
static int
569 
decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf)
570 
{
571 
  /* ProgCtrl
572 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
573 
     | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
574 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
575 
  int poprnd  = ((iw0 >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
576 
  int prgfunc = ((iw0 >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
577 
 
578 
  if (prgfunc == 0 && poprnd == 0)
579 
    OUTS (outf, "NOP");
580 
  else if (prgfunc == 1 && poprnd == 0)
581 
    OUTS (outf, "RTS");
582 
  else if (prgfunc == 1 && poprnd == 1)
583 
    OUTS (outf, "RTI");
584 
  else if (prgfunc == 1 && poprnd == 2)
585 
    OUTS (outf, "RTX");
586 
  else if (prgfunc == 1 && poprnd == 3)
587 
    OUTS (outf, "RTN");
588 
  else if (prgfunc == 1 && poprnd == 4)
589 
    OUTS (outf, "RTE");
590 
  else if (prgfunc == 2 && poprnd == 0)
591 
    OUTS (outf, "IDLE");
592 
  else if (prgfunc == 2 && poprnd == 3)
593 
    OUTS (outf, "CSYNC");
594 
  else if (prgfunc == 2 && poprnd == 4)
595 
    OUTS (outf, "SSYNC");
596 
  else if (prgfunc == 2 && poprnd == 5)
597 
    OUTS (outf, "EMUEXCPT");
598 
  else if (prgfunc == 3)
599 
    {
600 
      OUTS (outf, "CLI  ");
601 
      OUTS (outf, dregs (poprnd));
602 
    }
603 
  else if (prgfunc == 4)
604 
    {
605 
      OUTS (outf, "STI  ");
606 
      OUTS (outf, dregs (poprnd));
607 
    }
608 
  else if (prgfunc == 5)
609 
    {
610 
      OUTS (outf, "JUMP  (");
611 
      OUTS (outf, pregs (poprnd));
612 
      OUTS (outf, ")");
613 
    }
614 
  else if (prgfunc == 6)
615 
    {
616 
      OUTS (outf, "CALL  (");
617 
      OUTS (outf, pregs (poprnd));
618 
      OUTS (outf, ")");
619 
    }
620 
  else if (prgfunc == 7)
621 
    {
622 
      OUTS (outf, "CALL  (PC+");
623 
      OUTS (outf, pregs (poprnd));
624 
      OUTS (outf, ")");
625 
    }
626 
  else if (prgfunc == 8)
627 
    {
628 
      OUTS (outf, "JUMP  (PC+");
629 
      OUTS (outf, pregs (poprnd));
630 
      OUTS (outf, ")");
631 
    }
632 
  else if (prgfunc == 9)
633 
    {
634 
      OUTS (outf, "RAISE  ");
635 
      OUTS (outf, uimm4 (poprnd));
636 
    }
637 
  else if (prgfunc == 10)
638 
    {
639 
      OUTS (outf, "EXCPT  ");
640 
      OUTS (outf, uimm4 (poprnd));
641 
    }
642 
  else if (prgfunc == 11)
643 
    {
644 
      OUTS (outf, "TESTSET  (");
645 
      OUTS (outf, pregs (poprnd));
646 
      OUTS (outf, ")");
647 
    }
648 
  else
649 
    return 0;
650 
  return 2;
651 
}
652 
 
653 
static int
654 
decode_CaCTRL_0 (TIword iw0, disassemble_info *outf)
655 
{
656 
  /* CaCTRL
657 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
658 
     | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
659 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
660 
  int a   = ((iw0 >> CaCTRL_a_bits) & CaCTRL_a_mask);
661 
  int op  = ((iw0 >> CaCTRL_op_bits) & CaCTRL_op_mask);
662 
  int reg = ((iw0 >> CaCTRL_reg_bits) & CaCTRL_reg_mask);
663 
 
664 
  if (a == 0 && op == 0)
665 
    {
666 
      OUTS (outf, "PREFETCH[");
667 
      OUTS (outf, pregs (reg));
668 
      OUTS (outf, "]");
669 
    }
670 
  else if (a == 0 && op == 1)
671 
    {
672 
      OUTS (outf, "FLUSHINV[");
673 
      OUTS (outf, pregs (reg));
674 
      OUTS (outf, "]");
675 
    }
676 
  else if (a == 0 && op == 2)
677 
    {
678 
      OUTS (outf, "FLUSH[");
679 
      OUTS (outf, pregs (reg));
680 
      OUTS (outf, "]");
681 
    }
682 
  else if (a == 0 && op == 3)
683 
    {
684 
      OUTS (outf, "IFLUSH[");
685 
      OUTS (outf, pregs (reg));
686 
      OUTS (outf, "]");
687 
    }
688 
  else if (a == 1 && op == 0)
689 
    {
690 
      OUTS (outf, "PREFETCH[");
691 
      OUTS (outf, pregs (reg));
692 
      OUTS (outf, "++]");
693 
    }
694 
  else if (a == 1 && op == 1)
695 
    {
696 
      OUTS (outf, "FLUSHINV[");
697 
      OUTS (outf, pregs (reg));
698 
      OUTS (outf, "++]");
699 
    }
700 
  else if (a == 1 && op == 2)
701 
    {
702 
      OUTS (outf, "FLUSH[");
703 
      OUTS (outf, pregs (reg));
704 
      OUTS (outf, "++]");
705 
    }
706 
  else if (a == 1 && op == 3)
707 
    {
708 
      OUTS (outf, "IFLUSH[");
709 
      OUTS (outf, pregs (reg));
710 
      OUTS (outf, "++]");
711 
    }
712 
  else
713 
    return 0;
714 
  return 2;
715 
}
716 
 
717 
static int
718 
decode_PushPopReg_0 (TIword iw0, disassemble_info *outf)
719 
{
720 
  /* PushPopReg
721 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
722 
     | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
723 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
724 
  int W   = ((iw0 >> PushPopReg_W_bits) & PushPopReg_W_mask);
725 
  int grp = ((iw0 >> PushPopReg_grp_bits) & PushPopReg_grp_mask);
726 
  int reg = ((iw0 >> PushPopReg_reg_bits) & PushPopReg_reg_mask);
727 
 
728 
  if (W == 0)
729 
    {
730 
      OUTS (outf, allregs (reg, grp));
731 
      OUTS (outf, " = [SP++]");
732 
    }
733 
  else if (W == 1)
734 
    {
735 
      OUTS (outf, "[--SP] = ");
736 
      OUTS (outf, allregs (reg, grp));
737 
    }
738 
  else
739 
    return 0;
740 
  return 2;
741 
}
742 
 
743 
static int
744 
decode_PushPopMultiple_0 (TIword iw0, disassemble_info *outf)
745 
{
746 
  /* PushPopMultiple
747 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
748 
     | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
749 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
750 
  int p  = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask);
751 
  int d  = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask);
752 
  int W  = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask);
753 
  int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask);
754 
  int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask);
755 
  char ps[5], ds[5];
756 
 
757 
  sprintf (ps, "%d", pr);
758 
  sprintf (ds, "%d", dr);
759 
 
760 
  if (W == 1 && d == 1 && p == 1)
761 
    {
762 
      OUTS (outf, "[--SP] = (R7:");
763 
      OUTS (outf, ds);
764 
      OUTS (outf, ", P5:");
765 
      OUTS (outf, ps);
766 
      OUTS (outf, ")");
767 
    }
768 
  else if (W == 1 && d == 1 && p == 0)
769 
    {
770 
      OUTS (outf, "[--SP] = (R7:");
771 
      OUTS (outf, ds);
772 
      OUTS (outf, ")");
773 
    }
774 
  else if (W == 1 && d == 0 && p == 1)
775 
    {
776 
      OUTS (outf, "[--SP] = (P5:");
777 
      OUTS (outf, ps);
778 
      OUTS (outf, ")");
779 
    }
780 
  else if (W == 0 && d == 1 && p == 1)
781 
    {
782 
      OUTS (outf, "(R7:");
783 
      OUTS (outf, ds);
784 
      OUTS (outf, ", P5:");
785 
      OUTS (outf, ps);
786 
      OUTS (outf, ") = [SP++]");
787 
    }
788 
  else if (W == 0 && d == 1 && p == 0)
789 
    {
790 
      OUTS (outf, "(R7:");
791 
      OUTS (outf, ds);
792 
      OUTS (outf, ") = [SP++]");
793 
    }
794 
  else if (W == 0 && d == 0 && p == 1)
795 
    {
796 
      OUTS (outf, "(P5:");
797 
      OUTS (outf, ps);
798 
      OUTS (outf, ") = [SP++]");
799 
    }
800 
  else
801 
    return 0;
802 
  return 2;
803 
}
804 
 
805 
static int
806 
decode_ccMV_0 (TIword iw0, disassemble_info *outf)
807 
{
808 
  /* ccMV
809 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
810 
     | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
811 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
812 
  int s  = ((iw0 >> CCmv_s_bits) & CCmv_s_mask);
813 
  int d  = ((iw0 >> CCmv_d_bits) & CCmv_d_mask);
814 
  int T  = ((iw0 >> CCmv_T_bits) & CCmv_T_mask);
815 
  int src = ((iw0 >> CCmv_src_bits) & CCmv_src_mask);
816 
  int dst = ((iw0 >> CCmv_dst_bits) & CCmv_dst_mask);
817 
 
818 
  if (T == 1)
819 
    {
820 
      OUTS (outf, "IF CC ");
821 
      OUTS (outf, gregs (dst, d));
822 
      OUTS (outf, " = ");
823 
      OUTS (outf, gregs (src, s));
824 
    }
825 
  else if (T == 0)
826 
    {
827 
      OUTS (outf, "IF ! CC ");
828 
      OUTS (outf, gregs (dst, d));
829 
      OUTS (outf, " = ");
830 
      OUTS (outf, gregs (src, s));
831 
    }
832 
  else
833 
    return 0;
834 
  return 2;
835 
}
836 
 
837 
static int
838 
decode_CCflag_0 (TIword iw0, disassemble_info *outf)
839 
{
840 
  /* CCflag
841 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
842 
     | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
843 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
844 
  int x = ((iw0 >> CCflag_x_bits) & CCflag_x_mask);
845 
  int y = ((iw0 >> CCflag_y_bits) & CCflag_y_mask);
846 
  int I = ((iw0 >> CCflag_I_bits) & CCflag_I_mask);
847 
  int G = ((iw0 >> CCflag_G_bits) & CCflag_G_mask);
848 
  int opc = ((iw0 >> CCflag_opc_bits) & CCflag_opc_mask);
849 
 
850 
  if (opc == 0 && I == 0 && G == 0)
851 
    {
852 
      OUTS (outf, "CC=");
853 
      OUTS (outf, dregs (x));
854 
      OUTS (outf, "==");
855 
      OUTS (outf, dregs (y));
856 
    }
857 
  else if (opc == 1 && I == 0 && G == 0)
858 
    {
859 
      OUTS (outf, "CC=");
860 
      OUTS (outf, dregs (x));
861 
      OUTS (outf, "<");
862 
      OUTS (outf, dregs (y));
863 
    }
864 
  else if (opc == 2 && I == 0 && G == 0)
865 
    {
866 
      OUTS (outf, "CC=");
867 
      OUTS (outf, dregs (x));
868 
      OUTS (outf, "<=");
869 
      OUTS (outf, dregs (y));
870 
    }
871 
  else if (opc == 3 && I == 0 && G == 0)
872 
    {
873 
      OUTS (outf, "CC=");
874 
      OUTS (outf, dregs (x));
875 
      OUTS (outf, "<");
876 
      OUTS (outf, dregs (y));
877 
      OUTS (outf, "(IU)");
878 
    }
879 
  else if (opc == 4 && I == 0 && G == 0)
880 
    {
881 
      OUTS (outf, "CC=");
882 
      OUTS (outf, dregs (x));
883 
      OUTS (outf, "<=");
884 
      OUTS (outf, dregs (y));
885 
      OUTS (outf, "(IU)");
886 
    }
887 
  else if (opc == 0 && I == 1 && G == 0)
888 
    {
889 
      OUTS (outf, "CC=");
890 
      OUTS (outf, dregs (x));
891 
      OUTS (outf, "==");
892 
      OUTS (outf, imm3 (y));
893 
    }
894 
  else if (opc == 1 && I == 1 && G == 0)
895 
    {
896 
      OUTS (outf, "CC=");
897 
      OUTS (outf, dregs (x));
898 
      OUTS (outf, "<");
899 
      OUTS (outf, imm3 (y));
900 
    }
901 
  else if (opc == 2 && I == 1 && G == 0)
902 
    {
903 
      OUTS (outf, "CC=");
904 
      OUTS (outf, dregs (x));
905 
      OUTS (outf, "<=");
906 
      OUTS (outf, imm3 (y));
907 
    }
908 
  else if (opc == 3 && I == 1 && G == 0)
909 
    {
910 
      OUTS (outf, "CC=");
911 
      OUTS (outf, dregs (x));
912 
      OUTS (outf, "<");
913 
      OUTS (outf, uimm3 (y));
914 
      OUTS (outf, "(IU)");
915 
    }
916 
  else if (opc == 4 && I == 1 && G == 0)
917 
    {
918 
      OUTS (outf, "CC=");
919 
      OUTS (outf, dregs (x));
920 
      OUTS (outf, "<=");
921 
      OUTS (outf, uimm3 (y));
922 
      OUTS (outf, "(IU)");
923 
    }
924 
  else if (opc == 0 && I == 0 && G == 1)
925 
    {
926 
      OUTS (outf, "CC=");
927 
      OUTS (outf, pregs (x));
928 
      OUTS (outf, "==");
929 
      OUTS (outf, pregs (y));
930 
    }
931 
  else if (opc == 1 && I == 0 && G == 1)
932 
    {
933 
      OUTS (outf, "CC=");
934 
      OUTS (outf, pregs (x));
935 
      OUTS (outf, "<");
936 
      OUTS (outf, pregs (y));
937 
    }
938 
  else if (opc == 2 && I == 0 && G == 1)
939 
    {
940 
      OUTS (outf, "CC=");
941 
      OUTS (outf, pregs (x));
942 
      OUTS (outf, "<=");
943 
      OUTS (outf, pregs (y));
944 
    }
945 
  else if (opc == 3 && I == 0 && G == 1)
946 
    {
947 
      OUTS (outf, "CC=");
948 
      OUTS (outf, pregs (x));
949 
      OUTS (outf, "<");
950 
      OUTS (outf, pregs (y));
951 
      OUTS (outf, "(IU)");
952 
    }
953 
  else if (opc == 4 && I == 0 && G == 1)
954 
    {
955 
      OUTS (outf, "CC=");
956 
      OUTS (outf, pregs (x));
957 
      OUTS (outf, "<=");
958 
      OUTS (outf, pregs (y));
959 
      OUTS (outf, "(IU)");
960 
    }
961 
  else if (opc == 0 && I == 1 && G == 1)
962 
    {
963 
      OUTS (outf, "CC=");
964 
      OUTS (outf, pregs (x));
965 
      OUTS (outf, "==");
966 
      OUTS (outf, imm3 (y));
967 
    }
968 
  else if (opc == 1 && I == 1 && G == 1)
969 
    {
970 
      OUTS (outf, "CC=");
971 
      OUTS (outf, pregs (x));
972 
      OUTS (outf, "<");
973 
      OUTS (outf, imm3 (y));
974 
    }
975 
  else if (opc == 2 && I == 1 && G == 1)
976 
    {
977 
      OUTS (outf, "CC=");
978 
      OUTS (outf, pregs (x));
979 
      OUTS (outf, "<=");
980 
      OUTS (outf, imm3 (y));
981 
    }
982 
  else if (opc == 3 && I == 1 && G == 1)
983 
    {
984 
      OUTS (outf, "CC=");
985 
      OUTS (outf, pregs (x));
986 
      OUTS (outf, "<");
987 
      OUTS (outf, uimm3 (y));
988 
      OUTS (outf, "(IU)");
989 
    }
990 
  else if (opc == 4 && I == 1 && G == 1)
991 
    {
992 
      OUTS (outf, "CC=");
993 
      OUTS (outf, pregs (x));
994 
      OUTS (outf, "<=");
995 
      OUTS (outf, uimm3 (y));
996 
      OUTS (outf, "(IU)");
997 
    }
998 
  else if (opc == 5 && I == 0 && G == 0)
999 
    OUTS (outf, "CC=A0==A1");
1000 
 
1001 
  else if (opc == 6 && I == 0 && G == 0)
1002 
    OUTS (outf, "CC=A0<A1");
1003 
 
1004 
  else if (opc == 7 && I == 0 && G == 0)
1005 
    OUTS (outf, "CC=A0<=A1");
1006 
 
1007 
  else
1008 
    return 0;
1009 
  return 2;
1010 
}
1011 
 
1012 
static int
1013 
decode_CC2dreg_0 (TIword iw0, disassemble_info *outf)
1014 
{
1015 
  /* CC2dreg
1016 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1017 
     | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
1018 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1019 
  int op  = ((iw0 >> CC2dreg_op_bits) & CC2dreg_op_mask);
1020 
  int reg = ((iw0 >> CC2dreg_reg_bits) & CC2dreg_reg_mask);
1021 
 
1022 
  if (op == 0)
1023 
    {
1024 
      OUTS (outf, dregs (reg));
1025 
      OUTS (outf, "=CC");
1026 
    }
1027 
  else if (op == 1)
1028 
    {
1029 
      OUTS (outf, "CC=");
1030 
      OUTS (outf, dregs (reg));
1031 
    }
1032 
  else if (op == 3)
1033 
    OUTS (outf, "CC=!CC");
1034 
  else
1035 
    return 0;
1036 
 
1037 
  return 2;
1038 
}
1039 
 
1040 
static int
1041 
decode_CC2stat_0 (TIword iw0, disassemble_info *outf)
1042 
{
1043 
  /* CC2stat
1044 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1045 
     | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
1046 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1047 
  int D    = ((iw0 >> CC2stat_D_bits) & CC2stat_D_mask);
1048 
  int op   = ((iw0 >> CC2stat_op_bits) & CC2stat_op_mask);
1049 
  int cbit = ((iw0 >> CC2stat_cbit_bits) & CC2stat_cbit_mask);
1050 
 
1051 
  if (op == 0 && D == 0)
1052 
    {
1053 
      OUTS (outf, "CC = ");
1054 
      OUTS (outf, statbits (cbit));
1055 
    }
1056 
  else if (op == 1 && D == 0)
1057 
    {
1058 
      OUTS (outf, "CC|=");
1059 
      OUTS (outf, statbits (cbit));
1060 
    }
1061 
  else if (op == 2 && D == 0)
1062 
    {
1063 
      OUTS (outf, "CC&=");
1064 
      OUTS (outf, statbits (cbit));
1065 
    }
1066 
  else if (op == 3 && D == 0)
1067 
    {
1068 
      OUTS (outf, "CC^=");
1069 
      OUTS (outf, statbits (cbit));
1070 
    }
1071 
  else if (op == 0 && D == 1)
1072 
    {
1073 
      OUTS (outf, statbits (cbit));
1074 
      OUTS (outf, "=CC");
1075 
    }
1076 
  else if (op == 1 && D == 1)
1077 
    {
1078 
      OUTS (outf, statbits (cbit));
1079 
      OUTS (outf, "|=CC");
1080 
    }
1081 
  else if (op == 2 && D == 1)
1082 
    {
1083 
      OUTS (outf, statbits (cbit));
1084 
      OUTS (outf, "&=CC");
1085 
    }
1086 
  else if (op == 3 && D == 1)
1087 
    {
1088 
      OUTS (outf, statbits (cbit));
1089 
      OUTS (outf, "^=CC");
1090 
    }
1091 
  else
1092 
    return 0;
1093 
 
1094 
  return 2;
1095 
}
1096 
 
1097 
static int
1098 
decode_BRCC_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1099 
{
1100 
  /* BRCC
1101 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1102 
     | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
1103 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1104 
  int B = ((iw0 >> BRCC_B_bits) & BRCC_B_mask);
1105 
  int T = ((iw0 >> BRCC_T_bits) & BRCC_T_mask);
1106 
  int offset = ((iw0 >> BRCC_offset_bits) & BRCC_offset_mask);
1107 
 
1108 
  if (T == 1 && B == 1)
1109 
    {
1110 
      OUTS (outf, "IF CC JUMP ");
1111 
      OUTS (outf, pcrel10 (offset));
1112 
      OUTS (outf, "(BP)");
1113 
    }
1114 
  else if (T == 0 && B == 1)
1115 
    {
1116 
      OUTS (outf, "IF ! CC JUMP ");
1117 
      OUTS (outf, pcrel10 (offset));
1118 
      OUTS (outf, "(BP)");
1119 
    }
1120 
  else if (T == 1)
1121 
    {
1122 
      OUTS (outf, "IF CC JUMP ");
1123 
      OUTS (outf, pcrel10 (offset));
1124 
    }
1125 
  else if (T == 0)
1126 
    {
1127 
      OUTS (outf, "IF ! CC JUMP ");
1128 
      OUTS (outf, pcrel10 (offset));
1129 
    }
1130 
  else
1131 
    return 0;
1132 
 
1133 
  return 2;
1134 
}
1135 
 
1136 
static int
1137 
decode_UJUMP_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1138 
{
1139 
  /* UJUMP
1140 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1141 
     | 0 | 0 | 1 | 0 |.offset........................................|
1142 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1143 
  int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask);
1144 
 
1145 
  OUTS (outf, "JUMP.S  ");
1146 
  OUTS (outf, pcrel12 (offset));
1147 
  return 2;
1148 
}
1149 
 
1150 
static int
1151 
decode_REGMV_0 (TIword iw0, disassemble_info *outf)
1152 
{
1153 
  /* REGMV
1154 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1155 
     | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
1156 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1157 
  int gs  = ((iw0 >> RegMv_gs_bits) & RegMv_gs_mask);
1158 
  int gd  = ((iw0 >> RegMv_gd_bits) & RegMv_gd_mask);
1159 
  int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask);
1160 
  int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask);
1161 
 
1162 
  OUTS (outf, allregs (dst, gd));
1163 
  OUTS (outf, "=");
1164 
  OUTS (outf, allregs (src, gs));
1165 
  return 2;
1166 
}
1167 
 
1168 
static int
1169 
decode_ALU2op_0 (TIword iw0, disassemble_info *outf)
1170 
{
1171 
  /* ALU2op
1172 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1173 
     | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
1174 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1175 
  int src = ((iw0 >> ALU2op_src_bits) & ALU2op_src_mask);
1176 
  int opc = ((iw0 >> ALU2op_opc_bits) & ALU2op_opc_mask);
1177 
  int dst = ((iw0 >> ALU2op_dst_bits) & ALU2op_dst_mask);
1178 
 
1179 
  if (opc == 0)
1180 
    {
1181 
      OUTS (outf, dregs (dst));
1182 
      OUTS (outf, ">>>=");
1183 
      OUTS (outf, dregs (src));
1184 
    }
1185 
  else if (opc == 1)
1186 
    {
1187 
      OUTS (outf, dregs (dst));
1188 
      OUTS (outf, ">>=");
1189 
      OUTS (outf, dregs (src));
1190 
    }
1191 
  else if (opc == 2)
1192 
    {
1193 
      OUTS (outf, dregs (dst));
1194 
      OUTS (outf, "<<=");
1195 
      OUTS (outf, dregs (src));
1196 
    }
1197 
  else if (opc == 3)
1198 
    {
1199 
      OUTS (outf, dregs (dst));
1200 
      OUTS (outf, "*=");
1201 
      OUTS (outf, dregs (src));
1202 
    }
1203 
  else if (opc == 4)
1204 
    {
1205 
      OUTS (outf, dregs (dst));
1206 
      OUTS (outf, "=(");
1207 
      OUTS (outf, dregs (dst));
1208 
      OUTS (outf, "+");
1209 
      OUTS (outf, dregs (src));
1210 
      OUTS (outf, ")<<1");
1211 
    }
1212 
  else if (opc == 5)
1213 
    {
1214 
      OUTS (outf, dregs (dst));
1215 
      OUTS (outf, "=(");
1216 
      OUTS (outf, dregs (dst));
1217 
      OUTS (outf, "+");
1218 
      OUTS (outf, dregs (src));
1219 
      OUTS (outf, ")<<2");
1220 
    }
1221 
  else if (opc == 8)
1222 
    {
1223 
      OUTS (outf, "DIVQ(");
1224 
      OUTS (outf, dregs (dst));
1225 
      OUTS (outf, ",");
1226 
      OUTS (outf, dregs (src));
1227 
      OUTS (outf, ")");
1228 
    }
1229 
  else if (opc == 9)
1230 
    {
1231 
      OUTS (outf, "DIVS(");
1232 
      OUTS (outf, dregs (dst));
1233 
      OUTS (outf, ",");
1234 
      OUTS (outf, dregs (src));
1235 
      OUTS (outf, ")");
1236 
    }
1237 
  else if (opc == 10)
1238 
    {
1239 
      OUTS (outf, dregs (dst));
1240 
      OUTS (outf, "=");
1241 
      OUTS (outf, dregs_lo (src));
1242 
      OUTS (outf, "(X)");
1243 
    }
1244 
  else if (opc == 11)
1245 
    {
1246 
      OUTS (outf, dregs (dst));
1247 
      OUTS (outf, "=");
1248 
      OUTS (outf, dregs_lo (src));
1249 
      OUTS (outf, "(Z)");
1250 
    }
1251 
  else if (opc == 12)
1252 
    {
1253 
      OUTS (outf, dregs (dst));
1254 
      OUTS (outf, "=");
1255 
      OUTS (outf, dregs_byte (src));
1256 
      OUTS (outf, "(X)");
1257 
    }
1258 
  else if (opc == 13)
1259 
    {
1260 
      OUTS (outf, dregs (dst));
1261 
      OUTS (outf, "=");
1262 
      OUTS (outf, dregs_byte (src));
1263 
      OUTS (outf, "(Z)");
1264 
    }
1265 
  else if (opc == 14)
1266 
    {
1267 
      OUTS (outf, dregs (dst));
1268 
      OUTS (outf, "=-");
1269 
      OUTS (outf, dregs (src));
1270 
    }
1271 
  else if (opc == 15)
1272 
    {
1273 
      OUTS (outf, dregs (dst));
1274 
      OUTS (outf, "=~");
1275 
      OUTS (outf, dregs (src));
1276 
    }
1277 
  else
1278 
    return 0;
1279 
 
1280 
  return 2;
1281 
}
1282 
 
1283 
static int
1284 
decode_PTR2op_0 (TIword iw0, disassemble_info *outf)
1285 
{
1286 
  /* PTR2op
1287 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1288 
     | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
1289 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1290 
  int src = ((iw0 >> PTR2op_src_bits) & PTR2op_dst_mask);
1291 
  int opc = ((iw0 >> PTR2op_opc_bits) & PTR2op_opc_mask);
1292 
  int dst = ((iw0 >> PTR2op_dst_bits) & PTR2op_dst_mask);
1293 
 
1294 
  if (opc == 0)
1295 
    {
1296 
      OUTS (outf, pregs (dst));
1297 
      OUTS (outf, "-=");
1298 
      OUTS (outf, pregs (src));
1299 
    }
1300 
  else if (opc == 1)
1301 
    {
1302 
      OUTS (outf, pregs (dst));
1303 
      OUTS (outf, "=");
1304 
      OUTS (outf, pregs (src));
1305 
      OUTS (outf, "<<2");
1306 
    }
1307 
  else if (opc == 3)
1308 
    {
1309 
      OUTS (outf, pregs (dst));
1310 
      OUTS (outf, "=");
1311 
      OUTS (outf, pregs (src));
1312 
      OUTS (outf, ">>2");
1313 
    }
1314 
  else if (opc == 4)
1315 
    {
1316 
      OUTS (outf, pregs (dst));
1317 
      OUTS (outf, "=");
1318 
      OUTS (outf, pregs (src));
1319 
      OUTS (outf, ">>1");
1320 
    }
1321 
  else if (opc == 5)
1322 
    {
1323 
      OUTS (outf, pregs (dst));
1324 
      OUTS (outf, "+=");
1325 
      OUTS (outf, pregs (src));
1326 
      OUTS (outf, "(BREV)");
1327 
    }
1328 
  else if (opc == 6)
1329 
    {
1330 
      OUTS (outf, pregs (dst));
1331 
      OUTS (outf, "=(");
1332 
      OUTS (outf, pregs (dst));
1333 
      OUTS (outf, "+");
1334 
      OUTS (outf, pregs (src));
1335 
      OUTS (outf, ")<<1");
1336 
    }
1337 
  else if (opc == 7)
1338 
    {
1339 
      OUTS (outf, pregs (dst));
1340 
      OUTS (outf, "=(");
1341 
      OUTS (outf, pregs (dst));
1342 
      OUTS (outf, "+");
1343 
      OUTS (outf, pregs (src));
1344 
      OUTS (outf, ")<<2");
1345 
    }
1346 
  else
1347 
    return 0;
1348 
 
1349 
  return 2;
1350 
}
1351 
 
1352 
static int
1353 
decode_LOGI2op_0 (TIword iw0, disassemble_info *outf)
1354 
{
1355 
  /* LOGI2op
1356 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1357 
     | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
1358 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1359 
  int src = ((iw0 >> LOGI2op_src_bits) & LOGI2op_src_mask);
1360 
  int opc = ((iw0 >> LOGI2op_opc_bits) & LOGI2op_opc_mask);
1361 
  int dst = ((iw0 >> LOGI2op_dst_bits) & LOGI2op_dst_mask);
1362 
 
1363 
  if (opc == 0)
1364 
    {
1365 
      OUTS (outf, "CC = ! BITTST (");
1366 
      OUTS (outf, dregs (dst));
1367 
      OUTS (outf, ",");
1368 
      OUTS (outf, uimm5 (src));
1369 
      OUTS (outf, ")");
1370 
    }
1371 
  else if (opc == 1)
1372 
    {
1373 
      OUTS (outf, "CC = BITTST (");
1374 
      OUTS (outf, dregs (dst));
1375 
      OUTS (outf, ",");
1376 
      OUTS (outf, uimm5 (src));
1377 
      OUTS (outf, ")");
1378 
    }
1379 
  else if (opc == 2)
1380 
    {
1381 
      OUTS (outf, "BITSET (");
1382 
      OUTS (outf, dregs (dst));
1383 
      OUTS (outf, ",");
1384 
      OUTS (outf, uimm5 (src));
1385 
      OUTS (outf, ")");
1386 
    }
1387 
  else if (opc == 3)
1388 
    {
1389 
      OUTS (outf, "BITTGL (");
1390 
      OUTS (outf, dregs (dst));
1391 
      OUTS (outf, ",");
1392 
      OUTS (outf, uimm5 (src));
1393 
      OUTS (outf, ")");
1394 
    }
1395 
  else if (opc == 4)
1396 
    {
1397 
      OUTS (outf, "BITCLR (");
1398 
      OUTS (outf, dregs (dst));
1399 
      OUTS (outf, ",");
1400 
      OUTS (outf, uimm5 (src));
1401 
      OUTS (outf, ")");
1402 
    }
1403 
  else if (opc == 5)
1404 
    {
1405 
      OUTS (outf, dregs (dst));
1406 
      OUTS (outf, ">>>=");
1407 
      OUTS (outf, uimm5 (src));
1408 
    }
1409 
  else if (opc == 6)
1410 
    {
1411 
      OUTS (outf, dregs (dst));
1412 
      OUTS (outf, ">>=");
1413 
      OUTS (outf, uimm5 (src));
1414 
    }
1415 
  else if (opc == 7)
1416 
    {
1417 
      OUTS (outf, dregs (dst));
1418 
      OUTS (outf, "<<=");
1419 
      OUTS (outf, uimm5 (src));
1420 
    }
1421 
  else
1422 
    return 0;
1423 
 
1424 
  return 2;
1425 
}
1426 
 
1427 
static int
1428 
decode_COMP3op_0 (TIword iw0, disassemble_info *outf)
1429 
{
1430 
  /* COMP3op
1431 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1432 
     | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1433 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1434 
  int opc  = ((iw0 >> COMP3op_opc_bits) & COMP3op_opc_mask);
1435 
  int dst  = ((iw0 >> COMP3op_dst_bits) & COMP3op_dst_mask);
1436 
  int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask);
1437 
  int src1 = ((iw0 >> COMP3op_src1_bits) & COMP3op_src1_mask);
1438 
 
1439 
  if (opc == 5 && src1 == src0)
1440 
    {
1441 
      OUTS (outf, pregs (dst));
1442 
      OUTS (outf, "=");
1443 
      OUTS (outf, pregs (src0));
1444 
      OUTS (outf, "<<1");
1445 
    }
1446 
  else if (opc == 1)
1447 
    {
1448 
      OUTS (outf, dregs (dst));
1449 
      OUTS (outf, "=");
1450 
      OUTS (outf, dregs (src0));
1451 
      OUTS (outf, "-");
1452 
      OUTS (outf, dregs (src1));
1453 
    }
1454 
  else if (opc == 2)
1455 
    {
1456 
      OUTS (outf, dregs (dst));
1457 
      OUTS (outf, "=");
1458 
      OUTS (outf, dregs (src0));
1459 
      OUTS (outf, "&");
1460 
      OUTS (outf, dregs (src1));
1461 
    }
1462 
  else if (opc == 3)
1463 
    {
1464 
      OUTS (outf, dregs (dst));
1465 
      OUTS (outf, "=");
1466 
      OUTS (outf, dregs (src0));
1467 
      OUTS (outf, "|");
1468 
      OUTS (outf, dregs (src1));
1469 
    }
1470 
  else if (opc == 4)
1471 
    {
1472 
      OUTS (outf, dregs (dst));
1473 
      OUTS (outf, "=");
1474 
      OUTS (outf, dregs (src0));
1475 
      OUTS (outf, "^");
1476 
      OUTS (outf, dregs (src1));
1477 
    }
1478 
  else if (opc == 5)
1479 
    {
1480 
      OUTS (outf, pregs (dst));
1481 
      OUTS (outf, "=");
1482 
      OUTS (outf, pregs (src0));
1483 
      OUTS (outf, "+");
1484 
      OUTS (outf, pregs (src1));
1485 
    }
1486 
  else if (opc == 6)
1487 
    {
1488 
      OUTS (outf, pregs (dst));
1489 
      OUTS (outf, "=");
1490 
      OUTS (outf, pregs (src0));
1491 
      OUTS (outf, "+(");
1492 
      OUTS (outf, pregs (src1));
1493 
      OUTS (outf, "<<1)");
1494 
    }
1495 
  else if (opc == 7)
1496 
    {
1497 
      OUTS (outf, pregs (dst));
1498 
      OUTS (outf, "=");
1499 
      OUTS (outf, pregs (src0));
1500 
      OUTS (outf, "+(");
1501 
      OUTS (outf, pregs (src1));
1502 
      OUTS (outf, "<<2)");
1503 
    }
1504 
  else if (opc == 0)
1505 
    {
1506 
      OUTS (outf, dregs (dst));
1507 
      OUTS (outf, "=");
1508 
      OUTS (outf, dregs (src0));
1509 
      OUTS (outf, "+");
1510 
      OUTS (outf, dregs (src1));
1511 
    }
1512 
  else
1513 
    return 0;
1514 
 
1515 
  return 2;
1516 
}
1517 
 
1518 
static int
1519 
decode_COMPI2opD_0 (TIword iw0, disassemble_info *outf)
1520 
{
1521 
  /* COMPI2opD
1522 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1523 
     | 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......|
1524 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1525 
  int op  = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask);
1526 
  int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask);
1527 
  int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask);
1528 
 
1529 
  if (op == 0)
1530 
    {
1531 
      OUTS (outf, dregs (dst));
1532 
      OUTS (outf, "=");
1533 
      OUTS (outf, imm7 (src));
1534 
      OUTS (outf, "(x)");
1535 
    }
1536 
  else if (op == 1)
1537 
    {
1538 
      OUTS (outf, dregs (dst));
1539 
      OUTS (outf, "+=");
1540 
      OUTS (outf, imm7 (src));
1541 
    }
1542 
  else
1543 
    return 0;
1544 
 
1545 
  return 2;
1546 
}
1547 
 
1548 
static int
1549 
decode_COMPI2opP_0 (TIword iw0, disassemble_info *outf)
1550 
{
1551 
  /* COMPI2opP
1552 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1553 
     | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
1554 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1555 
  int op  = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask);
1556 
  int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask);
1557 
  int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask);
1558 
 
1559 
  if (op == 0)
1560 
    {
1561 
      OUTS (outf, pregs (dst));
1562 
      OUTS (outf, "=");
1563 
      OUTS (outf, imm7 (src));
1564 
    }
1565 
  else if (op == 1)
1566 
    {
1567 
      OUTS (outf, pregs (dst));
1568 
      OUTS (outf, "+=");
1569 
      OUTS (outf, imm7 (src));
1570 
    }
1571 
  else
1572 
    return 0;
1573 
 
1574 
  return 2;
1575 
}
1576 
 
1577 
static int
1578 
decode_LDSTpmod_0 (TIword iw0, disassemble_info *outf)
1579 
{
1580 
  /* LDSTpmod
1581 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1582 
     | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
1583 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1584 
  int W   = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask);
1585 
  int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask);
1586 
  int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask);
1587 
  int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask);
1588 
  int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask);
1589 
 
1590 
  if (aop == 1 && W == 0 && idx == ptr)
1591 
    {
1592 
      OUTS (outf, dregs_lo (reg));
1593 
      OUTS (outf, "=W[");
1594 
      OUTS (outf, pregs (ptr));
1595 
      OUTS (outf, "]");
1596 
    }
1597 
  else if (aop == 2 && W == 0 && idx == ptr)
1598 
    {
1599 
      OUTS (outf, dregs_hi (reg));
1600 
      OUTS (outf, "=W[");
1601 
      OUTS (outf, pregs (ptr));
1602 
      OUTS (outf, "]");
1603 
    }
1604 
  else if (aop == 1 && W == 1 && idx == ptr)
1605 
    {
1606 
      OUTS (outf, "W[");
1607 
      OUTS (outf, pregs (ptr));
1608 
      OUTS (outf, "]=");
1609 
      OUTS (outf, dregs_lo (reg));
1610 
    }
1611 
  else if (aop == 2 && W == 1 && idx == ptr)
1612 
    {
1613 
      OUTS (outf, "W[");
1614 
      OUTS (outf, pregs (ptr));
1615 
      OUTS (outf, "]=");
1616 
      OUTS (outf, dregs_hi (reg));
1617 
    }
1618 
  else if (aop == 0 && W == 0)
1619 
    {
1620 
      OUTS (outf, dregs (reg));
1621 
      OUTS (outf, "=[");
1622 
      OUTS (outf, pregs (ptr));
1623 
      OUTS (outf, "++");
1624 
      OUTS (outf, pregs (idx));
1625 
      OUTS (outf, "]");
1626 
    }
1627 
  else if (aop == 1 && W == 0)
1628 
    {
1629 
      OUTS (outf, dregs_lo (reg));
1630 
      OUTS (outf, "=W[");
1631 
      OUTS (outf, pregs (ptr));
1632 
      OUTS (outf, "++");
1633 
      OUTS (outf, pregs (idx));
1634 
      OUTS (outf, "]");
1635 
    }
1636 
  else if (aop == 2 && W == 0)
1637 
    {
1638 
      OUTS (outf, dregs_hi (reg));
1639 
      OUTS (outf, "=W[");
1640 
      OUTS (outf, pregs (ptr));
1641 
      OUTS (outf, "++");
1642 
      OUTS (outf, pregs (idx));
1643 
      OUTS (outf, "]");
1644 
    }
1645 
  else if (aop == 3 && W == 0)
1646 
    {
1647 
      OUTS (outf, dregs (reg));
1648 
      OUTS (outf, "=W[");
1649 
      OUTS (outf, pregs (ptr));
1650 
      OUTS (outf, "++");
1651 
      OUTS (outf, pregs (idx));
1652 
      OUTS (outf, "] (Z)");
1653 
    }
1654 
  else if (aop == 3 && W == 1)
1655 
    {
1656 
      OUTS (outf, dregs (reg));
1657 
      OUTS (outf, "=W[");
1658 
      OUTS (outf, pregs (ptr));
1659 
      OUTS (outf, "++");
1660 
      OUTS (outf, pregs (idx));
1661 
      OUTS (outf, "](X)");
1662 
    }
1663 
  else if (aop == 0 && W == 1)
1664 
    {
1665 
      OUTS (outf, "[");
1666 
      OUTS (outf, pregs (ptr));
1667 
      OUTS (outf, "++");
1668 
      OUTS (outf, pregs (idx));
1669 
      OUTS (outf, "]=");
1670 
      OUTS (outf, dregs (reg));
1671 
    }
1672 
  else if (aop == 1 && W == 1)
1673 
    {
1674 
      OUTS (outf, "W[");
1675 
      OUTS (outf, pregs (ptr));
1676 
      OUTS (outf, "++");
1677 
      OUTS (outf, pregs (idx));
1678 
      OUTS (outf, "]=");
1679 
      OUTS (outf, dregs_lo (reg));
1680 
    }
1681 
  else if (aop == 2 && W == 1)
1682 
    {
1683 
      OUTS (outf, "W[");
1684 
      OUTS (outf, pregs (ptr));
1685 
      OUTS (outf, "++");
1686 
      OUTS (outf, pregs (idx));
1687 
      OUTS (outf, "]=");
1688 
      OUTS (outf, dregs_hi (reg));
1689 
    }
1690 
  else
1691 
    return 0;
1692 
 
1693 
  return 2;
1694 
}
1695 
 
1696 
static int
1697 
decode_dagMODim_0 (TIword iw0, disassemble_info *outf)
1698 
{
1699 
  /* dagMODim
1700 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1701 
     | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
1702 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1703 
  int i  = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask);
1704 
  int m  = ((iw0 >> DagMODim_m_bits) & DagMODim_m_mask);
1705 
  int br = ((iw0 >> DagMODim_br_bits) & DagMODim_br_mask);
1706 
  int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask);
1707 
 
1708 
  if (op == 0 && br == 1)
1709 
    {
1710 
      OUTS (outf, iregs (i));
1711 
      OUTS (outf, "+=");
1712 
      OUTS (outf, mregs (m));
1713 
      OUTS (outf, "(BREV)");
1714 
    }
1715 
  else if (op == 0)
1716 
    {
1717 
      OUTS (outf, iregs (i));
1718 
      OUTS (outf, "+=");
1719 
      OUTS (outf, mregs (m));
1720 
    }
1721 
  else if (op == 1)
1722 
    {
1723 
      OUTS (outf, iregs (i));
1724 
      OUTS (outf, "-=");
1725 
      OUTS (outf, mregs (m));
1726 
    }
1727 
  else
1728 
    return 0;
1729 
 
1730 
  return 2;
1731 
}
1732 
 
1733 
static int
1734 
decode_dagMODik_0 (TIword iw0, disassemble_info *outf)
1735 
{
1736 
  /* dagMODik
1737 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1738 
     | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
1739 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1740 
  int i  = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask);
1741 
  int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask);
1742 
 
1743 
  if (op == 0)
1744 
    {
1745 
      OUTS (outf, iregs (i));
1746 
      OUTS (outf, "+=2");
1747 
    }
1748 
  else if (op == 1)
1749 
    {
1750 
      OUTS (outf, iregs (i));
1751 
      OUTS (outf, "-=2");
1752 
    }
1753 
  else if (op == 2)
1754 
    {
1755 
      OUTS (outf, iregs (i));
1756 
      OUTS (outf, "+=4");
1757 
    }
1758 
  else if (op == 3)
1759 
    {
1760 
      OUTS (outf, iregs (i));
1761 
      OUTS (outf, "-=4");
1762 
    }
1763 
  else
1764 
    return 0;
1765 
 
1766 
  return 2;
1767 
}
1768 
 
1769 
static int
1770 
decode_dspLDST_0 (TIword iw0, disassemble_info *outf)
1771 
{
1772 
  /* dspLDST
1773 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1774 
     | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
1775 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1776 
  int i   = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask);
1777 
  int m   = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask);
1778 
  int W   = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask);
1779 
  int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask);
1780 
  int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask);
1781 
 
1782 
  if (aop == 0 && W == 0 && m == 0)
1783 
    {
1784 
      OUTS (outf, dregs (reg));
1785 
      OUTS (outf, "=[");
1786 
      OUTS (outf, iregs (i));
1787 
      OUTS (outf, "++]");
1788 
    }
1789 
  else if (aop == 0 && W == 0 && m == 1)
1790 
    {
1791 
      OUTS (outf, dregs_lo (reg));
1792 
      OUTS (outf, "=W[");
1793 
      OUTS (outf, iregs (i));
1794 
      OUTS (outf, "++]");
1795 
    }
1796 
  else if (aop == 0 && W == 0 && m == 2)
1797 
    {
1798 
      OUTS (outf, dregs_hi (reg));
1799 
      OUTS (outf, "=W[");
1800 
      OUTS (outf, iregs (i));
1801 
      OUTS (outf, "++]");
1802 
    }
1803 
  else if (aop == 1 && W == 0 && m == 0)
1804 
    {
1805 
      OUTS (outf, dregs (reg));
1806 
      OUTS (outf, "=[");
1807 
      OUTS (outf, iregs (i));
1808 
      OUTS (outf, "--]");
1809 
    }
1810 
  else if (aop == 1 && W == 0 && m == 1)
1811 
    {
1812 
      OUTS (outf, dregs_lo (reg));
1813 
      OUTS (outf, "=W[");
1814 
      OUTS (outf, iregs (i));
1815 
      OUTS (outf, "--]");
1816 
    }
1817 
  else if (aop == 1 && W == 0 && m == 2)
1818 
    {
1819 
      OUTS (outf, dregs_hi (reg));
1820 
      OUTS (outf, "=W[");
1821 
      OUTS (outf, iregs (i));
1822 
      OUTS (outf, "--]");
1823 
    }
1824 
  else if (aop == 2 && W == 0 && m == 0)
1825 
    {
1826 
      OUTS (outf, dregs (reg));
1827 
      OUTS (outf, "=[");
1828 
      OUTS (outf, iregs (i));
1829 
      OUTS (outf, "]");
1830 
    }
1831 
  else if (aop == 2 && W == 0 && m == 1)
1832 
    {
1833 
      OUTS (outf, dregs_lo (reg));
1834 
      OUTS (outf, "=W[");
1835 
      OUTS (outf, iregs (i));
1836 
      OUTS (outf, "]");
1837 
    }
1838 
  else if (aop == 2 && W == 0 && m == 2)
1839 
    {
1840 
      OUTS (outf, dregs_hi (reg));
1841 
      OUTS (outf, "=W[");
1842 
      OUTS (outf, iregs (i));
1843 
      OUTS (outf, "]");
1844 
    }
1845 
  else if (aop == 0 && W == 1 && m == 0)
1846 
    {
1847 
      OUTS (outf, "[");
1848 
      OUTS (outf, iregs (i));
1849 
      OUTS (outf, "++]=");
1850 
      OUTS (outf, dregs (reg));
1851 
    }
1852 
  else if (aop == 0 && W == 1 && m == 1)
1853 
    {
1854 
      OUTS (outf, "W[");
1855 
      OUTS (outf, iregs (i));
1856 
      OUTS (outf, "++]=");
1857 
      OUTS (outf, dregs_lo (reg));
1858 
    }
1859 
  else if (aop == 0 && W == 1 && m == 2)
1860 
    {
1861 
      OUTS (outf, "W[");
1862 
      OUTS (outf, iregs (i));
1863 
      OUTS (outf, "++]=");
1864 
      OUTS (outf, dregs_hi (reg));
1865 
    }
1866 
  else if (aop == 1 && W == 1 && m == 0)
1867 
    {
1868 
      OUTS (outf, "[");
1869 
      OUTS (outf, iregs (i));
1870 
      OUTS (outf, "--]=");
1871 
      OUTS (outf, dregs (reg));
1872 
    }
1873 
  else if (aop == 1 && W == 1 && m == 1)
1874 
    {
1875 
      OUTS (outf, "W[");
1876 
      OUTS (outf, iregs (i));
1877 
      OUTS (outf, "--]=");
1878 
      OUTS (outf, dregs_lo (reg));
1879 
    }
1880 
  else if (aop == 1 && W == 1 && m == 2)
1881 
    {
1882 
      OUTS (outf, "W[");
1883 
      OUTS (outf, iregs (i));
1884 
      OUTS (outf, "--]=");
1885 
      OUTS (outf, dregs_hi (reg));
1886 
    }
1887 
  else if (aop == 2 && W == 1 && m == 0)
1888 
    {
1889 
      OUTS (outf, "[");
1890 
      OUTS (outf, iregs (i));
1891 
      OUTS (outf, "]=");
1892 
      OUTS (outf, dregs (reg));
1893 
    }
1894 
  else if (aop == 2 && W == 1 && m == 1)
1895 
    {
1896 
      OUTS (outf, "W[");
1897 
      OUTS (outf, iregs (i));
1898 
      OUTS (outf, "]=");
1899 
      OUTS (outf, dregs_lo (reg));
1900 
    }
1901 
  else if (aop == 2 && W == 1 && m == 2)
1902 
    {
1903 
      OUTS (outf, "W[");
1904 
      OUTS (outf, iregs (i));
1905 
      OUTS (outf, "]=");
1906 
      OUTS (outf, dregs_hi (reg));
1907 
    }
1908 
  else if (aop == 3 && W == 0)
1909 
    {
1910 
      OUTS (outf, dregs (reg));
1911 
      OUTS (outf, "=[");
1912 
      OUTS (outf, iregs (i));
1913 
      OUTS (outf, "++");
1914 
      OUTS (outf, mregs (m));
1915 
      OUTS (outf, "]");
1916 
    }
1917 
  else if (aop == 3 && W == 1)
1918 
    {
1919 
      OUTS (outf, "[");
1920 
      OUTS (outf, iregs (i));
1921 
      OUTS (outf, "++");
1922 
      OUTS (outf, mregs (m));
1923 
      OUTS (outf, "]=");
1924 
      OUTS (outf, dregs (reg));
1925 
    }
1926 
  else
1927 
    return 0;
1928 
 
1929 
  return 2;
1930 
}
1931 
 
1932 
static int
1933 
decode_LDST_0 (TIword iw0, disassemble_info *outf)
1934 
{
1935 
  /* LDST
1936 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1937 
     | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
1938 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1939 
  int Z   = ((iw0 >> LDST_Z_bits) & LDST_Z_mask);
1940 
  int W   = ((iw0 >> LDST_W_bits) & LDST_W_mask);
1941 
  int sz  = ((iw0 >> LDST_sz_bits) & LDST_sz_mask);
1942 
  int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask);
1943 
  int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask);
1944 
  int ptr = ((iw0 >> LDST_ptr_bits) & LDST_ptr_mask);
1945 
 
1946 
  if (aop == 0 && sz == 0 && Z == 0 && W == 0)
1947 
    {
1948 
      OUTS (outf, dregs (reg));
1949 
      OUTS (outf, "=[");
1950 
      OUTS (outf, pregs (ptr));
1951 
      OUTS (outf, "++]");
1952 
    }
1953 
  else if (aop == 0 && sz == 0 && Z == 1 && W == 0)
1954 
    {
1955 
      OUTS (outf, pregs (reg));
1956 
      OUTS (outf, "=[");
1957 
      OUTS (outf, pregs (ptr));
1958 
      OUTS (outf, "++]");
1959 
    }
1960 
  else if (aop == 0 && sz == 1 && Z == 0 && W == 0)
1961 
    {
1962 
      OUTS (outf, dregs (reg));
1963 
      OUTS (outf, "=W[");
1964 
      OUTS (outf, pregs (ptr));
1965 
      OUTS (outf, "++] (Z)");
1966 
    }
1967 
  else if (aop == 0 && sz == 1 && Z == 1 && W == 0)
1968 
    {
1969 
      OUTS (outf, dregs (reg));
1970 
      OUTS (outf, "=W[");
1971 
      OUTS (outf, pregs (ptr));
1972 
      OUTS (outf, "++](X)");
1973 
    }
1974 
  else if (aop == 0 && sz == 2 && Z == 0 && W == 0)
1975 
    {
1976 
      OUTS (outf, dregs (reg));
1977 
      OUTS (outf, "=B[");
1978 
      OUTS (outf, pregs (ptr));
1979 
      OUTS (outf, "++] (Z)");
1980 
    }
1981 
  else if (aop == 0 && sz == 2 && Z == 1 && W == 0)
1982 
    {
1983 
      OUTS (outf, dregs (reg));
1984 
      OUTS (outf, "=B[");
1985 
      OUTS (outf, pregs (ptr));
1986 
      OUTS (outf, "++](X)");
1987 
    }
1988 
  else if (aop == 1 && sz == 0 && Z == 0 && W == 0)
1989 
    {
1990 
      OUTS (outf, dregs (reg));
1991 
      OUTS (outf, "=[");
1992 
      OUTS (outf, pregs (ptr));
1993 
      OUTS (outf, "--]");
1994 
    }
1995 
  else if (aop == 1 && sz == 0 && Z == 1 && W == 0)
1996 
    {
1997 
      OUTS (outf, pregs (reg));
1998 
      OUTS (outf, "=[");
1999 
      OUTS (outf, pregs (ptr));
2000 
      OUTS (outf, "--]");
2001 
    }
2002 
  else if (aop == 1 && sz == 1 && Z == 0 && W == 0)
2003 
    {
2004 
      OUTS (outf, dregs (reg));
2005 
      OUTS (outf, "=W[");
2006 
      OUTS (outf, pregs (ptr));
2007 
      OUTS (outf, "--] (Z)");
2008 
    }
2009 
  else if (aop == 1 && sz == 1 && Z == 1 && W == 0)
2010 
    {
2011 
      OUTS (outf, dregs (reg));
2012 
      OUTS (outf, "=W[");
2013 
      OUTS (outf, pregs (ptr));
2014 
      OUTS (outf, "--](X)");
2015 
    }
2016 
  else if (aop == 1 && sz == 2 && Z == 0 && W == 0)
2017 
    {
2018 
      OUTS (outf, dregs (reg));
2019 
      OUTS (outf, "=B[");
2020 
      OUTS (outf, pregs (ptr));
2021 
      OUTS (outf, "--] (Z)");
2022 
    }
2023 
  else if (aop == 1 && sz == 2 && Z == 1 && W == 0)
2024 
    {
2025 
      OUTS (outf, dregs (reg));
2026 
      OUTS (outf, "=B[");
2027 
      OUTS (outf, pregs (ptr));
2028 
      OUTS (outf, "--](X)");
2029 
    }
2030 
  else if (aop == 2 && sz == 0 && Z == 0 && W == 0)
2031 
    {
2032 
      OUTS (outf, dregs (reg));
2033 
      OUTS (outf, "=[");
2034 
      OUTS (outf, pregs (ptr));
2035 
      OUTS (outf, "]");
2036 
    }
2037 
  else if (aop == 2 && sz == 0 && Z == 1 && W == 0)
2038 
    {
2039 
      OUTS (outf, pregs (reg));
2040 
      OUTS (outf, "=[");
2041 
      OUTS (outf, pregs (ptr));
2042 
      OUTS (outf, "]");
2043 
    }
2044 
  else if (aop == 2 && sz == 1 && Z == 0 && W == 0)
2045 
    {
2046 
      OUTS (outf, dregs (reg));
2047 
      OUTS (outf, "=W[");
2048 
      OUTS (outf, pregs (ptr));
2049 
      OUTS (outf, "] (Z)");
2050 
    }
2051 
  else if (aop == 2 && sz == 1 && Z == 1 && W == 0)
2052 
    {
2053 
      OUTS (outf, dregs (reg));
2054 
      OUTS (outf, "=W[");
2055 
      OUTS (outf, pregs (ptr));
2056 
      OUTS (outf, "](X)");
2057 
    }
2058 
  else if (aop == 2 && sz == 2 && Z == 0 && W == 0)
2059 
    {
2060 
      OUTS (outf, dregs (reg));
2061 
      OUTS (outf, "=B[");
2062 
      OUTS (outf, pregs (ptr));
2063 
      OUTS (outf, "] (Z)");
2064 
    }
2065 
  else if (aop == 2 && sz == 2 && Z == 1 && W == 0)
2066 
    {
2067 
      OUTS (outf, dregs (reg));
2068 
      OUTS (outf, "=B[");
2069 
      OUTS (outf, pregs (ptr));
2070 
      OUTS (outf, "](X)");
2071 
    }
2072 
  else if (aop == 0 && sz == 0 && Z == 0 && W == 1)
2073 
    {
2074 
      OUTS (outf, "[");
2075 
      OUTS (outf, pregs (ptr));
2076 
      OUTS (outf, "++]=");
2077 
      OUTS (outf, dregs (reg));
2078 
    }
2079 
  else if (aop == 0 && sz == 0 && Z == 1 && W == 1)
2080 
    {
2081 
      OUTS (outf, "[");
2082 
      OUTS (outf, pregs (ptr));
2083 
      OUTS (outf, "++]=");
2084 
      OUTS (outf, pregs (reg));
2085 
    }
2086 
  else if (aop == 0 && sz == 1 && Z == 0 && W == 1)
2087 
    {
2088 
      OUTS (outf, "W[");
2089 
      OUTS (outf, pregs (ptr));
2090 
      OUTS (outf, "++]=");
2091 
      OUTS (outf, dregs (reg));
2092 
    }
2093 
  else if (aop == 0 && sz == 2 && Z == 0 && W == 1)
2094 
    {
2095 
      OUTS (outf, "B[");
2096 
      OUTS (outf, pregs (ptr));
2097 
      OUTS (outf, "++]=");
2098 
      OUTS (outf, dregs (reg));
2099 
    }
2100 
  else if (aop == 1 && sz == 0 && Z == 0 && W == 1)
2101 
    {
2102 
      OUTS (outf, "[");
2103 
      OUTS (outf, pregs (ptr));
2104 
      OUTS (outf, "--]=");
2105 
      OUTS (outf, dregs (reg));
2106 
    }
2107 
  else if (aop == 1 && sz == 0 && Z == 1 && W == 1)
2108 
    {
2109 
      OUTS (outf, "[");
2110 
      OUTS (outf, pregs (ptr));
2111 
      OUTS (outf, "--]=");
2112 
      OUTS (outf, pregs (reg));
2113 
    }
2114 
  else if (aop == 1 && sz == 1 && Z == 0 && W == 1)
2115 
    {
2116 
      OUTS (outf, "W[");
2117 
      OUTS (outf, pregs (ptr));
2118 
      OUTS (outf, "--]=");
2119 
      OUTS (outf, dregs (reg));
2120 
    }
2121 
  else if (aop == 1 && sz == 2 && Z == 0 && W == 1)
2122 
    {
2123 
      OUTS (outf, "B[");
2124 
      OUTS (outf, pregs (ptr));
2125 
      OUTS (outf, "--]=");
2126 
      OUTS (outf, dregs (reg));
2127 
    }
2128 
  else if (aop == 2 && sz == 0 && Z == 0 && W == 1)
2129 
    {
2130 
      OUTS (outf, "[");
2131 
      OUTS (outf, pregs (ptr));
2132 
      OUTS (outf, "]=");
2133 
      OUTS (outf, dregs (reg));
2134 
    }
2135 
  else if (aop == 2 && sz == 0 && Z == 1 && W == 1)
2136 
    {
2137 
      OUTS (outf, "[");
2138 
      OUTS (outf, pregs (ptr));
2139 
      OUTS (outf, "]=");
2140 
      OUTS (outf, pregs (reg));
2141 
    }
2142 
  else if (aop == 2 && sz == 1 && Z == 0 && W == 1)
2143 
    {
2144 
      OUTS (outf, "W[");
2145 
      OUTS (outf, pregs (ptr));
2146 
      OUTS (outf, "]=");
2147 
      OUTS (outf, dregs (reg));
2148 
    }
2149 
  else if (aop == 2 && sz == 2 && Z == 0 && W == 1)
2150 
    {
2151 
      OUTS (outf, "B[");
2152 
      OUTS (outf, pregs (ptr));
2153 
      OUTS (outf, "]=");
2154 
      OUTS (outf, dregs (reg));
2155 
    }
2156 
  else
2157 
    return 0;
2158 
 
2159 
  return 2;
2160 
}
2161 
 
2162 
static int
2163 
decode_LDSTiiFP_0 (TIword iw0, disassemble_info *outf)
2164 
{
2165 
  /* LDSTiiFP
2166 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2167 
     | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
2168 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2169 
  int reg = ((iw0 >> LDSTiiFP_reg_bits) & LDSTiiFP_reg_mask);
2170 
  int offset = ((iw0 >> LDSTiiFP_offset_bits) & LDSTiiFP_offset_mask);
2171 
  int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask);
2172 
 
2173 
  if (W == 0)
2174 
    {
2175 
      OUTS (outf, dpregs (reg));
2176 
      OUTS (outf, "=[FP");
2177 
      OUTS (outf, negimm5s4 (offset));
2178 
      OUTS (outf, "]");
2179 
    }
2180 
  else if (W == 1)
2181 
    {
2182 
      OUTS (outf, "[FP");
2183 
      OUTS (outf, negimm5s4 (offset));
2184 
      OUTS (outf, "]=");
2185 
      OUTS (outf, dpregs (reg));
2186 
    }
2187 
  else
2188 
    return 0;
2189 
 
2190 
  return 2;
2191 
}
2192 
 
2193 
static int
2194 
decode_LDSTii_0 (TIword iw0, disassemble_info *outf)
2195 
{
2196 
  /* LDSTii
2197 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2198 
     | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
2199 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2200 
  int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask);
2201 
  int ptr = ((iw0 >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
2202 
  int offset = ((iw0 >> LDSTii_offset_bit) & LDSTii_offset_mask);
2203 
  int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask);
2204 
  int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask);
2205 
 
2206 
  if (W == 0 && op == 0)
2207 
    {
2208 
      OUTS (outf, dregs (reg));
2209 
      OUTS (outf, "=[");
2210 
      OUTS (outf, pregs (ptr));
2211 
      OUTS (outf, "+");
2212 
      OUTS (outf, uimm4s4 (offset));
2213 
      OUTS (outf, "]");
2214 
    }
2215 
  else if (W == 0 && op == 1)
2216 
    {
2217 
      OUTS (outf, dregs (reg));
2218 
      OUTS (outf, "=W[");
2219 
      OUTS (outf, pregs (ptr));
2220 
      OUTS (outf, "+");
2221 
      OUTS (outf, uimm4s2 (offset));
2222 
      OUTS (outf, "] (Z)");
2223 
    }
2224 
  else if (W == 0 && op == 2)
2225 
    {
2226 
      OUTS (outf, dregs (reg));
2227 
      OUTS (outf, "=W[");
2228 
      OUTS (outf, pregs (ptr));
2229 
      OUTS (outf, "+");
2230 
      OUTS (outf, uimm4s2 (offset));
2231 
      OUTS (outf, "](X)");
2232 
    }
2233 
  else if (W == 0 && op == 3)
2234 
    {
2235 
      OUTS (outf, pregs (reg));
2236 
      OUTS (outf, "=[");
2237 
      OUTS (outf, pregs (ptr));
2238 
      OUTS (outf, "+");
2239 
      OUTS (outf, uimm4s4 (offset));
2240 
      OUTS (outf, "]");
2241 
    }
2242 
  else if (W == 1 && op == 0)
2243 
    {
2244 
      OUTS (outf, "[");
2245 
      OUTS (outf, pregs (ptr));
2246 
      OUTS (outf, "+");
2247 
      OUTS (outf, uimm4s4 (offset));
2248 
      OUTS (outf, "]=");
2249 
      OUTS (outf, dregs (reg));
2250 
    }
2251 
  else if (W == 1 && op == 1)
2252 
    {
2253 
      OUTS (outf, "W");
2254 
      OUTS (outf, "[");
2255 
      OUTS (outf, pregs (ptr));
2256 
      OUTS (outf, "+");
2257 
      OUTS (outf, uimm4s2 (offset));
2258 
      OUTS (outf, "]");
2259 
      OUTS (outf, "=");
2260 
      OUTS (outf, dregs (reg));
2261 
    }
2262 
  else if (W == 1 && op == 3)
2263 
    {
2264 
      OUTS (outf, "[");
2265 
      OUTS (outf, pregs (ptr));
2266 
      OUTS (outf, "+");
2267 
      OUTS (outf, uimm4s4 (offset));
2268 
      OUTS (outf, "]=");
2269 
      OUTS (outf, pregs (reg));
2270 
    }
2271 
  else
2272 
    return 0;
2273 
 
2274 
  return 2;
2275 
}
2276 
 
2277 
static int
2278 
decode_LoopSetup_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2279 
{
2280 
  /* LoopSetup
2281 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2282 
     | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
2283 
     |.reg...........| - | - |.eoffset...............................|
2284 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2285 
  int c   = ((iw0 >> (LoopSetup_c_bits - 16)) & LoopSetup_c_mask);
2286 
  int reg = ((iw1 >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
2287 
  int rop = ((iw0 >> (LoopSetup_rop_bits - 16)) & LoopSetup_rop_mask);
2288 
  int soffset = ((iw0 >> (LoopSetup_soffset_bits - 16)) & LoopSetup_soffset_mask);
2289 
  int eoffset = ((iw1 >> LoopSetup_eoffset_bits) & LoopSetup_eoffset_mask);
2290 
 
2291 
  if (rop == 0)
2292 
    {
2293 
      OUTS (outf, "LSETUP");
2294 
      OUTS (outf, "(");
2295 
      OUTS (outf, pcrel4 (soffset));
2296 
      OUTS (outf, ",");
2297 
      OUTS (outf, lppcrel10 (eoffset));
2298 
      OUTS (outf, ")");
2299 
      OUTS (outf, counters (c));
2300 
    }
2301 
  else if (rop == 1)
2302 
    {
2303 
      OUTS (outf, "LSETUP");
2304 
      OUTS (outf, "(");
2305 
      OUTS (outf, pcrel4 (soffset));
2306 
      OUTS (outf, ",");
2307 
      OUTS (outf, lppcrel10 (eoffset));
2308 
      OUTS (outf, ")");
2309 
      OUTS (outf, counters (c));
2310 
      OUTS (outf, "=");
2311 
      OUTS (outf, pregs (reg));
2312 
    }
2313 
  else if (rop == 3)
2314 
    {
2315 
      OUTS (outf, "LSETUP");
2316 
      OUTS (outf, "(");
2317 
      OUTS (outf, pcrel4 (soffset));
2318 
      OUTS (outf, ",");
2319 
      OUTS (outf, lppcrel10 (eoffset));
2320 
      OUTS (outf, ")");
2321 
      OUTS (outf, counters (c));
2322 
      OUTS (outf, "=");
2323 
      OUTS (outf, pregs (reg));
2324 
      OUTS (outf, ">>1");
2325 
    }
2326 
  else
2327 
    return 0;
2328 
 
2329 
  return 4;
2330 
}
2331 
 
2332 
static int
2333 
decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2334 
{
2335 
  /* LDIMMhalf
2336 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2337 
     | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
2338 
     |.hword.........................................................|
2339 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2340 
  int H = ((iw0 >> (LDIMMhalf_H_bits - 16)) & LDIMMhalf_H_mask);
2341 
  int Z = ((iw0 >> (LDIMMhalf_Z_bits - 16)) & LDIMMhalf_Z_mask);
2342 
  int S = ((iw0 >> (LDIMMhalf_S_bits - 16)) & LDIMMhalf_S_mask);
2343 
  int reg = ((iw0 >> (LDIMMhalf_reg_bits - 16)) & LDIMMhalf_reg_mask);
2344 
  int grp = ((iw0 >> (LDIMMhalf_grp_bits - 16)) & LDIMMhalf_grp_mask);
2345 
  int hword = ((iw1 >> LDIMMhalf_hword_bits) & LDIMMhalf_hword_mask);
2346 
 
2347 
  if (grp == 0 && H == 0 && S == 0 && Z == 0)
2348 
    {
2349 
      OUTS (outf, dregs_lo (reg));
2350 
      OUTS (outf, "=");
2351 
      OUTS (outf, imm16 (hword));
2352 
    }
2353 
  else if (grp == 0 && H == 1 && S == 0 && Z == 0)
2354 
    {
2355 
      OUTS (outf, dregs_hi (reg));
2356 
      OUTS (outf, "=");
2357 
      OUTS (outf, imm16 (hword));
2358 
    }
2359 
  else if (grp == 0 && H == 0 && S == 1 && Z == 0)
2360 
    {
2361 
      OUTS (outf, dregs (reg));
2362 
      OUTS (outf, "=");
2363 
      OUTS (outf, imm16 (hword));
2364 
      OUTS (outf, " (X)");
2365 
    }
2366 
  else if (H == 0 && S == 1 && Z == 0)
2367 
    {
2368 
      OUTS (outf, regs (reg, grp));
2369 
      OUTS (outf, "=");
2370 
      OUTS (outf, imm16 (hword));
2371 
      OUTS (outf, " (X)");
2372 
    }
2373 
  else if (H == 0 && S == 0 && Z == 1)
2374 
    {
2375 
      OUTS (outf, regs (reg, grp));
2376 
      OUTS (outf, "=");
2377 
      OUTS (outf, luimm16 (hword));
2378 
      OUTS (outf, "(Z)");
2379 
    }
2380 
  else if (H == 0 && S == 0 && Z == 0)
2381 
    {
2382 
      OUTS (outf, regs_lo (reg, grp));
2383 
      OUTS (outf, "=");
2384 
      OUTS (outf, luimm16 (hword));
2385 
    }
2386 
  else if (H == 1 && S == 0 && Z == 0)
2387 
    {
2388 
      OUTS (outf, regs_hi (reg, grp));
2389 
      OUTS (outf, "=");
2390 
      OUTS (outf, huimm16 (hword));
2391 
    }
2392 
  else
2393 
    return 0;
2394 
 
2395 
  return 4;
2396 
}
2397 
 
2398 
static int
2399 
decode_CALLa_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2400 
{
2401 
  /* CALLa
2402 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2403 
     | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
2404 
     |.lsw...........................................................|
2405 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2406 
  int S   = ((iw0 >> (CALLa_S_bits - 16)) & CALLa_S_mask);
2407 
  int lsw = ((iw1 >> 0) & 0xffff);
2408 
  int msw = ((iw0 >> 0) & 0xff);
2409 
 
2410 
  if (S == 1)
2411 
    OUTS (outf, "CALL  ");
2412 
  else if (S == 0)
2413 
    OUTS (outf, "JUMP.L  ");
2414 
  else
2415 
    return 0;
2416 
 
2417 
  OUTS (outf, pcrel24 (((msw) << 16) | (lsw)));
2418 
  return 4;
2419 
}
2420 
 
2421 
static int
2422 
decode_LDSTidxI_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2423 
{
2424 
  /* LDSTidxI
2425 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2426 
     | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
2427 
     |.offset........................................................|
2428 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2429 
  int Z = ((iw0 >> (LDSTidxI_Z_bits - 16)) & LDSTidxI_Z_mask);
2430 
  int W = ((iw0 >> (LDSTidxI_W_bits - 16)) & LDSTidxI_W_mask);
2431 
  int sz = ((iw0 >> (LDSTidxI_sz_bits - 16)) & LDSTidxI_sz_mask);
2432 
  int reg = ((iw0 >> (LDSTidxI_reg_bits - 16)) & LDSTidxI_reg_mask);
2433 
  int ptr = ((iw0 >> (LDSTidxI_ptr_bits - 16)) & LDSTidxI_ptr_mask);
2434 
  int offset = ((iw1 >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
2435 
 
2436 
  if (W == 0 && sz == 0 && Z == 0)
2437 
    {
2438 
      OUTS (outf, dregs (reg));
2439 
      OUTS (outf, "=[");
2440 
      OUTS (outf, pregs (ptr));
2441 
      OUTS (outf, "+");
2442 
      OUTS (outf, imm16s4 (offset));
2443 
      OUTS (outf, "]");
2444 
    }
2445 
  else if (W == 0 && sz == 0 && Z == 1)
2446 
    {
2447 
      OUTS (outf, pregs (reg));
2448 
      OUTS (outf, "=[");
2449 
      OUTS (outf, pregs (ptr));
2450 
      OUTS (outf, "+");
2451 
      OUTS (outf, imm16s4 (offset));
2452 
      OUTS (outf, "]");
2453 
    }
2454 
  else if (W == 0 && sz == 1 && Z == 0)
2455 
    {
2456 
      OUTS (outf, dregs (reg));
2457 
      OUTS (outf, "=W[");
2458 
      OUTS (outf, pregs (ptr));
2459 
      OUTS (outf, "+");
2460 
      OUTS (outf, imm16s2 (offset));
2461 
      OUTS (outf, "] (Z)");
2462 
    }
2463 
  else if (W == 0 && sz == 1 && Z == 1)
2464 
    {
2465 
      OUTS (outf, dregs (reg));
2466 
      OUTS (outf, "=W[");
2467 
      OUTS (outf, pregs (ptr));
2468 
      OUTS (outf, "+");
2469 
      OUTS (outf, imm16s2 (offset));
2470 
      OUTS (outf, "](X)");
2471 
    }
2472 
  else if (W == 0 && sz == 2 && Z == 0)
2473 
    {
2474 
      OUTS (outf, dregs (reg));
2475 
      OUTS (outf, "=B[");
2476 
      OUTS (outf, pregs (ptr));
2477 
      OUTS (outf, "+");
2478 
      OUTS (outf, imm16 (offset));
2479 
      OUTS (outf, "] (Z)");
2480 
    }
2481 
  else if (W == 0 && sz == 2 && Z == 1)
2482 
    {
2483 
      OUTS (outf, dregs (reg));
2484 
      OUTS (outf, "=B[");
2485 
      OUTS (outf, pregs (ptr));
2486 
      OUTS (outf, "+");
2487 
      OUTS (outf, imm16 (offset));
2488 
      OUTS (outf, "](X)");
2489 
    }
2490 
  else if (W == 1 && sz == 0 && Z == 0)
2491 
    {
2492 
      OUTS (outf, "[");
2493 
      OUTS (outf, pregs (ptr));
2494 
      OUTS (outf, "+");
2495 
      OUTS (outf, imm16s4 (offset));
2496 
      OUTS (outf, "]=");
2497 
      OUTS (outf, dregs (reg));
2498 
    }
2499 
  else if (W == 1 && sz == 0 && Z == 1)
2500 
    {
2501 
      OUTS (outf, "[");
2502 
      OUTS (outf, pregs (ptr));
2503 
      OUTS (outf, "+");
2504 
      OUTS (outf, imm16s4 (offset));
2505 
      OUTS (outf, "]=");
2506 
      OUTS (outf, pregs (reg));
2507 
    }
2508 
  else if (W == 1 && sz == 1 && Z == 0)
2509 
    {
2510 
      OUTS (outf, "W[");
2511 
      OUTS (outf, pregs (ptr));
2512 
      OUTS (outf, "+");
2513 
      OUTS (outf, imm16s2 (offset));
2514 
      OUTS (outf, "]=");
2515 
      OUTS (outf, dregs (reg));
2516 
    }
2517 
  else if (W == 1 && sz == 2 && Z == 0)
2518 
    {
2519 
      OUTS (outf, "B[");
2520 
      OUTS (outf, pregs (ptr));
2521 
      OUTS (outf, "+");
2522 
      OUTS (outf, imm16 (offset));
2523 
      OUTS (outf, "]=");
2524 
      OUTS (outf, dregs (reg));
2525 
    }
2526 
  else
2527 
    return 0;
2528 
 
2529 
  return 4;
2530 
}
2531 
 
2532 
static int
2533 
decode_linkage_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2534 
{
2535 
  /* linkage
2536 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2537 
     | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
2538 
     |.framesize.....................................................|
2539 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2540 
  int R = ((iw0 >> (Linkage_R_bits - 16)) & Linkage_R_mask);
2541 
  int framesize = ((iw1 >> Linkage_framesize_bits) & Linkage_framesize_mask);
2542 
 
2543 
  if (R == 0)
2544 
    {
2545 
      OUTS (outf, "LINK ");
2546 
      OUTS (outf, uimm16s4 (framesize));
2547 
    }
2548 
  else if (R == 1)
2549 
    OUTS (outf, "UNLINK");
2550 
  else
2551 
    return 0;
2552 
 
2553 
  return 4;
2554 
}
2555 
 
2556 
static int
2557 
decode_dsp32mac_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2558 
{
2559 
  /* dsp32mac
2560 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2561 
     | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
2562 
     |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2563 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2564 
  int op1  = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask);
2565 
  int w1   = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
2566 
  int P    = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
2567 
  int MM   = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
2568 
  int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
2569 
  int w0   = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
2570 
  int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
2571 
  int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
2572 
  int dst  = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
2573 
  int h10  = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
2574 
  int h00  = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
2575 
  int op0  = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask);
2576 
  int h11  = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
2577 
  int h01  = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
2578 
 
2579 
  if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3)
2580 
    return 0;
2581 
 
2582 
  if (op1 == 3 && MM)
2583 
    return 0;
2584 
 
2585 
  if ((w1 || w0) && mmod == M_W32)
2586 
    return 0;
2587 
 
2588 
  if (((1 << mmod) & (P ? 0x31b : 0x1b5f)) == 0)
2589 
    return 0;
2590 
 
2591 
  if (w1 == 1 || op1 != 3)
2592 
    {
2593 
      if (w1)
2594 
        OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
2595 
 
2596 
      if (op1 == 3)
2597 
        OUTS (outf, " = A1");
2598 
      else
2599 
        {
2600 
          if (w1)
2601 
            OUTS (outf, " = (");
2602 
          decode_macfunc (1, op1, h01, h11, src0, src1, outf);
2603 
          if (w1)
2604 
            OUTS (outf, ")");
2605 
        }
2606 
 
2607 
      if (w0 == 1 || op0 != 3)
2608 
        {
2609 
          if (MM)
2610 
            OUTS (outf, " (M)");
2611 
          MM = 0;
2612 
          OUTS (outf, ", ");
2613 
        }
2614 
    }
2615 
 
2616 
  if (w0 == 1 || op0 != 3)
2617 
    {
2618 
      if (w0)
2619 
        OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
2620 
 
2621 
      if (op0 == 3)
2622 
        OUTS (outf, " = A0");
2623 
      else
2624 
        {
2625 
          if (w0)
2626 
            OUTS (outf, " = (");
2627 
          decode_macfunc (0, op0, h00, h10, src0, src1, outf);
2628 
          if (w0)
2629 
            OUTS (outf, ")");
2630 
        }
2631 
    }
2632 
 
2633 
  decode_optmode (mmod, MM, outf);
2634 
 
2635 
  return 4;
2636 
}
2637 
 
2638 
static int
2639 
decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2640 
{
2641 
  /* dsp32mult
2642 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2643 
     | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
2644 
     |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2645 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2646 
  int w1   = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
2647 
  int P    = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
2648 
  int MM   = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
2649 
  int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
2650 
  int w0   = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
2651 
  int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
2652 
  int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
2653 
  int dst  = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
2654 
  int h10  = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
2655 
  int h00  = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
2656 
  int h11  = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
2657 
  int h01  = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
2658 
 
2659 
  if (w1 == 0 && w0 == 0)
2660 
    return 0;
2661 
 
2662 
  if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0)
2663 
    return 0;
2664 
 
2665 
  if (w1)
2666 
    {
2667 
      OUTS (outf, P ? dregs (dst | 1) : dregs_hi (dst));
2668 
      OUTS (outf, " = ");
2669 
      decode_multfunc (h01, h11, src0, src1, outf);
2670 
 
2671 
      if (w0)
2672 
        {
2673 
          if (MM)
2674 
            OUTS (outf, " (M)");
2675 
          MM = 0;
2676 
          OUTS (outf, ", ");
2677 
        }
2678 
    }
2679 
 
2680 
  if (w0)
2681 
    {
2682 
      OUTS (outf, dregs (dst));
2683 
      OUTS (outf, " = ");
2684 
      decode_multfunc (h00, h10, src0, src1, outf);
2685 
    }
2686 
 
2687 
  decode_optmode (mmod, MM, outf);
2688 
  return 4;
2689 
}
2690 
 
2691 
static int
2692 
decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2693 
{
2694 
  /* dsp32alu
2695 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2696 
     | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
2697 
     |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
2698 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2699 
  int s    = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask);
2700 
  int x    = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask);
2701 
  int aop  = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask);
2702 
  int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask);
2703 
  int src1 = ((iw1 >> DSP32Alu_src1_bits) & DSP32Alu_src1_mask);
2704 
  int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask);
2705 
  int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask);
2706 
  int HL   = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask);
2707 
  int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask);
2708 
 
2709 
  if (aop == 0 && aopcde == 9 && HL == 0 && s == 0)
2710 
    {
2711 
      OUTS (outf, "A0.L=");
2712 
      OUTS (outf, dregs_lo (src0));
2713 
    }
2714 
  else if (aop == 2 && aopcde == 9 && HL == 1 && s == 0)
2715 
    {
2716 
      OUTS (outf, "A1.H=");
2717 
      OUTS (outf, dregs_hi (src0));
2718 
    }
2719 
  else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0)
2720 
    {
2721 
      OUTS (outf, "A1.L=");
2722 
      OUTS (outf, dregs_lo (src0));
2723 
    }
2724 
  else if (aop == 0 && aopcde == 9 && HL == 1 && s == 0)
2725 
    {
2726 
      OUTS (outf, "A0.H=");
2727 
      OUTS (outf, dregs_hi (src0));
2728 
    }
2729 
  else if (x == 1 && HL == 1 && aop == 3 && aopcde == 5)
2730 
    {
2731 
      OUTS (outf, dregs_hi (dst0));
2732 
      OUTS (outf, "=");
2733 
      OUTS (outf, dregs (src0));
2734 
      OUTS (outf, "-");
2735 
      OUTS (outf, dregs (src1));
2736 
      OUTS (outf, "(RND20)");
2737 
    }
2738 
  else if (x == 1 && HL == 1 && aop == 2 && aopcde == 5)
2739 
    {
2740 
      OUTS (outf, dregs_hi (dst0));
2741 
      OUTS (outf, "=");
2742 
      OUTS (outf, dregs (src0));
2743 
      OUTS (outf, "+");
2744 
      OUTS (outf, dregs (src1));
2745 
      OUTS (outf, "(RND20)");
2746 
    }
2747 
  else if (x == 0 && HL == 0 && aop == 1 && aopcde == 5)
2748 
    {
2749 
      OUTS (outf, dregs_lo (dst0));
2750 
      OUTS (outf, "=");
2751 
      OUTS (outf, dregs (src0));
2752 
      OUTS (outf, "-");
2753 
      OUTS (outf, dregs (src1));
2754 
      OUTS (outf, "(RND12)");
2755 
    }
2756 
  else if (x == 0 && HL == 0 && aop == 0 && aopcde == 5)
2757 
    {
2758 
      OUTS (outf, dregs_lo (dst0));
2759 
      OUTS (outf, "=");
2760 
      OUTS (outf, dregs (src0));
2761 
      OUTS (outf, "+");
2762 
      OUTS (outf, dregs (src1));
2763 
      OUTS (outf, "(RND12)");
2764 
    }
2765 
  else if (x == 1 && HL == 0 && aop == 3 && aopcde == 5)
2766 
    {
2767 
      OUTS (outf, dregs_lo (dst0));
2768 
      OUTS (outf, "=");
2769 
      OUTS (outf, dregs (src0));
2770 
      OUTS (outf, "-");
2771 
      OUTS (outf, dregs (src1));
2772 
      OUTS (outf, "(RND20)");
2773 
    }
2774 
  else if (x == 0 && HL == 1 && aop == 0 && aopcde == 5)
2775 
    {
2776 
      OUTS (outf, dregs_hi (dst0));
2777 
      OUTS (outf, "=");
2778 
      OUTS (outf, dregs (src0));
2779 
      OUTS (outf, "+");
2780 
      OUTS (outf, dregs (src1));
2781 
      OUTS (outf, "(RND12)");
2782 
    }
2783 
  else if (x == 1 && HL == 0 && aop == 2 && aopcde == 5)
2784 
    {
2785 
      OUTS (outf, dregs_lo (dst0));
2786 
      OUTS (outf, "=");
2787 
      OUTS (outf, dregs (src0));
2788 
      OUTS (outf, "+");
2789 
      OUTS (outf, dregs (src1));
2790 
      OUTS (outf, "(RND20)");
2791 
    }
2792 
  else if (x == 0 && HL == 1 && aop == 1 && aopcde == 5)
2793 
    {
2794 
      OUTS (outf, dregs_hi (dst0));
2795 
      OUTS (outf, "=");
2796 
      OUTS (outf, dregs (src0));
2797 
      OUTS (outf, "-");
2798 
      OUTS (outf, dregs (src1));
2799 
      OUTS (outf, "(RND12)");
2800 
    }
2801 
  else if (HL == 1 && aop == 0 && aopcde == 2)
2802 
    {
2803 
      OUTS (outf, dregs_hi (dst0));
2804 
      OUTS (outf, "=");
2805 
      OUTS (outf, dregs_lo (src0));
2806 
      OUTS (outf, "+");
2807 
      OUTS (outf, dregs_lo (src1));
2808 
      OUTS (outf, " ");
2809 
      amod1 (s, x, outf);
2810 
    }
2811 
  else if (HL == 1 && aop == 1 && aopcde == 2)
2812 
    {
2813 
      OUTS (outf, dregs_hi (dst0));
2814 
      OUTS (outf, "=");
2815 
      OUTS (outf, dregs_lo (src0));
2816 
      OUTS (outf, "+");
2817 
      OUTS (outf, dregs_hi (src1));
2818 
      OUTS (outf, " ");
2819 
      amod1 (s, x, outf);
2820 
    }
2821 
  else if (HL == 1 && aop == 2 && aopcde == 2)
2822 
    {
2823 
      OUTS (outf, dregs_hi (dst0));
2824 
      OUTS (outf, "=");
2825 
      OUTS (outf, dregs_hi (src0));
2826 
      OUTS (outf, "+");
2827 
      OUTS (outf, dregs_lo (src1));
2828 
      OUTS (outf, " ");
2829 
      amod1 (s, x, outf);
2830 
    }
2831 
  else if (HL == 1 && aop == 3 && aopcde == 2)
2832 
    {
2833 
      OUTS (outf, dregs_hi (dst0));
2834 
      OUTS (outf, "=");
2835 
      OUTS (outf, dregs_hi (src0));
2836 
      OUTS (outf, "+");
2837 
      OUTS (outf, dregs_hi (src1));
2838 
      OUTS (outf, " ");
2839 
      amod1 (s, x, outf);
2840 
    }
2841 
  else if (HL == 0 && aop == 0 && aopcde == 3)
2842 
    {
2843 
      OUTS (outf, dregs_lo (dst0));
2844 
      OUTS (outf, "=");
2845 
      OUTS (outf, dregs_lo (src0));
2846 
      OUTS (outf, "-");
2847 
      OUTS (outf, dregs_lo (src1));
2848 
      OUTS (outf, " ");
2849 
      amod1 (s, x, outf);
2850 
    }
2851 
  else if (HL == 0 && aop == 1 && aopcde == 3)
2852 
    {
2853 
      OUTS (outf, dregs_lo (dst0));
2854 
      OUTS (outf, "=");
2855 
      OUTS (outf, dregs_lo (src0));
2856 
      OUTS (outf, "-");
2857 
      OUTS (outf, dregs_hi (src1));
2858 
      OUTS (outf, " ");
2859 
      amod1 (s, x, outf);
2860 
    }
2861 
  else if (HL == 0 && aop == 3 && aopcde == 2)
2862 
    {
2863 
      OUTS (outf, dregs_lo (dst0));
2864 
      OUTS (outf, "=");
2865 
      OUTS (outf, dregs_hi (src0));
2866 
      OUTS (outf, "+");
2867 
      OUTS (outf, dregs_hi (src1));
2868 
      OUTS (outf, " ");
2869 
      amod1 (s, x, outf);
2870 
    }
2871 
  else if (HL == 1 && aop == 0 && aopcde == 3)
2872 
    {
2873 
      OUTS (outf, dregs_hi (dst0));
2874 
      OUTS (outf, "=");
2875 
      OUTS (outf, dregs_lo (src0));
2876 
      OUTS (outf, "-");
2877 
      OUTS (outf, dregs_lo (src1));
2878 
      OUTS (outf, " ");
2879 
      amod1 (s, x, outf);
2880 
    }
2881 
  else if (HL == 1 && aop == 1 && aopcde == 3)
2882 
    {
2883 
      OUTS (outf, dregs_hi (dst0));
2884 
      OUTS (outf, "=");
2885 
      OUTS (outf, dregs_lo (src0));
2886 
      OUTS (outf, "-");
2887 
      OUTS (outf, dregs_hi (src1));
2888 
      OUTS (outf, " ");
2889 
      amod1 (s, x, outf);
2890 
    }
2891 
  else if (HL == 1 && aop == 2 && aopcde == 3)
2892 
    {
2893 
      OUTS (outf, dregs_hi (dst0));
2894 
      OUTS (outf, "=");
2895 
      OUTS (outf, dregs_hi (src0));
2896 
      OUTS (outf, "-");
2897 
      OUTS (outf, dregs_lo (src1));
2898 
      OUTS (outf, " ");
2899 
      amod1 (s, x, outf);
2900 
    }
2901 
  else if (HL == 1 && aop == 3 && aopcde == 3)
2902 
    {
2903 
      OUTS (outf, dregs_hi (dst0));
2904 
      OUTS (outf, "=");
2905 
      OUTS (outf, dregs_hi (src0));
2906 
      OUTS (outf, "-");
2907 
      OUTS (outf, dregs_hi (src1));
2908 
      OUTS (outf, " ");
2909 
      amod1 (s, x, outf);
2910 
    }
2911 
  else if (HL == 0 && aop == 2 && aopcde == 2)
2912 
    {
2913 
      OUTS (outf, dregs_lo (dst0));
2914 
      OUTS (outf, "=");
2915 
      OUTS (outf, dregs_hi (src0));
2916 
      OUTS (outf, "+");
2917 
      OUTS (outf, dregs_lo (src1));
2918 
      OUTS (outf, " ");
2919 
      amod1 (s, x, outf);
2920 
    }
2921 
  else if (HL == 0 && aop == 1 && aopcde == 2)
2922 
    {
2923 
      OUTS (outf, dregs_lo (dst0));
2924 
      OUTS (outf, "=");
2925 
      OUTS (outf, dregs_lo (src0));
2926 
      OUTS (outf, "+");
2927 
      OUTS (outf, dregs_hi (src1));
2928 
      OUTS (outf, " ");
2929 
      amod1 (s, x, outf);
2930 
    }
2931 
  else if (HL == 0 && aop == 2 && aopcde == 3)
2932 
    {
2933 
      OUTS (outf, dregs_lo (dst0));
2934 
      OUTS (outf, "=");
2935 
      OUTS (outf, dregs_hi (src0));
2936 
      OUTS (outf, "-");
2937 
      OUTS (outf, dregs_lo (src1));
2938 
      OUTS (outf, " ");
2939 
      amod1 (s, x, outf);
2940 
    }
2941 
  else if (HL == 0 && aop == 3 && aopcde == 3)
2942 
    {
2943 
      OUTS (outf, dregs_lo (dst0));
2944 
      OUTS (outf, "=");
2945 
      OUTS (outf, dregs_hi (src0));
2946 
      OUTS (outf, "-");
2947 
      OUTS (outf, dregs_hi (src1));
2948 
      OUTS (outf, " ");
2949 
      amod1 (s, x, outf);
2950 
    }
2951 
  else if (HL == 0 && aop == 0 && aopcde == 2)
2952 
    {
2953 
      OUTS (outf, dregs_lo (dst0));
2954 
      OUTS (outf, "=");
2955 
      OUTS (outf, dregs_lo (src0));
2956 
      OUTS (outf, "+");
2957 
      OUTS (outf, dregs_lo (src1));
2958 
      OUTS (outf, " ");
2959 
      amod1 (s, x, outf);
2960 
    }
2961 
  else if (aop == 0 && aopcde == 9 && s == 1)
2962 
    {
2963 
      OUTS (outf, "A0=");
2964 
      OUTS (outf, dregs (src0));
2965 
    }
2966 
  else if (aop == 3 && aopcde == 11 && s == 0)
2967 
    OUTS (outf, "A0-=A1");
2968 
 
2969 
  else if (aop == 3 && aopcde == 11 && s == 1)
2970 
    OUTS (outf, "A0-=A1(W32)");
2971 
 
2972 
  else if (aop == 3 && aopcde == 22 && HL == 1)
2973 
    {
2974 
      OUTS (outf, dregs (dst0));
2975 
      OUTS (outf, "=BYTEOP2M(");
2976 
      OUTS (outf, dregs (src0 + 1));
2977 
      OUTS (outf, ":");
2978 
      OUTS (outf, imm5 (src0));
2979 
      OUTS (outf, ",");
2980 
      OUTS (outf, dregs (src1 + 1));
2981 
      OUTS (outf, ":");
2982 
      OUTS (outf, imm5 (src1));
2983 
      OUTS (outf, ")(TH");
2984 
      if (s == 1)
2985 
        OUTS (outf, ", R)");
2986 
      else
2987 
        OUTS (outf, ")");
2988 
    }
2989 
  else if (aop == 3 && aopcde == 22 && HL == 0)
2990 
    {
2991 
      OUTS (outf, dregs (dst0));
2992 
      OUTS (outf, "=BYTEOP2M(");
2993 
      OUTS (outf, dregs (src0 + 1));
2994 
      OUTS (outf, ":");
2995 
      OUTS (outf, imm5 (src0));
2996 
      OUTS (outf, ",");
2997 
      OUTS (outf, dregs (src1 + 1));
2998 
      OUTS (outf, ":");
2999 
      OUTS (outf, imm5 (src1));
3000 
      OUTS (outf, ")(TL");
3001 
      if (s == 1)
3002 
        OUTS (outf, ", R)");
3003 
      else
3004 
        OUTS (outf, ")");
3005 
    }
3006 
  else if (aop == 2 && aopcde == 22 && HL == 1)
3007 
    {
3008 
      OUTS (outf, dregs (dst0));
3009 
      OUTS (outf, "=BYTEOP2M(");
3010 
      OUTS (outf, dregs (src0 + 1));
3011 
      OUTS (outf, ":");
3012 
      OUTS (outf, imm5 (src0));
3013 
      OUTS (outf, ",");
3014 
      OUTS (outf, dregs (src1 + 1));
3015 
      OUTS (outf, ":");
3016 
      OUTS (outf, imm5 (src1));
3017 
      OUTS (outf, ")(RNDH");
3018 
      if (s == 1)
3019 
        OUTS (outf, ", R)");
3020 
      else
3021 
        OUTS (outf, ")");
3022 
    }
3023 
  else if (aop == 2 && aopcde == 22 && HL == 0)
3024 
    {
3025 
      OUTS (outf, dregs (dst0));
3026 
      OUTS (outf, "=BYTEOP2M(");
3027 
      OUTS (outf, dregs (src0 + 1));
3028 
      OUTS (outf, ":");
3029 
      OUTS (outf, imm5 (src0));
3030 
      OUTS (outf, ",");
3031 
      OUTS (outf, dregs (src1 + 1));
3032 
      OUTS (outf, ":");
3033 
      OUTS (outf, imm5 (src1));
3034 
      OUTS (outf, ")(RNDL");
3035 
      if (s == 1)
3036 
        OUTS (outf, ", R)");
3037 
      else
3038 
        OUTS (outf, ")");
3039 
    }
3040 
  else if (aop == 1 && aopcde == 22 && HL == 1)
3041 
    {
3042 
      OUTS (outf, dregs (dst0));
3043 
      OUTS (outf, "=BYTEOP2P(");
3044 
      OUTS (outf, dregs (src0 + 1));
3045 
      OUTS (outf, ":");
3046 
      OUTS (outf, imm5 (src0));
3047 
      OUTS (outf, ",");
3048 
      OUTS (outf, dregs (src1 + 1));
3049 
      OUTS (outf, ":");
3050 
      OUTS (outf, imm5 (src1));
3051 
      OUTS (outf, ")(TH");
3052 
      if (s == 1)
3053 
        OUTS (outf, ", R)");
3054 
      else
3055 
        OUTS (outf, ")");
3056 
    }
3057 
  else if (aop == 1 && aopcde == 22 && HL == 0)
3058 
    {
3059 
      OUTS (outf, dregs (dst0));
3060 
      OUTS (outf, "=BYTEOP2P(");
3061 
      OUTS (outf, dregs (src0 + 1));
3062 
      OUTS (outf, ":");
3063 
      OUTS (outf, imm5 (src0));
3064 
      OUTS (outf, ",");
3065 
      OUTS (outf, dregs (src1 + 1));
3066 
      OUTS (outf, ":");
3067 
      OUTS (outf, imm5 (src1));
3068 
      OUTS (outf, ")(TL");
3069 
      if (s == 1)
3070 
        OUTS (outf, ", R)");
3071 
      else
3072 
        OUTS (outf, ")");
3073 
    }
3074 
  else if (aop == 0 && aopcde == 22 && HL == 1)
3075 
    {
3076 
      OUTS (outf, dregs (dst0));
3077 
      OUTS (outf, "=BYTEOP2P(");
3078 
      OUTS (outf, dregs (src0 + 1));
3079 
      OUTS (outf, ":");
3080 
      OUTS (outf, imm5 (src0));
3081 
      OUTS (outf, ",");
3082 
      OUTS (outf, dregs (src1 + 1));
3083 
      OUTS (outf, ":");
3084 
      OUTS (outf, imm5 (src1));
3085 
      OUTS (outf, ")(RNDH");
3086 
      if (s == 1)
3087 
        OUTS (outf, ", R)");
3088 
      else
3089 
        OUTS (outf, ")");
3090 
    }
3091 
  else if (aop == 0 && aopcde == 22 && HL == 0)
3092 
    {
3093 
      OUTS (outf, dregs (dst0));
3094 
      OUTS (outf, "=BYTEOP2P(");
3095 
      OUTS (outf, dregs (src0 + 1));
3096 
      OUTS (outf, ":");
3097 
      OUTS (outf, imm5 (src0));
3098 
      OUTS (outf, ",");
3099 
      OUTS (outf, dregs (src1 + 1));
3100 
      OUTS (outf, ":");
3101 
      OUTS (outf, imm5 (src1));
3102 
      OUTS (outf, ")(RNDL");
3103 
      if (s == 1)
3104 
        OUTS (outf, ", R)");
3105 
      else
3106 
        OUTS (outf, ")");
3107 
    }
3108 
  else if (aop == 0 && s == 0 && aopcde == 8)
3109 
    OUTS (outf, "A0=0");
3110 
 
3111 
  else if (aop == 0 && s == 1 && aopcde == 8)
3112 
    OUTS (outf, "A0=A0(S)");
3113 
 
3114 
  else if (aop == 1 && s == 0 && aopcde == 8)
3115 
    OUTS (outf, "A1=0");
3116 
 
3117 
  else if (aop == 1 && s == 1 && aopcde == 8)
3118 
    OUTS (outf, "A1=A1(S)");
3119 
 
3120 
  else if (aop == 2 && s == 0 && aopcde == 8)
3121 
    OUTS (outf, "A1=A0=0");
3122 
 
3123 
  else if (aop == 2 && s == 1 && aopcde == 8)
3124 
    OUTS (outf, "A1=A1(S),A0=A0(S)");
3125 
 
3126 
  else if (aop == 3 && s == 0 && aopcde == 8)
3127 
    OUTS (outf, "A0=A1");
3128 
 
3129 
  else if (aop == 3 && s == 1 && aopcde == 8)
3130 
    OUTS (outf, "A1=A0");
3131 
 
3132 
  else if (aop == 1 && aopcde == 9 && s == 0)
3133 
    {
3134 
      OUTS (outf, "A0.x=");
3135 
      OUTS (outf, dregs_lo (src0));
3136 
    }
3137 
  else if (aop == 1 && HL == 0 && aopcde == 11)
3138 
    {
3139 
      OUTS (outf, dregs_lo (dst0));
3140 
      OUTS (outf, "=(A0+=A1)");
3141 
    }
3142 
  else if (aop == 3 && HL == 0 && aopcde == 16)
3143 
    OUTS (outf, "A1= ABS A0,A0= ABS A0");
3144 
 
3145 
  else if (aop == 0 && aopcde == 23 && HL == 1)
3146 
    {
3147 
      OUTS (outf, dregs (dst0));
3148 
      OUTS (outf, "=BYTEOP3P(");
3149 
      OUTS (outf, dregs (src0 + 1));
3150 
      OUTS (outf, ":");
3151 
      OUTS (outf, imm5 (src0));
3152 
      OUTS (outf, ",");
3153 
      OUTS (outf, dregs (src1 + 1));
3154 
      OUTS (outf, ":");
3155 
      OUTS (outf, imm5 (src1));
3156 
      OUTS (outf, ")(HI");
3157 
      if (s == 1)
3158 
        OUTS (outf, ", R)");
3159 
      else
3160 
        OUTS (outf, ")");
3161 
    }
3162 
  else if (aop == 3 && aopcde == 9 && s == 0)
3163 
    {
3164 
      OUTS (outf, "A1.x=");
3165 
      OUTS (outf, dregs_lo (src0));
3166 
    }
3167 
  else if (aop == 1 && HL == 1 && aopcde == 16)
3168 
    OUTS (outf, "A1= ABS A1");
3169 
 
3170 
  else if (aop == 0 && HL == 1 && aopcde == 16)
3171 
    OUTS (outf, "A1= ABS A0");
3172 
 
3173 
  else if (aop == 2 && aopcde == 9 && s == 1)
3174 
    {
3175 
      OUTS (outf, "A1=");
3176 
      OUTS (outf, dregs (src0));
3177 
    }
3178 
  else if (HL == 0 && aop == 3 && aopcde == 12)
3179 
    {
3180 
      OUTS (outf, dregs_lo (dst0));
3181 
      OUTS (outf, "=");
3182 
      OUTS (outf, dregs (src0));
3183 
      OUTS (outf, "(RND)");
3184 
    }
3185 
  else if (aop == 1 && HL == 0 && aopcde == 16)
3186 
    OUTS (outf, "A0= ABS A1");
3187 
 
3188 
  else if (aop == 0 && HL == 0 && aopcde == 16)
3189 
    OUTS (outf, "A0= ABS A0");
3190 
 
3191 
  else if (aop == 3 && HL == 0 && aopcde == 15)
3192 
    {
3193 
      OUTS (outf, dregs (dst0));
3194 
      OUTS (outf, "=-");
3195 
      OUTS (outf, dregs (src0));
3196 
      OUTS (outf, "(V)");
3197 
    }
3198 
  else if (aop == 3 && s == 1 && HL == 0 && aopcde == 7)
3199 
    {
3200 
      OUTS (outf, dregs (dst0));
3201 
      OUTS (outf, "=-");
3202 
      OUTS (outf, dregs (src0));
3203 
      OUTS (outf, "(S)");
3204 
    }
3205 
  else if (aop == 3 && s == 0 && HL == 0 && aopcde == 7)
3206 
    {
3207 
      OUTS (outf, dregs (dst0));
3208 
      OUTS (outf, "=-");
3209 
      OUTS (outf, dregs (src0));
3210 
      OUTS (outf, "(NS)");
3211 
    }
3212 
  else if (aop == 1 && HL == 1 && aopcde == 11)
3213 
    {
3214 
      OUTS (outf, dregs_hi (dst0));
3215 
      OUTS (outf, "=(A0+=A1)");
3216 
    }
3217 
  else if (aop == 2 && aopcde == 11 && s == 0)
3218 
    OUTS (outf, "A0+=A1");
3219 
 
3220 
  else if (aop == 2 && aopcde == 11 && s == 1)
3221 
    OUTS (outf, "A0+=A1(W32)");
3222 
 
3223 
  else if (aop == 3 && HL == 0 && aopcde == 14)
3224 
    OUTS (outf, "A1=-A1,A0=-A0");
3225 
 
3226 
  else if (HL == 1 && aop == 3 && aopcde == 12)
3227 
    {
3228 
      OUTS (outf, dregs_hi (dst0));
3229 
      OUTS (outf, "=");
3230 
      OUTS (outf, dregs (src0));
3231 
      OUTS (outf, "(RND)");
3232 
    }
3233 
  else if (aop == 0 && aopcde == 23 && HL == 0)
3234 
    {
3235 
      OUTS (outf, dregs (dst0));
3236 
      OUTS (outf, "=BYTEOP3P(");
3237 
      OUTS (outf, dregs (src0 + 1));
3238 
      OUTS (outf, ":");
3239 
      OUTS (outf, imm5 (src0));
3240 
      OUTS (outf, ",");
3241 
      OUTS (outf, dregs (src1 + 1));
3242 
      OUTS (outf, ":");
3243 
      OUTS (outf, imm5 (src1));
3244 
      OUTS (outf, ")(LO");
3245 
      if (s == 1)
3246 
        OUTS (outf, ", R)");
3247 
      else
3248 
        OUTS (outf, ")");
3249 
    }
3250 
  else if (aop == 0 && HL == 0 && aopcde == 14)
3251 
    OUTS (outf, "A0=-A0");
3252 
 
3253 
  else if (aop == 1 && HL == 0 && aopcde == 14)
3254 
    OUTS (outf, "A0=-A1");
3255 
 
3256 
  else if (aop == 0 && HL == 1 && aopcde == 14)
3257 
    OUTS (outf, "A1=-A0");
3258 
 
3259 
  else if (aop == 1 && HL == 1 && aopcde == 14)
3260 
    OUTS (outf, "A1=-A1");
3261 
 
3262 
  else if (aop == 0 && aopcde == 12)
3263 
    {
3264 
      OUTS (outf, dregs_hi (dst0));
3265 
      OUTS (outf, "=");
3266 
      OUTS (outf, dregs_lo (dst0));
3267 
      OUTS (outf, "=SIGN(");
3268 
      OUTS (outf, dregs_hi (src0));
3269 
      OUTS (outf, ")*");
3270 
      OUTS (outf, dregs_hi (src1));
3271 
      OUTS (outf, "+SIGN(");
3272 
      OUTS (outf, dregs_lo (src0));
3273 
      OUTS (outf, ")*");
3274 
      OUTS (outf, dregs_lo (src1));
3275 
      OUTS (outf, ")");
3276 
    }
3277 
  else if (aop == 2 && aopcde == 0)
3278 
    {
3279 
      OUTS (outf, dregs (dst0));
3280 
      OUTS (outf, "=");
3281 
      OUTS (outf, dregs (src0));
3282 
      OUTS (outf, "-|+");
3283 
      OUTS (outf, dregs (src1));
3284 
      OUTS (outf, " ");
3285 
      amod0 (s, x, outf);
3286 
    }
3287 
  else if (aop == 1 && aopcde == 12)
3288 
    {
3289 
      OUTS (outf, dregs (dst1));
3290 
      OUTS (outf, "=A1.L+A1.H,");
3291 
      OUTS (outf, dregs (dst0));
3292 
      OUTS (outf, "=A0.L+A0.H");
3293 
    }
3294 
  else if (aop == 2 && aopcde == 4)
3295 
    {
3296 
      OUTS (outf, dregs (dst1));
3297 
      OUTS (outf, "=");
3298 
      OUTS (outf, dregs (src0));
3299 
      OUTS (outf, "+");
3300 
      OUTS (outf, dregs (src1));
3301 
      OUTS (outf, ",");
3302 
      OUTS (outf, dregs (dst0));
3303 
      OUTS (outf, "=");
3304 
      OUTS (outf, dregs (src0));
3305 
      OUTS (outf, "-");
3306 
      OUTS (outf, dregs (src1));
3307 
      OUTS (outf, " ");
3308 
      amod1 (s, x, outf);
3309 
    }
3310 
  else if (HL == 0 && aopcde == 1)
3311 
    {
3312 
      OUTS (outf, dregs (dst1));
3313 
      OUTS (outf, "=");
3314 
      OUTS (outf, dregs (src0));
3315 
      OUTS (outf, "+|+");
3316 
      OUTS (outf, dregs (src1));
3317 
      OUTS (outf, ",");
3318 
      OUTS (outf, dregs (dst0));
3319 
      OUTS (outf, "=");
3320 
      OUTS (outf, dregs (src0));
3321 
      OUTS (outf, "-|-");
3322 
      OUTS (outf, dregs (src1));
3323 
      amod0amod2 (s, x, aop, outf);
3324 
    }
3325 
  else if (aop == 0 && aopcde == 11)
3326 
    {
3327 
      OUTS (outf, dregs (dst0));
3328 
      OUTS (outf, "=(A0+=A1)");
3329 
    }
3330 
  else if (aop == 0 && aopcde == 10)
3331 
    {
3332 
      OUTS (outf, dregs_lo (dst0));
3333 
      OUTS (outf, "=A0.x");
3334 
    }
3335 
  else if (aop == 1 && aopcde == 10)
3336 
    {
3337 
      OUTS (outf, dregs_lo (dst0));
3338 
      OUTS (outf, "=A1.x");
3339 
    }
3340 
  else if (aop == 1 && aopcde == 0)
3341 
    {
3342 
      OUTS (outf, dregs (dst0));
3343 
      OUTS (outf, "=");
3344 
      OUTS (outf, dregs (src0));
3345 
      OUTS (outf, "+|-");
3346 
      OUTS (outf, dregs (src1));
3347 
      OUTS (outf, " ");
3348 
      amod0 (s, x, outf);
3349 
    }
3350 
  else if (aop == 3 && aopcde == 0)
3351 
    {
3352 
      OUTS (outf, dregs (dst0));
3353 
      OUTS (outf, "=");
3354 
      OUTS (outf, dregs (src0));
3355 
      OUTS (outf, "-|-");
3356 
      OUTS (outf, dregs (src1));
3357 
      OUTS (outf, " ");
3358 
      amod0 (s, x, outf);
3359 
    }
3360 
  else if (aop == 1 && aopcde == 4)
3361 
    {
3362 
      OUTS (outf, dregs (dst0));
3363 
      OUTS (outf, "=");
3364 
      OUTS (outf, dregs (src0));
3365 
      OUTS (outf, "-");
3366 
      OUTS (outf, dregs (src1));
3367 
      OUTS (outf, " ");
3368 
      amod1 (s, x, outf);
3369 
    }
3370 
  else if (aop == 0 && aopcde == 17)
3371 
    {
3372 
      OUTS (outf, dregs (dst1));
3373 
      OUTS (outf, "=A1+A0,");
3374 
      OUTS (outf, dregs (dst0));
3375 
      OUTS (outf, "=A1-A0 ");
3376 
      amod1 (s, x, outf);
3377 
    }
3378 
  else if (aop == 1 && aopcde == 17)
3379 
    {
3380 
      OUTS (outf, dregs (dst1));
3381 
      OUTS (outf, "=A0+A1,");
3382 
      OUTS (outf, dregs (dst0));
3383 
      OUTS (outf, "=A0-A1 ");
3384 
      amod1 (s, x, outf);
3385 
    }
3386 
  else if (aop == 0 && aopcde == 18)
3387 
    {
3388 
      OUTS (outf, "SAA(");
3389 
      OUTS (outf, dregs (src0 + 1));
3390 
      OUTS (outf, ":");
3391 
      OUTS (outf, imm5 (src0));
3392 
      OUTS (outf, ",");
3393 
      OUTS (outf, dregs (src1 + 1));
3394 
      OUTS (outf, ":");
3395 
      OUTS (outf, imm5 (src1));
3396 
      OUTS (outf, ") ");
3397 
      aligndir (s, outf);
3398 
    }
3399 
  else if (aop == 3 && aopcde == 18)
3400 
    OUTS (outf, "DISALGNEXCPT");
3401 
 
3402 
  else if (aop == 0 && aopcde == 20)
3403 
    {
3404 
      OUTS (outf, dregs (dst0));
3405 
      OUTS (outf, "=BYTEOP1P(");
3406 
      OUTS (outf, dregs (src0 + 1));
3407 
      OUTS (outf, ":");
3408 
      OUTS (outf, imm5 (src0));
3409 
      OUTS (outf, ",");
3410 
      OUTS (outf, dregs (src1 + 1));
3411 
      OUTS (outf, ":");
3412 
      OUTS (outf, imm5 (src1));
3413 
      OUTS (outf, ")");
3414 
      aligndir (s, outf);
3415 
    }
3416 
  else if (aop == 1 && aopcde == 20)
3417 
    {
3418 
      OUTS (outf, dregs (dst0));
3419 
      OUTS (outf, "=BYTEOP1P(");
3420 
      OUTS (outf, dregs (src0 + 1));
3421 
      OUTS (outf, ":");
3422 
      OUTS (outf, imm5 (src0));
3423 
      OUTS (outf, ",");
3424 
      OUTS (outf, dregs (src1 + 1));
3425 
      OUTS (outf, ":");
3426 
      OUTS (outf, imm5 (src1));
3427 
      OUTS (outf, ")(T");
3428 
      if (s == 1)
3429 
        OUTS (outf, ", R)");
3430 
      else
3431 
        OUTS (outf, ")");
3432 
    }
3433 
  else if (aop == 0 && aopcde == 21)
3434 
    {
3435 
      OUTS (outf, "(");
3436 
      OUTS (outf, dregs (dst1));
3437 
      OUTS (outf, ",");
3438 
      OUTS (outf, dregs (dst0));
3439 
      OUTS (outf, ")=BYTEOP16P(");
3440 
      OUTS (outf, dregs (src0 + 1));
3441 
      OUTS (outf, ":");
3442 
      OUTS (outf, imm5 (src0));
3443 
      OUTS (outf, ",");
3444 
      OUTS (outf, dregs (src1 + 1));
3445 
      OUTS (outf, ":");
3446 
      OUTS (outf, imm5 (src1));
3447 
      OUTS (outf, ") ");
3448 
      aligndir (s, outf);
3449 
    }
3450 
  else if (aop == 1 && aopcde == 21)
3451 
    {
3452 
      OUTS (outf, "(");
3453 
      OUTS (outf, dregs (dst1));
3454 
      OUTS (outf, ",");
3455 
      OUTS (outf, dregs (dst0));
3456 
      OUTS (outf, ")=BYTEOP16M(");
3457 
      OUTS (outf, dregs (src0 + 1));
3458 
      OUTS (outf, ":");
3459 
      OUTS (outf, imm5 (src0));
3460 
      OUTS (outf, ",");
3461 
      OUTS (outf, dregs (src1 + 1));
3462 
      OUTS (outf, ":");
3463 
      OUTS (outf, imm5 (src1));
3464 
      OUTS (outf, ") ");
3465 
      aligndir (s, outf);
3466 
    }
3467 
  else if (aop == 2 && aopcde == 7)
3468 
    {
3469 
      OUTS (outf, dregs (dst0));
3470 
      OUTS (outf, "= ABS ");
3471 
      OUTS (outf, dregs (src0));
3472 
    }
3473 
  else if (aop == 1 && aopcde == 7)
3474 
    {
3475 
      OUTS (outf, dregs (dst0));
3476 
      OUTS (outf, "=MIN(");
3477 
      OUTS (outf, dregs (src0));
3478 
      OUTS (outf, ",");
3479 
      OUTS (outf, dregs (src1));
3480 
      OUTS (outf, ")");
3481 
    }
3482 
  else if (aop == 0 && aopcde == 7)
3483 
    {
3484 
      OUTS (outf, dregs (dst0));
3485 
      OUTS (outf, "=MAX(");
3486 
      OUTS (outf, dregs (src0));
3487 
      OUTS (outf, ",");
3488 
      OUTS (outf, dregs (src1));
3489 
      OUTS (outf, ")");
3490 
    }
3491 
  else if (aop == 2 && aopcde == 6)
3492 
    {
3493 
      OUTS (outf, dregs (dst0));
3494 
      OUTS (outf, "= ABS ");
3495 
      OUTS (outf, dregs (src0));
3496 
      OUTS (outf, "(V)");
3497 
    }
3498 
  else if (aop == 1 && aopcde == 6)
3499 
    {
3500 
      OUTS (outf, dregs (dst0));
3501 
      OUTS (outf, "=MIN(");
3502 
      OUTS (outf, dregs (src0));
3503 
      OUTS (outf, ",");
3504 
      OUTS (outf, dregs (src1));
3505 
      OUTS (outf, ")(V)");
3506 
    }
3507 
  else if (aop == 0 && aopcde == 6)
3508 
    {
3509 
      OUTS (outf, dregs (dst0));
3510 
      OUTS (outf, "=MAX(");
3511 
      OUTS (outf, dregs (src0));
3512 
      OUTS (outf, ",");
3513 
      OUTS (outf, dregs (src1));
3514 
      OUTS (outf, ")(V)");
3515 
    }
3516 
  else if (HL == 1 && aopcde == 1)
3517 
    {
3518 
      OUTS (outf, dregs (dst1));
3519 
      OUTS (outf, "=");
3520 
      OUTS (outf, dregs (src0));
3521 
      OUTS (outf, "+|-");
3522 
      OUTS (outf, dregs (src1));
3523 
      OUTS (outf, ",");
3524 
      OUTS (outf, dregs (dst0));
3525 
      OUTS (outf, "=");
3526 
      OUTS (outf, dregs (src0));
3527 
      OUTS (outf, "-|+");
3528 
      OUTS (outf, dregs (src1));
3529 
      amod0amod2 (s, x, aop, outf);
3530 
    }
3531 
  else if (aop == 0 && aopcde == 4)
3532 
    {
3533 
      OUTS (outf, dregs (dst0));
3534 
      OUTS (outf, "=");
3535 
      OUTS (outf, dregs (src0));
3536 
      OUTS (outf, "+");
3537 
      OUTS (outf, dregs (src1));
3538 
      OUTS (outf, " ");
3539 
      amod1 (s, x, outf);
3540 
    }
3541 
  else if (aop == 0 && aopcde == 0)
3542 
    {
3543 
      OUTS (outf, dregs (dst0));
3544 
      OUTS (outf, "=");
3545 
      OUTS (outf, dregs (src0));
3546 
      OUTS (outf, "+|+");
3547 
      OUTS (outf, dregs (src1));
3548 
      OUTS (outf, " ");
3549 
      amod0 (s, x, outf);
3550 
    }
3551 
  else if (aop == 0 && aopcde == 24)
3552 
    {
3553 
      OUTS (outf, dregs (dst0));
3554 
      OUTS (outf, "=BYTEPACK(");
3555 
      OUTS (outf, dregs (src0));
3556 
      OUTS (outf, ",");
3557 
      OUTS (outf, dregs (src1));
3558 
      OUTS (outf, ")");
3559 
    }
3560 
  else if (aop == 1 && aopcde == 24)
3561 
    {
3562 
      OUTS (outf, "(");
3563 
      OUTS (outf, dregs (dst1));
3564 
      OUTS (outf, ",");
3565 
      OUTS (outf, dregs (dst0));
3566 
      OUTS (outf, ") = BYTEUNPACK ");
3567 
      OUTS (outf, dregs (src0 + 1));
3568 
      OUTS (outf, ":");
3569 
      OUTS (outf, imm5 (src0));
3570 
      OUTS (outf, " ");
3571 
      aligndir (s, outf);
3572 
    }
3573 
  else if (aopcde == 13)
3574 
    {
3575 
      OUTS (outf, "(");
3576 
      OUTS (outf, dregs (dst1));
3577 
      OUTS (outf, ",");
3578 
      OUTS (outf, dregs (dst0));
3579 
      OUTS (outf, ") = SEARCH ");
3580 
      OUTS (outf, dregs (src0));
3581 
      OUTS (outf, "(");
3582 
      searchmod (aop, outf);
3583 
      OUTS (outf, ")");
3584 
    }
3585 
  else
3586 
    return 0;
3587 
 
3588 
  return 4;
3589 
}
3590 
 
3591 
static int
3592 
decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3593 
{
3594 
  /* dsp32shift
3595 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3596 
     | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
3597 
     |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
3598 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
3599 
  int HLs  = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask);
3600 
  int sop  = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask);
3601 
  int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask);
3602 
  int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask);
3603 
  int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask);
3604 
  int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask);
3605 
  const char *acc01 = (HLs & 1) == 0 ? "A0" : "A1";
3606 
 
3607 
  if (HLs == 0 && sop == 0 && sopcde == 0)
3608 
    {
3609 
      OUTS (outf, dregs_lo (dst0));
3610 
      OUTS (outf, "= ASHIFT ");
3611 
      OUTS (outf, dregs_lo (src1));
3612 
      OUTS (outf, " BY ");
3613 
      OUTS (outf, dregs_lo (src0));
3614 
    }
3615 
  else if (HLs == 1 && sop == 0 && sopcde == 0)
3616 
    {
3617 
      OUTS (outf, dregs_lo (dst0));
3618 
      OUTS (outf, "= ASHIFT ");
3619 
      OUTS (outf, dregs_hi (src1));
3620 
      OUTS (outf, " BY ");
3621 
      OUTS (outf, dregs_lo (src0));
3622 
    }
3623 
  else if (HLs == 2 && sop == 0 && sopcde == 0)
3624 
    {
3625 
      OUTS (outf, dregs_hi (dst0));
3626 
      OUTS (outf, "= ASHIFT ");
3627 
      OUTS (outf, dregs_lo (src1));
3628 
      OUTS (outf, " BY ");
3629 
      OUTS (outf, dregs_lo (src0));
3630 
    }
3631 
  else if (HLs == 3 && sop == 0 && sopcde == 0)
3632 
    {
3633 
      OUTS (outf, dregs_hi (dst0));
3634 
      OUTS (outf, "= ASHIFT ");
3635 
      OUTS (outf, dregs_hi (src1));
3636 
      OUTS (outf, " BY ");
3637 
      OUTS (outf, dregs_lo (src0));
3638 
    }
3639 
  else if (HLs == 0 && sop == 1 && sopcde == 0)
3640 
    {
3641 
      OUTS (outf, dregs_lo (dst0));
3642 
      OUTS (outf, "= ASHIFT ");
3643 
      OUTS (outf, dregs_lo (src1));
3644 
      OUTS (outf, " BY ");
3645 
      OUTS (outf, dregs_lo (src0));
3646 
      OUTS (outf, "(S)");
3647 
    }
3648 
  else if (HLs == 1 && sop == 1 && sopcde == 0)
3649 
    {
3650 
      OUTS (outf, dregs_lo (dst0));
3651 
      OUTS (outf, "= ASHIFT ");
3652 
      OUTS (outf, dregs_hi (src1));
3653 
      OUTS (outf, " BY ");
3654 
      OUTS (outf, dregs_lo (src0));
3655 
      OUTS (outf, "(S)");
3656 
    }
3657 
  else if (HLs == 2 && sop == 1 && sopcde == 0)
3658 
    {
3659 
      OUTS (outf, dregs_hi (dst0));
3660 
      OUTS (outf, "= ASHIFT ");
3661 
      OUTS (outf, dregs_lo (src1));
3662 
      OUTS (outf, " BY ");
3663 
      OUTS (outf, dregs_lo (src0));
3664 
      OUTS (outf, "(S)");
3665 
    }
3666 
  else if (HLs == 3 && sop == 1 && sopcde == 0)
3667 
    {
3668 
      OUTS (outf, dregs_hi (dst0));
3669 
      OUTS (outf, "= ASHIFT ");
3670 
      OUTS (outf, dregs_hi (src1));
3671 
      OUTS (outf, " BY ");
3672 
      OUTS (outf, dregs_lo (src0));
3673 
      OUTS (outf, "(S)");
3674 
    }
3675 
  else if (sop == 2 && sopcde == 0)
3676 
    {
3677 
      OUTS (outf, (HLs & 2) == 0 ? dregs_lo (dst0) : dregs_hi (dst0));
3678 
      OUTS (outf, "= LSHIFT ");
3679 
      OUTS (outf, (HLs & 1) == 0 ? dregs_lo (src1) : dregs_hi (src1));
3680 
      OUTS (outf, " BY ");
3681 
      OUTS (outf, dregs_lo (src0));
3682 
    }
3683 
  else if (sop == 0 && sopcde == 3)
3684 
    {
3685 
      OUTS (outf, acc01);
3686 
      OUTS (outf, "= ASHIFT ");
3687 
      OUTS (outf, acc01);
3688 
      OUTS (outf, " BY ");
3689 
      OUTS (outf, dregs_lo (src0));
3690 
    }
3691 
  else if (sop == 1 && sopcde == 3)
3692 
    {
3693 
      OUTS (outf, acc01);
3694 
      OUTS (outf, "= LSHIFT ");
3695 
      OUTS (outf, acc01);
3696 
      OUTS (outf, " BY ");
3697 
      OUTS (outf, dregs_lo (src0));
3698 
    }
3699 
  else if (sop == 2 && sopcde == 3)
3700 
    {
3701 
      OUTS (outf, acc01);
3702 
      OUTS (outf, "= ROT ");
3703 
      OUTS (outf, acc01);
3704 
      OUTS (outf, " BY ");
3705 
      OUTS (outf, dregs_lo (src0));
3706 
    }
3707 
  else if (sop == 3 && sopcde == 3)
3708 
    {
3709 
      OUTS (outf, dregs (dst0));
3710 
      OUTS (outf, "= ROT ");
3711 
      OUTS (outf, dregs (src1));
3712 
      OUTS (outf, " BY ");
3713 
      OUTS (outf, dregs_lo (src0));
3714 
    }
3715 
  else if (sop == 1 && sopcde == 1)
3716 
    {
3717 
      OUTS (outf, dregs (dst0));
3718 
      OUTS (outf, "= ASHIFT ");
3719 
      OUTS (outf, dregs (src1));
3720 
      OUTS (outf, " BY ");
3721 
      OUTS (outf, dregs_lo (src0));
3722 
      OUTS (outf, "(V,S)");
3723 
    }
3724 
  else if (sop == 0 && sopcde == 1)
3725 
    {
3726 
      OUTS (outf, dregs (dst0));
3727 
      OUTS (outf, "= ASHIFT ");
3728 
      OUTS (outf, dregs (src1));
3729 
      OUTS (outf, " BY ");
3730 
      OUTS (outf, dregs_lo (src0));
3731 
      OUTS (outf, "(V)");
3732 
    }
3733 
  else if (sop == 0 && sopcde == 2)
3734 
    {
3735 
      OUTS (outf, dregs (dst0));
3736 
      OUTS (outf, "= ASHIFT ");
3737 
      OUTS (outf, dregs (src1));
3738 
      OUTS (outf, " BY ");
3739 
      OUTS (outf, dregs_lo (src0));
3740 
    }
3741 
  else if (sop == 1 && sopcde == 2)
3742 
    {
3743 
      OUTS (outf, dregs (dst0));
3744 
      OUTS (outf, "= ASHIFT ");
3745 
      OUTS (outf, dregs (src1));
3746 
      OUTS (outf, " BY ");
3747 
      OUTS (outf, dregs_lo (src0));
3748 
      OUTS (outf, "(S)");
3749 
    }
3750 
  else if (sop == 2 && sopcde == 2)
3751 
    {
3752 
      OUTS (outf, dregs (dst0));
3753 
      OUTS (outf, "=SHIFT ");
3754 
      OUTS (outf, dregs (src1));
3755 
      OUTS (outf, " BY ");
3756 
      OUTS (outf, dregs_lo (src0));
3757 
    }
3758 
  else if (sop == 3 && sopcde == 2)
3759 
    {
3760 
      OUTS (outf, dregs (dst0));
3761 
      OUTS (outf, "= ROT ");
3762 
      OUTS (outf, dregs (src1));
3763 
      OUTS (outf, " BY ");
3764 
      OUTS (outf, dregs_lo (src0));
3765 
    }
3766 
  else if (sop == 2 && sopcde == 1)
3767 
    {
3768 
      OUTS (outf, dregs (dst0));
3769 
      OUTS (outf, "=SHIFT ");
3770 
      OUTS (outf, dregs (src1));
3771 
      OUTS (outf, " BY ");
3772 
      OUTS (outf, dregs_lo (src0));
3773 
      OUTS (outf, "(V)");
3774 
    }
3775 
  else if (sop == 0 && sopcde == 4)
3776 
    {
3777 
      OUTS (outf, dregs (dst0));
3778 
      OUTS (outf, "=PACK");
3779 
      OUTS (outf, "(");
3780 
      OUTS (outf, dregs_lo (src1));
3781 
      OUTS (outf, ",");
3782 
      OUTS (outf, dregs_lo (src0));
3783 
      OUTS (outf, ")");
3784 
    }
3785 
  else if (sop == 1 && sopcde == 4)
3786 
    {
3787 
      OUTS (outf, dregs (dst0));
3788 
      OUTS (outf, "=PACK(");
3789 
      OUTS (outf, dregs_lo (src1));
3790 
      OUTS (outf, ",");
3791 
      OUTS (outf, dregs_hi (src0));
3792 
      OUTS (outf, ")");
3793 
    }
3794 
  else if (sop == 2 && sopcde == 4)
3795 
    {
3796 
      OUTS (outf, dregs (dst0));
3797 
      OUTS (outf, "=PACK(");
3798 
      OUTS (outf, dregs_hi (src1));
3799 
      OUTS (outf, ",");
3800 
      OUTS (outf, dregs_lo (src0));
3801 
      OUTS (outf, ")");
3802 
    }
3803 
  else if (sop == 3 && sopcde == 4)
3804 
    {
3805 
      OUTS (outf, dregs (dst0));
3806 
      OUTS (outf, "=PACK(");
3807 
      OUTS (outf, dregs_hi (src1));
3808 
      OUTS (outf, ",");
3809 
      OUTS (outf, dregs_hi (src0));
3810 
      OUTS (outf, ")");
3811 
    }
3812 
  else if (sop == 0 && sopcde == 5)
3813 
    {
3814 
      OUTS (outf, dregs_lo (dst0));
3815 
      OUTS (outf, "=SIGNBITS ");
3816 
      OUTS (outf, dregs (src1));
3817 
    }
3818 
  else if (sop == 1 && sopcde == 5)
3819 
    {
3820 
      OUTS (outf, dregs_lo (dst0));
3821 
      OUTS (outf, "=SIGNBITS ");
3822 
      OUTS (outf, dregs_lo (src1));
3823 
    }
3824 
  else if (sop == 2 && sopcde == 5)
3825 
    {
3826 
      OUTS (outf, dregs_lo (dst0));
3827 
      OUTS (outf, "=SIGNBITS ");
3828 
      OUTS (outf, dregs_hi (src1));
3829 
    }
3830 
  else if (sop == 0 && sopcde == 6)
3831 
    {
3832 
      OUTS (outf, dregs_lo (dst0));
3833 
      OUTS (outf, "=SIGNBITS A0");
3834 
    }
3835 
  else if (sop == 1 && sopcde == 6)
3836 
    {
3837 
      OUTS (outf, dregs_lo (dst0));
3838 
      OUTS (outf, "=SIGNBITS A1");
3839 
    }
3840 
  else if (sop == 3 && sopcde == 6)
3841 
    {
3842 
      OUTS (outf, dregs_lo (dst0));
3843 
      OUTS (outf, "=ONES ");
3844 
      OUTS (outf, dregs (src1));
3845 
    }
3846 
  else if (sop == 0 && sopcde == 7)
3847 
    {
3848 
      OUTS (outf, dregs_lo (dst0));
3849 
      OUTS (outf, "=EXPADJ (");
3850 
      OUTS (outf, dregs (src1));
3851 
      OUTS (outf, ",");
3852 
      OUTS (outf, dregs_lo (src0));
3853 
      OUTS (outf, ")");
3854 
    }
3855 
  else if (sop == 1 && sopcde == 7)
3856 
    {
3857 
      OUTS (outf, dregs_lo (dst0));
3858 
      OUTS (outf, "=EXPADJ (");
3859 
      OUTS (outf, dregs (src1));
3860 
      OUTS (outf, ",");
3861 
      OUTS (outf, dregs_lo (src0));
3862 
      OUTS (outf, ") (V)");
3863 
    }
3864 
  else if (sop == 2 && sopcde == 7)
3865 
    {
3866 
      OUTS (outf, dregs_lo (dst0));
3867 
      OUTS (outf, "=EXPADJ (");
3868 
      OUTS (outf, dregs_lo (src1));
3869 
      OUTS (outf, ",");
3870 
      OUTS (outf, dregs_lo (src0));
3871 
      OUTS (outf, ")");
3872 
    }
3873 
  else if (sop == 3 && sopcde == 7)
3874 
    {
3875 
      OUTS (outf, dregs_lo (dst0));
3876 
      OUTS (outf, "=EXPADJ (");
3877 
      OUTS (outf, dregs_hi (src1));
3878 
      OUTS (outf, ",");
3879 
      OUTS (outf, dregs_lo (src0));
3880 
      OUTS (outf, ")");
3881 
    }
3882 
  else if (sop == 0 && sopcde == 8)
3883 
    {
3884 
      OUTS (outf, "BITMUX (");
3885 
      OUTS (outf, dregs (src0));
3886 
      OUTS (outf, ",");
3887 
      OUTS (outf, dregs (src1));
3888 
      OUTS (outf, ",A0 )(ASR)");
3889 
    }
3890 
  else if (sop == 1 && sopcde == 8)
3891 
    {
3892 
      OUTS (outf, "BITMUX (");
3893 
      OUTS (outf, dregs (src0));
3894 
      OUTS (outf, ",");
3895 
      OUTS (outf, dregs (src1));
3896 
      OUTS (outf, ",A0 )(ASL)");
3897 
    }
3898 
  else if (sop == 0 && sopcde == 9)
3899 
    {
3900 
      OUTS (outf, dregs_lo (dst0));
3901 
      OUTS (outf, "=VIT_MAX (");
3902 
      OUTS (outf, dregs (src1));
3903 
      OUTS (outf, ") (ASL)");
3904 
    }
3905 
  else if (sop == 1 && sopcde == 9)
3906 
    {
3907 
      OUTS (outf, dregs_lo (dst0));
3908 
      OUTS (outf, "=VIT_MAX (");
3909 
      OUTS (outf, dregs (src1));
3910 
      OUTS (outf, ") (ASR)");
3911 
    }
3912 
  else if (sop == 2 && sopcde == 9)
3913 
    {
3914 
      OUTS (outf, dregs (dst0));
3915 
      OUTS (outf, "=VIT_MAX(");
3916 
      OUTS (outf, dregs (src1));
3917 
      OUTS (outf, ",");
3918 
      OUTS (outf, dregs (src0));
3919 
      OUTS (outf, ")(ASL)");
3920 
    }
3921 
  else if (sop == 3 && sopcde == 9)
3922 
    {
3923 
      OUTS (outf, dregs (dst0));
3924 
      OUTS (outf, "=VIT_MAX(");
3925 
      OUTS (outf, dregs (src1));
3926 
      OUTS (outf, ",");
3927 
      OUTS (outf, dregs (src0));
3928 
      OUTS (outf, ")(ASR)");
3929 
    }
3930 
  else if (sop == 0 && sopcde == 10)
3931 
    {
3932 
      OUTS (outf, dregs (dst0));
3933 
      OUTS (outf, "=EXTRACT(");
3934 
      OUTS (outf, dregs (src1));
3935 
      OUTS (outf, ",");
3936 
      OUTS (outf, dregs_lo (src0));
3937 
      OUTS (outf, ") (Z)");
3938 
    }
3939 
  else if (sop == 1 && sopcde == 10)
3940 
    {
3941 
      OUTS (outf, dregs (dst0));
3942 
      OUTS (outf, "=EXTRACT(");
3943 
      OUTS (outf, dregs (src1));
3944 
      OUTS (outf, ",");
3945 
      OUTS (outf, dregs_lo (src0));
3946 
      OUTS (outf, ")(X)");
3947 
    }
3948 
  else if (sop == 2 && sopcde == 10)
3949 
    {
3950 
      OUTS (outf, dregs (dst0));
3951 
      OUTS (outf, "=DEPOSIT(");
3952 
      OUTS (outf, dregs (src1));
3953 
      OUTS (outf, ",");
3954 
      OUTS (outf, dregs (src0));
3955 
      OUTS (outf, ")");
3956 
    }
3957 
  else if (sop == 3 && sopcde == 10)
3958 
    {
3959 
      OUTS (outf, dregs (dst0));
3960 
      OUTS (outf, "=DEPOSIT(");
3961 
      OUTS (outf, dregs (src1));
3962 
      OUTS (outf, ",");
3963 
      OUTS (outf, dregs (src0));
3964 
      OUTS (outf, ")(X)");
3965 
    }
3966 
  else if (sop == 0 && sopcde == 11)
3967 
    {
3968 
      OUTS (outf, dregs_lo (dst0));
3969 
      OUTS (outf, "=CC=BXORSHIFT(A0,");
3970 
      OUTS (outf, dregs (src0));
3971 
      OUTS (outf, ")");
3972 
    }
3973 
  else if (sop == 1 && sopcde == 11)
3974 
    {
3975 
      OUTS (outf, dregs_lo (dst0));
3976 
      OUTS (outf, "=CC=BXOR(A0,");
3977 
      OUTS (outf, dregs (src0));
3978 
      OUTS (outf, ")");
3979 
    }
3980 
  else if (sop == 0 && sopcde == 12)
3981 
    OUTS (outf, "A0=BXORSHIFT(A0,A1 ,CC)");
3982 
 
3983 
  else if (sop == 1 && sopcde == 12)
3984 
    {
3985 
      OUTS (outf, dregs_lo (dst0));
3986 
      OUTS (outf, "=CC=BXOR( A0,A1 ,CC )");
3987 
    }
3988 
  else if (sop == 0 && sopcde == 13)
3989 
    {
3990 
      OUTS (outf, dregs (dst0));
3991 
      OUTS (outf, "=ALIGN8(");
3992 
      OUTS (outf, dregs (src1));
3993 
      OUTS (outf, ",");
3994 
      OUTS (outf, dregs (src0));
3995 
      OUTS (outf, ")");
3996 
    }
3997 
  else if (sop == 1 && sopcde == 13)
3998 
    {
3999 
      OUTS (outf, dregs (dst0));
4000 
      OUTS (outf, "=ALIGN16(");
4001 
      OUTS (outf, dregs (src1));
4002 
      OUTS (outf, ",");
4003 
      OUTS (outf, dregs (src0));
4004 
      OUTS (outf, ")");
4005 
    }
4006 
  else if (sop == 2 && sopcde == 13)
4007 
    {
4008 
      OUTS (outf, dregs (dst0));
4009 
      OUTS (outf, "=ALIGN24(");
4010 
      OUTS (outf, dregs (src1));
4011 
      OUTS (outf, ",");
4012 
      OUTS (outf, dregs (src0));
4013 
      OUTS (outf, ")");
4014 
    }
4015 
  else
4016 
    return 0;
4017 
 
4018 
  return 4;
4019 
}
4020 
 
4021 
static int
4022 
decode_dsp32shiftimm_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4023 
{
4024 
  /* dsp32shiftimm
4025 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4026 
     | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
4027 
     |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
4028 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
4029 
  int src1     = ((iw1 >> DSP32ShiftImm_src1_bits) & DSP32ShiftImm_src1_mask);
4030 
  int sop      = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask);
4031 
  int bit8     = ((iw1 >> 8) & 0x1);
4032 
  int immag    = ((iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4033 
  int newimmag = (-(iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4034 
  int dst0     = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask);
4035 
  int sopcde   = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask);
4036 
  int HLs      = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
4037 
 
4038 
 
4039 
  if (sop == 0 && sopcde == 0)
4040 
    {
4041 
      OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4042 
      OUTS (outf, " = ");
4043 
      OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4044 
      OUTS (outf, " >>> ");
4045 
      OUTS (outf, uimm4 (newimmag));
4046 
    }
4047 
  else if (sop == 1 && sopcde == 0 && bit8 == 0)
4048 
    {
4049 
      OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4050 
      OUTS (outf, " = ");
4051 
      OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4052 
      OUTS (outf, " << ");
4053 
      OUTS (outf, uimm4 (immag));
4054 
      OUTS (outf, " (S)");
4055 
    }
4056 
  else if (sop == 1 && sopcde == 0 && bit8 == 1)
4057 
    {
4058 
      OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4059 
      OUTS (outf, " = ");
4060 
      OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4061 
      OUTS (outf, " >>> ");
4062 
      OUTS (outf, uimm4 (newimmag));
4063 
      OUTS (outf, " (S)");
4064 
    }
4065 
  else if (sop == 2 && sopcde == 0 && bit8 == 0)
4066 
    {
4067 
      OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4068 
      OUTS (outf, " = ");
4069 
      OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4070 
      OUTS (outf, " << ");
4071 
      OUTS (outf, uimm4 (immag));
4072 
    }
4073 
  else if (sop == 2 && sopcde == 0 && bit8 == 1)
4074 
    {
4075 
      OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4076 
      OUTS (outf, " = ");
4077 
      OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4078 
      OUTS (outf, " >> ");
4079 
      OUTS (outf, uimm4 (newimmag));
4080 
    }
4081 
  else if (sop == 2 && sopcde == 3 && HLs == 1)
4082 
    {
4083 
      OUTS (outf, "A1= ROT A1 BY ");
4084 
      OUTS (outf, imm6 (immag));
4085 
    }
4086 
  else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0)
4087 
    {
4088 
      OUTS (outf, "A0=A0<<");
4089 
      OUTS (outf, uimm5 (immag));
4090 
    }
4091 
  else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1)
4092 
    {
4093 
      OUTS (outf, "A0=A0>>>");
4094 
      OUTS (outf, uimm5 (newimmag));
4095 
    }
4096 
  else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0)
4097 
    {
4098 
      OUTS (outf, "A1=A1<<");
4099 
      OUTS (outf, uimm5 (immag));
4100 
    }
4101 
  else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1)
4102 
    {
4103 
      OUTS (outf, "A1=A1>>>");
4104 
      OUTS (outf, uimm5 (newimmag));
4105 
    }
4106 
  else if (sop == 1 && sopcde == 3 && HLs == 0)
4107 
    {
4108 
      OUTS (outf, "A0=A0>>");
4109 
      OUTS (outf, uimm5 (newimmag));
4110 
    }
4111 
  else if (sop == 1 && sopcde == 3 && HLs == 1)
4112 
    {
4113 
      OUTS (outf, "A1=A1>>");
4114 
      OUTS (outf, uimm5 (newimmag));
4115 
    }
4116 
  else if (sop == 2 && sopcde == 3 && HLs == 0)
4117 
    {
4118 
      OUTS (outf, "A0= ROT A0 BY ");
4119 
      OUTS (outf, imm6 (immag));
4120 
    }
4121 
  else if (sop == 1 && sopcde == 1 && bit8 == 0)
4122 
    {
4123 
      OUTS (outf, dregs (dst0));
4124 
      OUTS (outf, "=");
4125 
      OUTS (outf, dregs (src1));
4126 
      OUTS (outf, "<<");
4127 
      OUTS (outf, uimm5 (immag));
4128 
      OUTS (outf, " (V, S)");
4129 
    }
4130 
  else if (sop == 1 && sopcde == 1 && bit8 == 1)
4131 
    {
4132 
      OUTS (outf, dregs (dst0));
4133 
      OUTS (outf, "=");
4134 
      OUTS (outf, dregs (src1));
4135 
      OUTS (outf, ">>>");
4136 
      OUTS (outf, imm5 (-immag));
4137 
      OUTS (outf, " (V)");
4138 
    }
4139 
  else if (sop == 2 && sopcde == 1 && bit8 == 1)
4140 
    {
4141 
      OUTS (outf, dregs (dst0));
4142 
      OUTS (outf, "=");
4143 
      OUTS (outf, dregs (src1));
4144 
      OUTS (outf, " >> ");
4145 
      OUTS (outf, uimm5 (newimmag));
4146 
      OUTS (outf, " (V)");
4147 
    }
4148 
  else if (sop == 2 && sopcde == 1 && bit8 == 0)
4149 
    {
4150 
      OUTS (outf, dregs (dst0));
4151 
      OUTS (outf, "=");
4152 
      OUTS (outf, dregs (src1));
4153 
      OUTS (outf, "<<");
4154 
      OUTS (outf, imm5 (immag));
4155 
      OUTS (outf, " (V)");
4156 
    }
4157 
  else if (sop == 0 && sopcde == 1)
4158 
    {
4159 
      OUTS (outf, dregs (dst0));
4160 
      OUTS (outf, "=");
4161 
      OUTS (outf, dregs (src1));
4162 
      OUTS (outf, ">>>");
4163 
      OUTS (outf, uimm5 (newimmag));
4164 
      OUTS (outf, " (V)");
4165 
    }
4166 
  else if (sop == 1 && sopcde == 2)
4167 
    {
4168 
      OUTS (outf, dregs (dst0));
4169 
      OUTS (outf, "=");
4170 
      OUTS (outf, dregs (src1));
4171 
      OUTS (outf, "<<");
4172 
      OUTS (outf, uimm5 (immag));
4173 
      OUTS (outf, "(S)");
4174 
    }
4175 
  else if (sop == 2 && sopcde == 2 && bit8 == 1)
4176 
    {
4177 
      OUTS (outf, dregs (dst0));
4178 
      OUTS (outf, "=");
4179 
      OUTS (outf, dregs (src1));
4180 
      OUTS (outf, ">>");
4181 
      OUTS (outf, uimm5 (newimmag));
4182 
    }
4183 
  else if (sop == 2 && sopcde == 2 && bit8 == 0)
4184 
    {
4185 
      OUTS (outf, dregs (dst0));
4186 
      OUTS (outf, "=");
4187 
      OUTS (outf, dregs (src1));
4188 
      OUTS (outf, "<<");
4189 
      OUTS (outf, uimm5 (immag));
4190 
    }
4191 
  else if (sop == 3 && sopcde == 2)
4192 
    {
4193 
      OUTS (outf, dregs (dst0));
4194 
      OUTS (outf, "= ROT ");
4195 
      OUTS (outf, dregs (src1));
4196 
      OUTS (outf, " BY ");
4197 
      OUTS (outf, imm6 (immag));
4198 
    }
4199 
  else if (sop == 0 && sopcde == 2)
4200 
    {
4201 
      OUTS (outf, dregs (dst0));
4202 
      OUTS (outf, "=");
4203 
      OUTS (outf, dregs (src1));
4204 
      OUTS (outf, ">>>");
4205 
      OUTS (outf, uimm5 (newimmag));
4206 
    }
4207 
  else
4208 
    return 0;
4209 
 
4210 
  return 4;
4211 
}
4212 
 
4213 
static int
4214 
decode_pseudoDEBUG_0 (TIword iw0, disassemble_info *outf)
4215 
{
4216 
  /* pseudoDEBUG
4217 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4218 
     | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
4219 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
4220 
  int fn  = ((iw0 >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask);
4221 
  int grp = ((iw0 >> PseudoDbg_grp_bits) & PseudoDbg_grp_mask);
4222 
  int reg = ((iw0 >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask);
4223 
 
4224 
  if (reg == 0 && fn == 3)
4225 
    OUTS (outf, "DBG A0");
4226 
 
4227 
  else if (reg == 1 && fn == 3)
4228 
    OUTS (outf, "DBG A1");
4229 
 
4230 
  else if (reg == 3 && fn == 3)
4231 
    OUTS (outf, "ABORT");
4232 
 
4233 
  else if (reg == 4 && fn == 3)
4234 
    OUTS (outf, "HLT");
4235 
 
4236 
  else if (reg == 5 && fn == 3)
4237 
    OUTS (outf, "DBGHALT");
4238 
 
4239 
  else if (reg == 6 && fn == 3)
4240 
    {
4241 
      OUTS (outf, "DBGCMPLX(");
4242 
      OUTS (outf, dregs (grp));
4243 
      OUTS (outf, ")");
4244 
    }
4245 
  else if (reg == 7 && fn == 3)
4246 
    OUTS (outf, "DBG");
4247 
 
4248 
  else if (grp == 0 && fn == 2)
4249 
    {
4250 
      OUTS (outf, "OUTC");
4251 
      OUTS (outf, dregs (reg));
4252 
    }
4253 
  else if (fn == 0)
4254 
    {
4255 
      OUTS (outf, "DBG");
4256 
      OUTS (outf, allregs (reg, grp));
4257 
    }
4258 
  else if (fn == 1)
4259 
    {
4260 
      OUTS (outf, "PRNT");
4261 
      OUTS (outf, allregs (reg, grp));
4262 
    }
4263 
  else
4264 
    return 0;
4265 
 
4266 
  return 2;
4267 
}
4268 
 
4269 
static int
4270 
decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4271 
{
4272 
  /* pseudodbg_assert
4273 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4274 
     | 1 | 1 | 1 | 1 | 0 | - | - | - | - | - |.dbgop.....|.regtest...|
4275 
     |.expected......................................................|
4276 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
4277 
  int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
4278 
  int dbgop    = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask);
4279 
  int regtest  = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask);
4280 
 
4281 
  if (dbgop == 0)
4282 
    {
4283 
      OUTS (outf, "DBGA(");
4284 
      OUTS (outf, dregs_lo (regtest));
4285 
      OUTS (outf, ",");
4286 
      OUTS (outf, uimm16 (expected));
4287 
      OUTS (outf, ")");
4288 
    }
4289 
  else if (dbgop == 1)
4290 
    {
4291 
      OUTS (outf, "DBGA(");
4292 
      OUTS (outf, dregs_hi (regtest));
4293 
      OUTS (outf, ",");
4294 
      OUTS (outf, uimm16 (expected));
4295 
      OUTS (outf, ")");
4296 
    }
4297 
  else if (dbgop == 2)
4298 
    {
4299 
      OUTS (outf, "DBGAL(");
4300 
      OUTS (outf, dregs (regtest));
4301 
      OUTS (outf, ",");
4302 
      OUTS (outf, uimm16 (expected));
4303 
      OUTS (outf, ")");
4304 
    }
4305 
  else if (dbgop == 3)
4306 
    {
4307 
      OUTS (outf, "DBGAH(");
4308 
      OUTS (outf, dregs (regtest));
4309 
      OUTS (outf, ",");
4310 
      OUTS (outf, uimm16 (expected));
4311 
      OUTS (outf, ")");
4312 
    }
4313 
  else
4314 
    return 0;
4315 
  return 4;
4316 
}
4317 
 
4318 
int
4319 
_print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4320 
{
4321 
  bfd_byte buf[4];
4322 
  TIword iw0;
4323 
  TIword iw1;
4324 
  int status;
4325 
  int rv = 0;
4326 
 
4327 
  status = (*outf->read_memory_func) (pc & ~0x1, buf, 2, outf);
4328 
  status = (*outf->read_memory_func) ((pc + 2) & ~0x1, buf + 2, 2, outf);
4329 
 
4330 
  iw0 = bfd_getl16 (buf);
4331 
  iw1 = bfd_getl16 (buf + 2);
4332 
 
4333 
  if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800)
4334 
    {
4335 
      OUTS (outf, "mnop");
4336 
      return 4;
4337 
    }
4338 
  else if ((iw0 & 0xff00) == 0x0000)
4339 
    rv = decode_ProgCtrl_0 (iw0, outf);
4340 
  else if ((iw0 & 0xffc0) == 0x0240)
4341 
    rv = decode_CaCTRL_0 (iw0, outf);
4342 
  else if ((iw0 & 0xff80) == 0x0100)
4343 
    rv = decode_PushPopReg_0 (iw0, outf);
4344 
  else if ((iw0 & 0xfe00) == 0x0400)
4345 
    rv = decode_PushPopMultiple_0 (iw0, outf);
4346 
  else if ((iw0 & 0xfe00) == 0x0600)
4347 
    rv = decode_ccMV_0 (iw0, outf);
4348 
  else if ((iw0 & 0xf800) == 0x0800)
4349 
    rv = decode_CCflag_0 (iw0, outf);
4350 
  else if ((iw0 & 0xffe0) == 0x0200)
4351 
    rv = decode_CC2dreg_0 (iw0, outf);
4352 
  else if ((iw0 & 0xff00) == 0x0300)
4353 
    rv = decode_CC2stat_0 (iw0, outf);
4354 
  else if ((iw0 & 0xf000) == 0x1000)
4355 
    rv = decode_BRCC_0 (iw0, pc, outf);
4356 
  else if ((iw0 & 0xf000) == 0x2000)
4357 
    rv = decode_UJUMP_0 (iw0, pc, outf);
4358 
  else if ((iw0 & 0xf000) == 0x3000)
4359 
    rv = decode_REGMV_0 (iw0, outf);
4360 
  else if ((iw0 & 0xfc00) == 0x4000)
4361 
    rv = decode_ALU2op_0 (iw0, outf);
4362 
  else if ((iw0 & 0xfe00) == 0x4400)
4363 
    rv = decode_PTR2op_0 (iw0, outf);
4364 
  else if ((iw0 & 0xf800) == 0x4800)
4365 
    rv = decode_LOGI2op_0 (iw0, outf);
4366 
  else if ((iw0 & 0xf000) == 0x5000)
4367 
    rv = decode_COMP3op_0 (iw0, outf);
4368 
  else if ((iw0 & 0xf800) == 0x6000)
4369 
    rv = decode_COMPI2opD_0 (iw0, outf);
4370 
  else if ((iw0 & 0xf800) == 0x6800)
4371 
    rv = decode_COMPI2opP_0 (iw0, outf);
4372 
  else if ((iw0 & 0xf000) == 0x8000)
4373 
    rv = decode_LDSTpmod_0 (iw0, outf);
4374 
  else if ((iw0 & 0xff60) == 0x9e60)
4375 
    rv = decode_dagMODim_0 (iw0, outf);
4376 
  else if ((iw0 & 0xfff0) == 0x9f60)
4377 
    rv = decode_dagMODik_0 (iw0, outf);
4378 
  else if ((iw0 & 0xfc00) == 0x9c00)
4379 
    rv = decode_dspLDST_0 (iw0, outf);
4380 
  else if ((iw0 & 0xf000) == 0x9000)
4381 
    rv = decode_LDST_0 (iw0, outf);
4382 
  else if ((iw0 & 0xfc00) == 0xb800)
4383 
    rv = decode_LDSTiiFP_0 (iw0, outf);
4384 
  else if ((iw0 & 0xe000) == 0xA000)
4385 
    rv = decode_LDSTii_0 (iw0, outf);
4386 
  else if ((iw0 & 0xff80) == 0xe080 && (iw1 & 0x0C00) == 0x0000)
4387 
    rv = decode_LoopSetup_0 (iw0, iw1, pc, outf);
4388 
  else if ((iw0 & 0xff00) == 0xe100 && (iw1 & 0x0000) == 0x0000)
4389 
    rv = decode_LDIMMhalf_0 (iw0, iw1, outf);
4390 
  else if ((iw0 & 0xfe00) == 0xe200 && (iw1 & 0x0000) == 0x0000)
4391 
    rv = decode_CALLa_0 (iw0, iw1, pc, outf);
4392 
  else if ((iw0 & 0xfc00) == 0xe400 && (iw1 & 0x0000) == 0x0000)
4393 
    rv = decode_LDSTidxI_0 (iw0, iw1, outf);
4394 
  else if ((iw0 & 0xfffe) == 0xe800 && (iw1 & 0x0000) == 0x0000)
4395 
    rv = decode_linkage_0 (iw0, iw1, outf);
4396 
  else if ((iw0 & 0xf600) == 0xc000 && (iw1 & 0x0000) == 0x0000)
4397 
    rv = decode_dsp32mac_0 (iw0, iw1, outf);
4398 
  else if ((iw0 & 0xf600) == 0xc200 && (iw1 & 0x0000) == 0x0000)
4399 
    rv = decode_dsp32mult_0 (iw0, iw1, outf);
4400 
  else if ((iw0 & 0xf7c0) == 0xc400 && (iw1 & 0x0000) == 0x0000)
4401 
    rv = decode_dsp32alu_0 (iw0, iw1, outf);
4402 
  else if ((iw0 & 0xf780) == 0xc600 && (iw1 & 0x01c0) == 0x0000)
4403 
    rv = decode_dsp32shift_0 (iw0, iw1, outf);
4404 
  else if ((iw0 & 0xf780) == 0xc680 && (iw1 & 0x0000) == 0x0000)
4405 
    rv = decode_dsp32shiftimm_0 (iw0, iw1, outf);
4406 
  else if ((iw0 & 0xff00) == 0xf800)
4407 
    rv = decode_pseudoDEBUG_0 (iw0, outf);
4408 
#if 0
4409 
  else if ((iw0 & 0xFF00) == 0xF900)
4410 
    rv = decode_pseudoOChar_0 (iw0, iw1, pc, outf);
4411 
#endif
4412 
  else if ((iw0 & 0xFFC0) == 0xf000 && (iw1 & 0x0000) == 0x0000)
4413 
    rv = decode_pseudodbg_assert_0 (iw0, iw1, outf);
4414 
 
4415 
  return rv;
4416 
}
4417 
 
4418 
 
4419 
int
4420 
print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4421 
{
4422 
  bfd_byte buf[2];
4423 
  unsigned short iw0;
4424 
  int status;
4425 
  int count = 0;
4426 
 
4427 
  status = (*outf->read_memory_func) (pc & ~0x01, buf, 2, outf);
4428 
  iw0 = bfd_getl16 (buf);
4429 
 
4430 
  count += _print_insn_bfin (pc, outf);
4431 
 
4432 
  /* Proper display of multiple issue instructions.  */
4433 
 
4434 
  if ((iw0 & 0xc000) == 0xc000 && (iw0 & BIT_MULTI_INS)
4435 
      && ((iw0 & 0xe800) != 0xe800 /* Not Linkage.  */ ))
4436 
    {
4437 
      outf->fprintf_func (outf->stream, " || ");
4438 
      count += _print_insn_bfin (pc + 4, outf);
4439 
      outf->fprintf_func (outf->stream, " || ");
4440 
      count += _print_insn_bfin (pc + 6, outf);
4441 
    }
4442 
  if (count == 0)
4443 
    {
4444 
      outf->fprintf_func (outf->stream, "ILLEGAL");
4445 
      return 2;
4446 
    }
4447 
  outf->fprintf_func (outf->stream, ";");
4448 
  return count;
4449 
}

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