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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [opcodes/] [fr30-desc.h] - Blame information for rev 157

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1 24 jeremybenn
/* CPU data header for fr30.
2
 
3
THIS FILE IS MACHINE GENERATED WITH CGEN.
4
 
5
Copyright 1996-2007 Free Software Foundation, Inc.
6
 
7
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8
 
9
   This file is free software; you can redistribute it and/or modify
10
   it under the terms of the GNU General Public License as published by
11
   the Free Software Foundation; either version 3, or (at your option)
12
   any later version.
13
 
14
   It is distributed in the hope that it will be useful, but WITHOUT
15
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
17
   License for more details.
18
 
19
   You should have received a copy of the GNU General Public License along
20
   with this program; if not, write to the Free Software Foundation, Inc.,
21
   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
22
 
23
*/
24
 
25
#ifndef FR30_CPU_H
26
#define FR30_CPU_H
27
 
28
#include "opcode/cgen-bitset.h"
29
 
30
#define CGEN_ARCH fr30
31
 
32
/* Given symbol S, return fr30_cgen_<S>.  */
33
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
34
#define CGEN_SYM(s) fr30##_cgen_##s
35
#else
36
#define CGEN_SYM(s) fr30/**/_cgen_/**/s
37
#endif
38
 
39
 
40
/* Selected cpu families.  */
41
#define HAVE_CPU_FR30BF
42
 
43
#define CGEN_INSN_LSB0_P 0
44
 
45
/* Minimum size of any insn (in bytes).  */
46
#define CGEN_MIN_INSN_SIZE 2
47
 
48
/* Maximum size of any insn (in bytes).  */
49
#define CGEN_MAX_INSN_SIZE 6
50
 
51
#define CGEN_INT_INSN_P 0
52
 
53
/* Maximum number of syntax elements in an instruction.  */
54
#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 15
55
 
56
/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
57
   e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
58
   we can't hash on everything up to the space.  */
59
#define CGEN_MNEMONIC_OPERANDS
60
 
61
/* Maximum number of fields in an instruction.  */
62
#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 7
63
 
64
/* Enums.  */
65
 
66
/* Enum declaration for insn op1 enums.  */
67
typedef enum insn_op1 {
68
  OP1_0, OP1_1, OP1_2, OP1_3
69
 , OP1_4, OP1_5, OP1_6, OP1_7
70
 , OP1_8, OP1_9, OP1_A, OP1_B
71
 , OP1_C, OP1_D, OP1_E, OP1_F
72
} INSN_OP1;
73
 
74
/* Enum declaration for insn op2 enums.  */
75
typedef enum insn_op2 {
76
  OP2_0, OP2_1, OP2_2, OP2_3
77
 , OP2_4, OP2_5, OP2_6, OP2_7
78
 , OP2_8, OP2_9, OP2_A, OP2_B
79
 , OP2_C, OP2_D, OP2_E, OP2_F
80
} INSN_OP2;
81
 
82
/* Enum declaration for insn op3 enums.  */
83
typedef enum insn_op3 {
84
  OP3_0, OP3_1, OP3_2, OP3_3
85
 , OP3_4, OP3_5, OP3_6, OP3_7
86
 , OP3_8, OP3_9, OP3_A, OP3_B
87
 , OP3_C, OP3_D, OP3_E, OP3_F
88
} INSN_OP3;
89
 
90
/* Enum declaration for insn op4 enums.  */
91
typedef enum insn_op4 {
92
  OP4_0
93
} INSN_OP4;
94
 
95
/* Enum declaration for insn op5 enums.  */
96
typedef enum insn_op5 {
97
  OP5_0, OP5_1
98
} INSN_OP5;
99
 
100
/* Enum declaration for insn cc enums.  */
101
typedef enum insn_cc {
102
  CC_RA, CC_NO, CC_EQ, CC_NE
103
 , CC_C, CC_NC, CC_N, CC_P
104
 , CC_V, CC_NV, CC_LT, CC_GE
105
 , CC_LE, CC_GT, CC_LS, CC_HI
106
} INSN_CC;
107
 
108
/* Enum declaration for .  */
109
typedef enum gr_names {
110
  H_GR_R0 = 0, H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3
111
 , H_GR_R4 = 4, H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7
112
 , H_GR_R8 = 8, H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11
113
 , H_GR_R12 = 12, H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15
114
 , H_GR_AC = 13, H_GR_FP = 14, H_GR_SP = 15
115
} GR_NAMES;
116
 
117
/* Enum declaration for .  */
118
typedef enum cr_names {
119
  H_CR_CR0, H_CR_CR1, H_CR_CR2, H_CR_CR3
120
 , H_CR_CR4, H_CR_CR5, H_CR_CR6, H_CR_CR7
121
 , H_CR_CR8, H_CR_CR9, H_CR_CR10, H_CR_CR11
122
 , H_CR_CR12, H_CR_CR13, H_CR_CR14, H_CR_CR15
123
} CR_NAMES;
124
 
125
/* Enum declaration for .  */
126
typedef enum dr_names {
127
  H_DR_TBR, H_DR_RP, H_DR_SSP, H_DR_USP
128
 , H_DR_MDH, H_DR_MDL
129
} DR_NAMES;
130
 
131
/* Attributes.  */
132
 
133
/* Enum declaration for machine type selection.  */
134
typedef enum mach_attr {
135
  MACH_BASE, MACH_FR30, MACH_MAX
136
} MACH_ATTR;
137
 
138
/* Enum declaration for instruction set selection.  */
139
typedef enum isa_attr {
140
  ISA_FR30, ISA_MAX
141
} ISA_ATTR;
142
 
143
/* Number of architecture variants.  */
144
#define MAX_ISAS  1
145
#define MAX_MACHS ((int) MACH_MAX)
146
 
147
/* Ifield support.  */
148
 
149
/* Ifield attribute indices.  */
150
 
151
/* Enum declaration for cgen_ifld attrs.  */
152
typedef enum cgen_ifld_attr {
153
  CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
154
 , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
155
 , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
156
} CGEN_IFLD_ATTR;
157
 
158
/* Number of non-boolean elements in cgen_ifld_attr.  */
159
#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
160
 
161
/* cgen_ifld attribute accessor macros.  */
162
#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
163
#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
164
#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
165
#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
166
#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
167
#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
168
#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
169
 
170
/* Enum declaration for fr30 ifield types.  */
171
typedef enum ifield_type {
172
  FR30_F_NIL, FR30_F_ANYOF, FR30_F_OP1, FR30_F_OP2
173
 , FR30_F_OP3, FR30_F_OP4, FR30_F_OP5, FR30_F_CC
174
 , FR30_F_CCC, FR30_F_RJ, FR30_F_RI, FR30_F_RS1
175
 , FR30_F_RS2, FR30_F_RJC, FR30_F_RIC, FR30_F_CRJ
176
 , FR30_F_CRI, FR30_F_U4, FR30_F_U4C, FR30_F_I4
177
 , FR30_F_M4, FR30_F_U8, FR30_F_I8, FR30_F_I20_4
178
 , FR30_F_I20_16, FR30_F_I20, FR30_F_I32, FR30_F_UDISP6
179
 , FR30_F_DISP8, FR30_F_DISP9, FR30_F_DISP10, FR30_F_S10
180
 , FR30_F_U10, FR30_F_REL9, FR30_F_DIR8, FR30_F_DIR9
181
 , FR30_F_DIR10, FR30_F_REL12, FR30_F_REGLIST_HI_ST, FR30_F_REGLIST_LOW_ST
182
 , FR30_F_REGLIST_HI_LD, FR30_F_REGLIST_LOW_LD, FR30_F_MAX
183
} IFIELD_TYPE;
184
 
185
#define MAX_IFLD ((int) FR30_F_MAX)
186
 
187
/* Hardware attribute indices.  */
188
 
189
/* Enum declaration for cgen_hw attrs.  */
190
typedef enum cgen_hw_attr {
191
  CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
192
 , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
193
} CGEN_HW_ATTR;
194
 
195
/* Number of non-boolean elements in cgen_hw_attr.  */
196
#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
197
 
198
/* cgen_hw attribute accessor macros.  */
199
#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
200
#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
201
#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
202
#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
203
#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
204
 
205
/* Enum declaration for fr30 hardware types.  */
206
typedef enum cgen_hw_type {
207
  HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
208
 , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_CR
209
 , HW_H_DR, HW_H_PS, HW_H_R13, HW_H_R14
210
 , HW_H_R15, HW_H_NBIT, HW_H_ZBIT, HW_H_VBIT
211
 , HW_H_CBIT, HW_H_IBIT, HW_H_SBIT, HW_H_TBIT
212
 , HW_H_D0BIT, HW_H_D1BIT, HW_H_CCR, HW_H_SCR
213
 , HW_H_ILM, HW_MAX
214
} CGEN_HW_TYPE;
215
 
216
#define MAX_HW ((int) HW_MAX)
217
 
218
/* Operand attribute indices.  */
219
 
220
/* Enum declaration for cgen_operand attrs.  */
221
typedef enum cgen_operand_attr {
222
  CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
223
 , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
224
 , CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH
225
 , CGEN_OPERAND_END_NBOOLS
226
} CGEN_OPERAND_ATTR;
227
 
228
/* Number of non-boolean elements in cgen_operand_attr.  */
229
#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
230
 
231
/* cgen_operand attribute accessor macros.  */
232
#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
233
#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
234
#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
235
#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
236
#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
237
#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
238
#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
239
#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
240
#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
241
#define CGEN_ATTR_CGEN_OPERAND_HASH_PREFIX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_HASH_PREFIX)) != 0)
242
 
243
/* Enum declaration for fr30 operand types.  */
244
typedef enum cgen_operand_type {
245
  FR30_OPERAND_PC, FR30_OPERAND_RI, FR30_OPERAND_RJ, FR30_OPERAND_RIC
246
 , FR30_OPERAND_RJC, FR30_OPERAND_CRI, FR30_OPERAND_CRJ, FR30_OPERAND_RS1
247
 , FR30_OPERAND_RS2, FR30_OPERAND_R13, FR30_OPERAND_R14, FR30_OPERAND_R15
248
 , FR30_OPERAND_PS, FR30_OPERAND_U4, FR30_OPERAND_U4C, FR30_OPERAND_U8
249
 , FR30_OPERAND_I8, FR30_OPERAND_UDISP6, FR30_OPERAND_DISP8, FR30_OPERAND_DISP9
250
 , FR30_OPERAND_DISP10, FR30_OPERAND_S10, FR30_OPERAND_U10, FR30_OPERAND_I32
251
 , FR30_OPERAND_M4, FR30_OPERAND_I20, FR30_OPERAND_DIR8, FR30_OPERAND_DIR9
252
 , FR30_OPERAND_DIR10, FR30_OPERAND_LABEL9, FR30_OPERAND_LABEL12, FR30_OPERAND_REGLIST_LOW_LD
253
 , FR30_OPERAND_REGLIST_HI_LD, FR30_OPERAND_REGLIST_LOW_ST, FR30_OPERAND_REGLIST_HI_ST, FR30_OPERAND_CC
254
 , FR30_OPERAND_CCC, FR30_OPERAND_NBIT, FR30_OPERAND_VBIT, FR30_OPERAND_ZBIT
255
 , FR30_OPERAND_CBIT, FR30_OPERAND_IBIT, FR30_OPERAND_SBIT, FR30_OPERAND_TBIT
256
 , FR30_OPERAND_D0BIT, FR30_OPERAND_D1BIT, FR30_OPERAND_CCR, FR30_OPERAND_SCR
257
 , FR30_OPERAND_ILM, FR30_OPERAND_MAX
258
} CGEN_OPERAND_TYPE;
259
 
260
/* Number of operands types.  */
261
#define MAX_OPERANDS 49
262
 
263
/* Maximum number of operands referenced by any insn.  */
264
#define MAX_OPERAND_INSTANCES 8
265
 
266
/* Insn attribute indices.  */
267
 
268
/* Enum declaration for cgen_insn attrs.  */
269
typedef enum cgen_insn_attr {
270
  CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
271
 , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
272
 , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_NOT_IN_DELAY_SLOT, CGEN_INSN_END_BOOLS
273
 , CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
274
} CGEN_INSN_ATTR;
275
 
276
/* Number of non-boolean elements in cgen_insn_attr.  */
277
#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
278
 
279
/* cgen_insn attribute accessor macros.  */
280
#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
281
#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
282
#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
283
#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
284
#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
285
#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
286
#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
287
#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
288
#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
289
#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
290
#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
291
#define CGEN_ATTR_CGEN_INSN_NOT_IN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NOT_IN_DELAY_SLOT)) != 0)
292
 
293
/* cgen.h uses things we just defined.  */
294
#include "opcode/cgen.h"
295
 
296
extern const struct cgen_ifld fr30_cgen_ifld_table[];
297
 
298
/* Attributes.  */
299
extern const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[];
300
extern const CGEN_ATTR_TABLE fr30_cgen_ifield_attr_table[];
301
extern const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[];
302
extern const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[];
303
 
304
/* Hardware decls.  */
305
 
306
extern CGEN_KEYWORD fr30_cgen_opval_gr_names;
307
extern CGEN_KEYWORD fr30_cgen_opval_cr_names;
308
extern CGEN_KEYWORD fr30_cgen_opval_dr_names;
309
extern CGEN_KEYWORD fr30_cgen_opval_h_ps;
310
extern CGEN_KEYWORD fr30_cgen_opval_h_r13;
311
extern CGEN_KEYWORD fr30_cgen_opval_h_r14;
312
extern CGEN_KEYWORD fr30_cgen_opval_h_r15;
313
 
314
extern const CGEN_HW_ENTRY fr30_cgen_hw_table[];
315
 
316
 
317
 
318
#endif /* FR30_CPU_H */

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