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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [opcodes/] [i386-opc.h] - Blame information for rev 24

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1 24 jeremybenn
/* Declarations for Intel 80386 opcode table
2
   Copyright 2007, 2008
3
   Free Software Foundation, Inc.
4
 
5
   This file is part of the GNU opcodes library.
6
 
7
   This library is free software; you can redistribute it and/or modify
8
   it under the terms of the GNU General Public License as published by
9
   the Free Software Foundation; either version 3, or (at your option)
10
   any later version.
11
 
12
   It is distributed in the hope that it will be useful, but WITHOUT
13
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15
   License for more details.
16
 
17
   You should have received a copy of the GNU General Public License
18
   along with GAS; see the file COPYING.  If not, write to the Free
19
   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20
   02110-1301, USA.  */
21
 
22
#include "opcode/i386.h"
23
#ifdef HAVE_LIMITS_H
24
#include <limits.h>
25
#endif
26
 
27
#ifndef CHAR_BIT
28
#define CHAR_BIT 8
29
#endif
30
 
31
/* Position of cpu flags bitfiled.  */
32
 
33
/* i186 or better required */
34
#define Cpu186          0
35
/* i286 or better required */
36
#define Cpu286          (Cpu186 + 1)
37
/* i386 or better required */
38
#define Cpu386          (Cpu286 + 1)
39
/* i486 or better required */
40
#define Cpu486          (Cpu386 + 1)
41
/* i585 or better required */
42
#define Cpu586          (Cpu486 + 1)
43
/* i686 or better required */
44
#define Cpu686          (Cpu586 + 1)
45
/* Pentium4 or better required */
46
#define CpuP4           (Cpu686 + 1)
47
/* AMD K6 or better required*/
48
#define CpuK6           (CpuP4 + 1)
49
/* AMD K8 or better required */
50
#define CpuK8           (CpuK6 + 1)
51
/* MMX support required */
52
#define CpuMMX          (CpuK8 + 1)
53
/* SSE support required */
54
#define CpuSSE          (CpuMMX + 1)
55
/* SSE2 support required */
56
#define CpuSSE2         (CpuSSE + 1)
57
/* 3dnow! support required */
58
#define Cpu3dnow        (CpuSSE2 + 1)
59
/* 3dnow! Extensions support required */
60
#define Cpu3dnowA       (Cpu3dnow + 1)
61
/* SSE3 support required */
62
#define CpuSSE3         (Cpu3dnowA + 1)
63
/* VIA PadLock required */
64
#define CpuPadLock      (CpuSSE3 + 1)
65
/* AMD Secure Virtual Machine Ext-s required */
66
#define CpuSVME         (CpuPadLock + 1)
67
/* VMX Instructions required */
68
#define CpuVMX          (CpuSVME + 1)
69
/* SMX Instructions required */
70
#define CpuSMX          (CpuVMX + 1)
71
/* SSSE3 support required */
72
#define CpuSSSE3        (CpuSMX + 1)
73
/* SSE4a support required */
74
#define CpuSSE4a        (CpuSSSE3 + 1)
75
/* ABM New Instructions required */
76
#define CpuABM          (CpuSSE4a + 1)
77
/* SSE4.1 support required */
78
#define CpuSSE4_1       (CpuABM + 1)
79
/* SSE4.2 support required */
80
#define CpuSSE4_2       (CpuSSE4_1 + 1)
81
/* SSE5 support required */
82
#define CpuSSE5         (CpuSSE4_2 + 1)
83
/* Xsave/xrstor New Instuctions support required */
84
#define CpuXsave        (CpuSSE5 + 1)
85
/* 64bit support available, used by -march= in assembler.  */
86
#define CpuLM           (CpuXsave + 1)
87
/* 64bit support required  */
88
#define Cpu64           (CpuLM + 1)
89
/* Not supported in the 64bit mode  */
90
#define CpuNo64         (Cpu64 + 1)
91
/* The last bitfield in i386_cpu_flags.  */
92
#define CpuMax          CpuNo64
93
 
94
#define CpuNumOfUints \
95
  (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
96
#define CpuNumOfBits \
97
  (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
98
 
99
/* If you get a compiler error for zero width of the unused field,
100
   comment it out.  */
101
#define CpuUnused       (CpuMax + 1)
102
 
103
/* We can check if an instruction is available with array instead
104
   of bitfield. */
105
typedef union i386_cpu_flags
106
{
107
  struct
108
    {
109
      unsigned int cpui186:1;
110
      unsigned int cpui286:1;
111
      unsigned int cpui386:1;
112
      unsigned int cpui486:1;
113
      unsigned int cpui586:1;
114
      unsigned int cpui686:1;
115
      unsigned int cpup4:1;
116
      unsigned int cpuk6:1;
117
      unsigned int cpuk8:1;
118
      unsigned int cpummx:1;
119
      unsigned int cpusse:1;
120
      unsigned int cpusse2:1;
121
      unsigned int cpua3dnow:1;
122
      unsigned int cpua3dnowa:1;
123
      unsigned int cpusse3:1;
124
      unsigned int cpupadlock:1;
125
      unsigned int cpusvme:1;
126
      unsigned int cpuvmx:1;
127
      unsigned int cpusmx:1;
128
      unsigned int cpussse3:1;
129
      unsigned int cpusse4a:1;
130
      unsigned int cpuabm:1;
131
      unsigned int cpusse4_1:1;
132
      unsigned int cpusse4_2:1;
133
      unsigned int cpusse5:1;
134
      unsigned int cpuxsave:1;
135
      unsigned int cpulm:1;
136
      unsigned int cpu64:1;
137
      unsigned int cpuno64:1;
138
#ifdef CpuUnused
139
      unsigned int unused:(CpuNumOfBits - CpuUnused);
140
#endif
141
    } bitfield;
142
  unsigned int array[CpuNumOfUints];
143
} i386_cpu_flags;
144
 
145
/* Position of opcode_modifier bits.  */
146
 
147
/* has direction bit. */
148
#define D                       0
149
/* set if operands can be words or dwords encoded the canonical way */
150
#define W                       (D + 1)
151
/* insn has a modrm byte. */
152
#define Modrm                   (W + 1)
153
/* register is in low 3 bits of opcode */
154
#define ShortForm               (Modrm + 1)
155
/* special case for jump insns.  */
156
#define Jump                    (ShortForm + 1)
157
/* call and jump */
158
#define JumpDword               (Jump + 1)
159
/* loop and jecxz */
160
#define JumpByte                (JumpDword + 1)
161
/* special case for intersegment leaps/calls */
162
#define JumpInterSegment        (JumpByte + 1)
163
/* FP insn memory format bit, sized by 0x4 */
164
#define FloatMF                 (JumpInterSegment + 1)
165
/* src/dest swap for floats. */
166
#define FloatR                  (FloatMF + 1)
167
/* has float insn direction bit. */
168
#define FloatD                  (FloatR + 1)
169
/* needs size prefix if in 32-bit mode */
170
#define Size16                  (FloatD + 1)
171
/* needs size prefix if in 16-bit mode */
172
#define Size32                  (Size16 + 1)
173
/* needs size prefix if in 64-bit mode */
174
#define Size64                  (Size32 + 1)
175
/* instruction ignores operand size prefix and in Intel mode ignores
176
   mnemonic size suffix check.  */
177
#define IgnoreSize              (Size64 + 1)
178
/* default insn size depends on mode */
179
#define DefaultSize             (IgnoreSize + 1)
180
/* b suffix on instruction illegal */
181
#define No_bSuf                 (DefaultSize + 1)
182
/* w suffix on instruction illegal */
183
#define No_wSuf                 (No_bSuf + 1)
184
/* l suffix on instruction illegal */
185
#define No_lSuf                 (No_wSuf + 1)
186
/* s suffix on instruction illegal */
187
#define No_sSuf                 (No_lSuf + 1)
188
/* q suffix on instruction illegal */
189
#define No_qSuf                 (No_sSuf + 1)
190
/* long double suffix on instruction illegal */
191
#define No_ldSuf                (No_qSuf + 1)
192
/* instruction needs FWAIT */
193
#define FWait                   (No_ldSuf + 1)
194
/* quick test for string instructions */
195
#define IsString                (FWait + 1)
196
/* fake an extra reg operand for clr, imul and special register
197
   processing for some instructions.  */
198
#define RegKludge               (IsString + 1)
199
/* The first operand must be xmm0 */
200
#define FirstXmm0               (RegKludge + 1)
201
/* BYTE is OK in Intel syntax. */
202
#define ByteOkIntel             (FirstXmm0 + 1)
203
/* Convert to DWORD */
204
#define ToDword                 (ByteOkIntel + 1)
205
/* Convert to QWORD */
206
#define ToQword                 (ToDword + 1)
207
/* Address prefix changes operand 0 */
208
#define AddrPrefixOp0           (ToQword + 1)
209
/* opcode is a prefix */
210
#define IsPrefix                (AddrPrefixOp0 + 1)
211
/* instruction has extension in 8 bit imm */
212
#define ImmExt                  (IsPrefix + 1)
213
/* instruction don't need Rex64 prefix.  */
214
#define NoRex64                 (ImmExt + 1)
215
/* instruction require Rex64 prefix.  */
216
#define Rex64                   (NoRex64 + 1)
217
/* deprecated fp insn, gets a warning */
218
#define Ugh                     (Rex64 + 1)
219
#define Drex                    (Ugh + 1)
220
/* instruction needs DREX with multiple encodings for memory ops */
221
#define Drexv                   (Drex + 1)
222
/* special DREX for comparisons */
223
#define Drexc                   (Drexv + 1)
224
/* Compatible with old (<= 2.8.1) versions of gcc  */
225
#define OldGcc                  (Drexc + 1)
226
/* AT&T mnemonic.  */
227
#define ATTMnemonic             (OldGcc + 1)
228
/* AT&T syntax.  */
229
#define ATTSyntax               (ATTMnemonic + 1)
230
/* Intel syntax.  */
231
#define IntelSyntax             (ATTSyntax + 1)
232
/* The last bitfield in i386_opcode_modifier.  */
233
#define Opcode_Modifier_Max     IntelSyntax
234
 
235
typedef struct i386_opcode_modifier
236
{
237
  unsigned int d:1;
238
  unsigned int w:1;
239
  unsigned int modrm:1;
240
  unsigned int shortform:1;
241
  unsigned int jump:1;
242
  unsigned int jumpdword:1;
243
  unsigned int jumpbyte:1;
244
  unsigned int jumpintersegment:1;
245
  unsigned int floatmf:1;
246
  unsigned int floatr:1;
247
  unsigned int floatd:1;
248
  unsigned int size16:1;
249
  unsigned int size32:1;
250
  unsigned int size64:1;
251
  unsigned int ignoresize:1;
252
  unsigned int defaultsize:1;
253
  unsigned int no_bsuf:1;
254
  unsigned int no_wsuf:1;
255
  unsigned int no_lsuf:1;
256
  unsigned int no_ssuf:1;
257
  unsigned int no_qsuf:1;
258
  unsigned int no_ldsuf:1;
259
  unsigned int fwait:1;
260
  unsigned int isstring:1;
261
  unsigned int regkludge:1;
262
  unsigned int firstxmm0:1;
263
  unsigned int byteokintel:1;
264
  unsigned int todword:1;
265
  unsigned int toqword:1;
266
  unsigned int addrprefixop0:1;
267
  unsigned int isprefix:1;
268
  unsigned int immext:1;
269
  unsigned int norex64:1;
270
  unsigned int rex64:1;
271
  unsigned int ugh:1;
272
  unsigned int drex:1;
273
  unsigned int drexv:1;
274
  unsigned int drexc:1;
275
  unsigned int oldgcc:1;
276
  unsigned int attmnemonic:1;
277
  unsigned int attsyntax:1;
278
  unsigned int intelsyntax:1;
279
} i386_opcode_modifier;
280
 
281
/* Position of operand_type bits.  */
282
 
283
/* 8bit register */
284
#define Reg8                    0
285
/* 16bit register */
286
#define Reg16                   (Reg8 + 1)
287
/* 32bit register */
288
#define Reg32                   (Reg16 + 1)
289
/* 64bit register */
290
#define Reg64                   (Reg32 + 1)
291
/* Floating pointer stack register */
292
#define FloatReg                (Reg64 + 1)
293
/* MMX register */
294
#define RegMMX                  (FloatReg + 1)
295
/* SSE register */
296
#define RegXMM                  (RegMMX + 1)
297
/* Control register */
298
#define Control                 (RegXMM + 1)
299
/* Debug register */
300
#define Debug                   (Control + 1)
301
/* Test register */
302
#define Test                    (Debug + 1)
303
/* 2 bit segment register */
304
#define SReg2                   (Test + 1)
305
/* 3 bit segment register */
306
#define SReg3                   (SReg2 + 1)
307
/* 1 bit immediate */
308
#define Imm1                    (SReg3 + 1)
309
/* 8 bit immediate */
310
#define Imm8                    (Imm1 + 1)
311
/* 8 bit immediate sign extended */
312
#define Imm8S                   (Imm8 + 1)
313
/* 16 bit immediate */
314
#define Imm16                   (Imm8S + 1)
315
/* 32 bit immediate */
316
#define Imm32                   (Imm16 + 1)
317
/* 32 bit immediate sign extended */
318
#define Imm32S                  (Imm32 + 1)
319
/* 64 bit immediate */
320
#define Imm64                   (Imm32S + 1)
321
/* 8bit/16bit/32bit displacements are used in different ways,
322
   depending on the instruction.  For jumps, they specify the
323
   size of the PC relative displacement, for instructions with
324
   memory operand, they specify the size of the offset relative
325
   to the base register, and for instructions with memory offset
326
   such as `mov 1234,%al' they specify the size of the offset
327
   relative to the segment base.  */
328
/* 8 bit displacement */
329
#define Disp8                   (Imm64 + 1)
330
/* 16 bit displacement */
331
#define Disp16                  (Disp8 + 1)
332
/* 32 bit displacement */
333
#define Disp32                  (Disp16 + 1)
334
/* 32 bit signed displacement */
335
#define Disp32S                 (Disp32 + 1)
336
/* 64 bit displacement */
337
#define Disp64                  (Disp32S + 1)
338
/* Accumulator %al/%ax/%eax/%rax */
339
#define Acc                     (Disp64 + 1)
340
/* Floating pointer top stack register %st(0) */
341
#define FloatAcc                (Acc + 1)
342
/* Register which can be used for base or index in memory operand.  */
343
#define BaseIndex               (FloatAcc + 1)
344
/* Register to hold in/out port addr = dx */
345
#define InOutPortReg            (BaseIndex + 1)
346
/* Register to hold shift count = cl */
347
#define ShiftCount              (InOutPortReg + 1)
348
/* Absolute address for jump.  */
349
#define JumpAbsolute            (ShiftCount + 1)
350
/* String insn operand with fixed es segment */
351
#define EsSeg                   (JumpAbsolute + 1)
352
/* RegMem is for instructions with a modrm byte where the register
353
   destination operand should be encoded in the mod and regmem fields.
354
   Normally, it will be encoded in the reg field. We add a RegMem
355
   flag to the destination register operand to indicate that it should
356
   be encoded in the regmem field.  */
357
#define RegMem                  (EsSeg + 1)
358
/* Memory.  */
359
#define Mem                     (RegMem + 1)
360
/* BYTE memory. */
361
#define Byte                    (Mem + 1)
362
/* WORD memory. 2 byte */
363
#define Word                    (Byte + 1)
364
/* DWORD memory. 4 byte */
365
#define Dword                   (Word + 1)
366
/* FWORD memory. 6 byte */
367
#define Fword                   (Dword + 1)
368
/* QWORD memory. 8 byte */
369
#define Qword                   (Fword + 1)
370
/* TBYTE memory. 10 byte */
371
#define Tbyte                   (Qword + 1)
372
/* XMMWORD memory. */
373
#define Xmmword                 (Tbyte + 1)
374
/* Unspecified memory size.  */
375
#define Unspecified             (Xmmword + 1)
376
/* Any memory size.  */
377
#define Anysize                 (Unspecified  + 1)
378
 
379
/* The last bitfield in i386_operand_type.  */
380
#define OTMax                   Anysize
381
 
382
#define OTNumOfUints \
383
  (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
384
#define OTNumOfBits \
385
  (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
386
 
387
/* If you get a compiler error for zero width of the unused field,
388
   comment it out.  */
389
#define OTUnused                (OTMax + 1)
390
 
391
typedef union i386_operand_type
392
{
393
  struct
394
    {
395
      unsigned int reg8:1;
396
      unsigned int reg16:1;
397
      unsigned int reg32:1;
398
      unsigned int reg64:1;
399
      unsigned int floatreg:1;
400
      unsigned int regmmx:1;
401
      unsigned int regxmm:1;
402
      unsigned int control:1;
403
      unsigned int debug:1;
404
      unsigned int test:1;
405
      unsigned int sreg2:1;
406
      unsigned int sreg3:1;
407
      unsigned int imm1:1;
408
      unsigned int imm8:1;
409
      unsigned int imm8s:1;
410
      unsigned int imm16:1;
411
      unsigned int imm32:1;
412
      unsigned int imm32s:1;
413
      unsigned int imm64:1;
414
      unsigned int disp8:1;
415
      unsigned int disp16:1;
416
      unsigned int disp32:1;
417
      unsigned int disp32s:1;
418
      unsigned int disp64:1;
419
      unsigned int acc:1;
420
      unsigned int floatacc:1;
421
      unsigned int baseindex:1;
422
      unsigned int inoutportreg:1;
423
      unsigned int shiftcount:1;
424
      unsigned int jumpabsolute:1;
425
      unsigned int esseg:1;
426
      unsigned int regmem:1;
427
      unsigned int mem:1;
428
      unsigned int byte:1;
429
      unsigned int word:1;
430
      unsigned int dword:1;
431
      unsigned int fword:1;
432
      unsigned int qword:1;
433
      unsigned int tbyte:1;
434
      unsigned int xmmword:1;
435
      unsigned int unspecified:1;
436
      unsigned int anysize:1;
437
#ifdef OTUnused
438
      unsigned int unused:(OTNumOfBits - OTUnused);
439
#endif
440
    } bitfield;
441
  unsigned int array[OTNumOfUints];
442
} i386_operand_type;
443
 
444
typedef struct template
445
{
446
  /* instruction name sans width suffix ("mov" for movl insns) */
447
  char *name;
448
 
449
  /* how many operands */
450
  unsigned int operands;
451
 
452
  /* base_opcode is the fundamental opcode byte without optional
453
     prefix(es).  */
454
  unsigned int base_opcode;
455
#define Opcode_D        0x2 /* Direction bit:
456
                               set if Reg --> Regmem;
457
                               unset if Regmem --> Reg. */
458
#define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
459
#define Opcode_FloatD 0x400 /* Direction bit for float insns. */
460
 
461
  /* extension_opcode is the 3 bit extension for group <n> insns.
462
     This field is also used to store the 8-bit opcode suffix for the
463
     AMD 3DNow! instructions.
464
     If this template has no extension opcode (the usual case) use None
465
     Instructions with Drex use this to specify 2 bits for OC */
466
  unsigned int extension_opcode;
467
#define None 0xffff             /* If no extension_opcode is possible.  */
468
 
469
  /* Opcode length.  */
470
  unsigned char opcode_length;
471
 
472
  /* cpu feature flags */
473
  i386_cpu_flags cpu_flags;
474
 
475
  /* the bits in opcode_modifier are used to generate the final opcode from
476
     the base_opcode.  These bits also are used to detect alternate forms of
477
     the same instruction */
478
  i386_opcode_modifier opcode_modifier;
479
 
480
  /* operand_types[i] describes the type of operand i.  This is made
481
     by OR'ing together all of the possible type masks.  (e.g.
482
     'operand_types[i] = Reg|Imm' specifies that operand i can be
483
     either a register or an immediate operand.  */
484
  i386_operand_type operand_types[MAX_OPERANDS];
485
}
486
template;
487
 
488
extern const template i386_optab[];
489
 
490
/* these are for register name --> number & type hash lookup */
491
typedef struct
492
{
493
  char *reg_name;
494
  i386_operand_type reg_type;
495
  unsigned char reg_flags;
496
#define RegRex      0x1  /* Extended register.  */
497
#define RegRex64    0x2  /* Extended 8 bit register.  */
498
  unsigned char reg_num;
499
#define RegRip  ((unsigned char ) ~0)
500
#define RegEip  (RegRip - 1)
501
/* EIZ and RIZ are fake index registers.  */
502
#define RegEiz  (RegEip - 1)
503
#define RegRiz  (RegEiz - 1)
504
/* FLAT is a fake segment register (Intel mode).  */
505
#define RegFlat     ((unsigned char) ~0)
506
  signed char dw2_regnum[2];
507
#define Dw2Inval (-1)
508
}
509
reg_entry;
510
 
511
/* Entries in i386_regtab.  */
512
#define REGNAM_AL 1
513
#define REGNAM_AX 25
514
#define REGNAM_EAX 41
515
 
516
extern const reg_entry i386_regtab[];
517
extern const unsigned int i386_regtab_size;
518
 
519
typedef struct
520
{
521
  char *seg_name;
522
  unsigned int seg_prefix;
523
}
524
seg_entry;
525
 
526
extern const seg_entry cs;
527
extern const seg_entry ds;
528
extern const seg_entry ss;
529
extern const seg_entry es;
530
extern const seg_entry fs;
531
extern const seg_entry gs;

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