OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [opcodes/] [m32r-desc.c] - Blame information for rev 165

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn 
/* CPU data for m32r.
2 
 
3 
THIS FILE IS MACHINE GENERATED WITH CGEN.
4 
 
5 
Copyright 1996-2007 Free Software Foundation, Inc.
6 
 
7 
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8 
 
9 
   This file is free software; you can redistribute it and/or modify
10 
   it under the terms of the GNU General Public License as published by
11 
   the Free Software Foundation; either version 3, or (at your option)
12 
   any later version.
13 
 
14 
   It is distributed in the hope that it will be useful, but WITHOUT
15 
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
17 
   License for more details.
18 
 
19 
   You should have received a copy of the GNU General Public License along
20 
   with this program; if not, write to the Free Software Foundation, Inc.,
21 
   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
22 
 
23 
*/
24 
 
25 
#include "sysdep.h"
26 
#include <stdio.h>
27 
#include <stdarg.h>
28 
#include "ansidecl.h"
29 
#include "bfd.h"
30 
#include "symcat.h"
31 
#include "m32r-desc.h"
32 
#include "m32r-opc.h"
33 
#include "opintl.h"
34 
#include "libiberty.h"
35 
#include "xregex.h"
36 
 
37 
/* Attributes.  */
38 
 
39 
static const CGEN_ATTR_ENTRY bool_attr[] =
40 
{
41 
  { "#f", 0 },
42 
  { "#t", 1 },
43 
  { 0, 0 }
44 
};
45 
 
46 
static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
47 
{
48 
  { "base", MACH_BASE },
49 
  { "m32r", MACH_M32R },
50 
  { "m32rx", MACH_M32RX },
51 
  { "m32r2", MACH_M32R2 },
52 
  { "max", MACH_MAX },
53 
  { 0, 0 }
54 
};
55 
 
56 
static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
57 
{
58 
  { "m32r", ISA_M32R },
59 
  { "max", ISA_MAX },
60 
  { 0, 0 }
61 
};
62 
 
63 
static const CGEN_ATTR_ENTRY PIPE_attr[] ATTRIBUTE_UNUSED =
64 
{
65 
  { "NONE", PIPE_NONE },
66 
  { "O", PIPE_O },
67 
  { "S", PIPE_S },
68 
  { "OS", PIPE_OS },
69 
  { "O_OS", PIPE_O_OS },
70 
  { 0, 0 }
71 
};
72 
 
73 
const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[] =
74 
{
75 
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
76 
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
77 
  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
78 
  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
79 
  { "RESERVED", &bool_attr[0], &bool_attr[0] },
80 
  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
81 
  { "SIGNED", &bool_attr[0], &bool_attr[0] },
82 
  { "RELOC", &bool_attr[0], &bool_attr[0] },
83 
  { 0, 0, 0 }
84 
};
85 
 
86 
const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[] =
87 
{
88 
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
89 
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
90 
  { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
91 
  { "PC", &bool_attr[0], &bool_attr[0] },
92 
  { "PROFILE", &bool_attr[0], &bool_attr[0] },
93 
  { 0, 0, 0 }
94 
};
95 
 
96 
const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
97 
{
98 
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
99 
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
100 
  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
101 
  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
102 
  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
103 
  { "SIGNED", &bool_attr[0], &bool_attr[0] },
104 
  { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
105 
  { "RELAX", &bool_attr[0], &bool_attr[0] },
106 
  { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
107 
  { "RELOC", &bool_attr[0], &bool_attr[0] },
108 
  { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
109 
  { 0, 0, 0 }
110 
};
111 
 
112 
const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
113 
{
114 
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
115 
  { "PIPE", & PIPE_attr[0], & PIPE_attr[0] },
116 
  { "ALIAS", &bool_attr[0], &bool_attr[0] },
117 
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
118 
  { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
119 
  { "COND-CTI", &bool_attr[0], &bool_attr[0] },
120 
  { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
121 
  { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
122 
  { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
123 
  { "RELAXED", &bool_attr[0], &bool_attr[0] },
124 
  { "NO-DIS", &bool_attr[0], &bool_attr[0] },
125 
  { "PBB", &bool_attr[0], &bool_attr[0] },
126 
  { "FILL-SLOT", &bool_attr[0], &bool_attr[0] },
127 
  { "SPECIAL", &bool_attr[0], &bool_attr[0] },
128 
  { "SPECIAL_M32R", &bool_attr[0], &bool_attr[0] },
129 
  { "SPECIAL_FLOAT", &bool_attr[0], &bool_attr[0] },
130 
  { 0, 0, 0 }
131 
};
132 
 
133 
/* Instruction set variants.  */
134 
 
135 
static const CGEN_ISA m32r_cgen_isa_table[] = {
136 
  { "m32r", 32, 32, 16, 32 },
137 
  { 0, 0, 0, 0, 0 }
138 
};
139 
 
140 
/* Machine variants.  */
141 
 
142 
static const CGEN_MACH m32r_cgen_mach_table[] = {
143 
  { "m32r", "m32r", MACH_M32R, 0 },
144 
  { "m32rx", "m32rx", MACH_M32RX, 0 },
145 
  { "m32r2", "m32r2", MACH_M32R2, 0 },
146 
  { 0, 0, 0, 0 }
147 
};
148 
 
149 
static CGEN_KEYWORD_ENTRY m32r_cgen_opval_gr_names_entries[] =
150 
{
151 
  { "fp", 13, {0, {{{0, 0}}}}, 0, 0 },
152 
  { "lr", 14, {0, {{{0, 0}}}}, 0, 0 },
153 
  { "sp", 15, {0, {{{0, 0}}}}, 0, 0 },
154 
  { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
155 
  { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
156 
  { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
157 
  { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
158 
  { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
159 
  { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
160 
  { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
161 
  { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
162 
  { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
163 
  { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
164 
  { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
165 
  { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
166 
  { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
167 
  { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
168 
  { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
169 
  { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }
170 
};
171 
 
172 
CGEN_KEYWORD m32r_cgen_opval_gr_names =
173 
{
174 
  & m32r_cgen_opval_gr_names_entries[0],
175 
  19,
176 
  0, 0, 0, 0, ""
177 
};
178 
 
179 
static CGEN_KEYWORD_ENTRY m32r_cgen_opval_cr_names_entries[] =
180 
{
181 
  { "psw", 0, {0, {{{0, 0}}}}, 0, 0 },
182 
  { "cbr", 1, {0, {{{0, 0}}}}, 0, 0 },
183 
  { "spi", 2, {0, {{{0, 0}}}}, 0, 0 },
184 
  { "spu", 3, {0, {{{0, 0}}}}, 0, 0 },
185 
  { "bpc", 6, {0, {{{0, 0}}}}, 0, 0 },
186 
  { "bbpsw", 8, {0, {{{0, 0}}}}, 0, 0 },
187 
  { "bbpc", 14, {0, {{{0, 0}}}}, 0, 0 },
188 
  { "evb", 5, {0, {{{0, 0}}}}, 0, 0 },
189 
  { "cr0", 0, {0, {{{0, 0}}}}, 0, 0 },
190 
  { "cr1", 1, {0, {{{0, 0}}}}, 0, 0 },
191 
  { "cr2", 2, {0, {{{0, 0}}}}, 0, 0 },
192 
  { "cr3", 3, {0, {{{0, 0}}}}, 0, 0 },
193 
  { "cr4", 4, {0, {{{0, 0}}}}, 0, 0 },
194 
  { "cr5", 5, {0, {{{0, 0}}}}, 0, 0 },
195 
  { "cr6", 6, {0, {{{0, 0}}}}, 0, 0 },
196 
  { "cr7", 7, {0, {{{0, 0}}}}, 0, 0 },
197 
  { "cr8", 8, {0, {{{0, 0}}}}, 0, 0 },
198 
  { "cr9", 9, {0, {{{0, 0}}}}, 0, 0 },
199 
  { "cr10", 10, {0, {{{0, 0}}}}, 0, 0 },
200 
  { "cr11", 11, {0, {{{0, 0}}}}, 0, 0 },
201 
  { "cr12", 12, {0, {{{0, 0}}}}, 0, 0 },
202 
  { "cr13", 13, {0, {{{0, 0}}}}, 0, 0 },
203 
  { "cr14", 14, {0, {{{0, 0}}}}, 0, 0 },
204 
  { "cr15", 15, {0, {{{0, 0}}}}, 0, 0 }
205 
};
206 
 
207 
CGEN_KEYWORD m32r_cgen_opval_cr_names =
208 
{
209 
  & m32r_cgen_opval_cr_names_entries[0],
210 
  24,
211 
  0, 0, 0, 0, ""
212 
};
213 
 
214 
static CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
215 
{
216 
  { "a0", 0, {0, {{{0, 0}}}}, 0, 0 },
217 
  { "a1", 1, {0, {{{0, 0}}}}, 0, 0 }
218 
};
219 
 
220 
CGEN_KEYWORD m32r_cgen_opval_h_accums =
221 
{
222 
  & m32r_cgen_opval_h_accums_entries[0],
223 
  2,
224 
  0, 0, 0, 0, ""
225 
};
226 
 
227 
 
228 
/* The hardware table.  */
229 
 
230 
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
231 
#define A(a) (1 << CGEN_HW_##a)
232 
#else
233 
#define A(a) (1 << CGEN_HW_/**/a)
234 
#endif
235 
 
236 
const CGEN_HW_ENTRY m32r_cgen_hw_table[] =
237 
{
238 
  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
239 
  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
240 
  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
241 
  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
242 
  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
243 
  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
244 
  { "h-hi16", HW_H_HI16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
245 
  { "h-slo16", HW_H_SLO16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
246 
  { "h-ulo16", HW_H_ULO16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
247 
  { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
248 
  { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_cr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
249 
  { "h-accum", HW_H_ACCUM, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
250 
  { "h-accums", HW_H_ACCUMS, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } },
251 
  { "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
252 
  { "h-psw", HW_H_PSW, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
253 
  { "h-bpsw", HW_H_BPSW, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
254 
  { "h-bbpsw", HW_H_BBPSW, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
255 
  { "h-lock", HW_H_LOCK, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
256 
  { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
257 
};
258 
 
259 
#undef A
260 
 
261 
 
262 
/* The instruction field table.  */
263 
 
264 
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
265 
#define A(a) (1 << CGEN_IFLD_##a)
266 
#else
267 
#define A(a) (1 << CGEN_IFLD_/**/a)
268 
#endif
269 
 
270 
const CGEN_IFLD m32r_cgen_ifld_table[] =
271 
{
272 
  { M32R_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
273 
  { M32R_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
274 
  { M32R_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
275 
  { M32R_F_OP2, "f-op2", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
276 
  { M32R_F_COND, "f-cond", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
277 
  { M32R_F_R1, "f-r1", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
278 
  { M32R_F_R2, "f-r2", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
279 
  { M32R_F_SIMM8, "f-simm8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
280 
  { M32R_F_SIMM16, "f-simm16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
281 
  { M32R_F_SHIFT_OP2, "f-shift-op2", 0, 32, 8, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
282 
  { M32R_F_UIMM3, "f-uimm3", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
283 
  { M32R_F_UIMM4, "f-uimm4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
284 
  { M32R_F_UIMM5, "f-uimm5", 0, 32, 11, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
285 
  { M32R_F_UIMM8, "f-uimm8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
286 
  { M32R_F_UIMM16, "f-uimm16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
287 
  { M32R_F_UIMM24, "f-uimm24", 0, 32, 8, 24, { 0|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
288 
  { M32R_F_HI16, "f-hi16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
289 
  { M32R_F_DISP8, "f-disp8", 0, 32, 8, 8, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
290 
  { M32R_F_DISP16, "f-disp16", 0, 32, 16, 16, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
291 
  { M32R_F_DISP24, "f-disp24", 0, 32, 8, 24, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
292 
  { M32R_F_OP23, "f-op23", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
293 
  { M32R_F_OP3, "f-op3", 0, 32, 14, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
294 
  { M32R_F_ACC, "f-acc", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
295 
  { M32R_F_ACCS, "f-accs", 0, 32, 12, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
296 
  { M32R_F_ACCD, "f-accd", 0, 32, 4, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
297 
  { M32R_F_BITS67, "f-bits67", 0, 32, 6, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
298 
  { M32R_F_BIT4, "f-bit4", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
299 
  { M32R_F_BIT14, "f-bit14", 0, 32, 14, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
300 
  { M32R_F_IMM1, "f-imm1", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
301 
  { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
302 
};
303 
 
304 
#undef A
305 
 
306 
 
307 
 
308 
/* multi ifield declarations */
309 
 
310 
 
311 
 
312 
/* multi ifield definitions */
313 
 
314 
 
315 
/* The operand table.  */
316 
 
317 
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
318 
#define A(a) (1 << CGEN_OPERAND_##a)
319 
#else
320 
#define A(a) (1 << CGEN_OPERAND_/**/a)
321 
#endif
322 
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
323 
#define OPERAND(op) M32R_OPERAND_##op
324 
#else
325 
#define OPERAND(op) M32R_OPERAND_/**/op
326 
#endif
327 
 
328 
const CGEN_OPERAND m32r_cgen_operand_table[] =
329 
{
330 
/* pc: program counter */
331 
  { "pc", M32R_OPERAND_PC, HW_H_PC, 0, 0,
332 
    { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_NIL] } },
333 
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
334 
/* sr: source register */
335 
  { "sr", M32R_OPERAND_SR, HW_H_GR, 12, 4,
336 
    { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
337 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
338 
/* dr: destination register */
339 
  { "dr", M32R_OPERAND_DR, HW_H_GR, 4, 4,
340 
    { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
341 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
342 
/* src1: source register 1 */
343 
  { "src1", M32R_OPERAND_SRC1, HW_H_GR, 4, 4,
344 
    { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
345 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
346 
/* src2: source register 2 */
347 
  { "src2", M32R_OPERAND_SRC2, HW_H_GR, 12, 4,
348 
    { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
349 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
350 
/* scr: source control register */
351 
  { "scr", M32R_OPERAND_SCR, HW_H_CR, 12, 4,
352 
    { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
353 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
354 
/* dcr: destination control register */
355 
  { "dcr", M32R_OPERAND_DCR, HW_H_CR, 4, 4,
356 
    { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
357 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
358 
/* simm8: 8 bit signed immediate */
359 
  { "simm8", M32R_OPERAND_SIMM8, HW_H_SINT, 8, 8,
360 
    { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM8] } },
361 
    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
362 
/* simm16: 16 bit signed immediate */
363 
  { "simm16", M32R_OPERAND_SIMM16, HW_H_SINT, 16, 16,
364 
    { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } },
365 
    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
366 
/* uimm3: 3 bit unsigned number */
367 
  { "uimm3", M32R_OPERAND_UIMM3, HW_H_UINT, 5, 3,
368 
    { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM3] } },
369 
    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
370 
/* uimm4: 4 bit trap number */
371 
  { "uimm4", M32R_OPERAND_UIMM4, HW_H_UINT, 12, 4,
372 
    { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM4] } },
373 
    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
374 
/* uimm5: 5 bit shift count */
375 
  { "uimm5", M32R_OPERAND_UIMM5, HW_H_UINT, 11, 5,
376 
    { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM5] } },
377 
    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
378 
/* uimm8: 8 bit unsigned immediate */
379 
  { "uimm8", M32R_OPERAND_UIMM8, HW_H_UINT, 8, 8,
380 
    { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM8] } },
381 
    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
382 
/* uimm16: 16 bit unsigned immediate */
383 
  { "uimm16", M32R_OPERAND_UIMM16, HW_H_UINT, 16, 16,
384 
    { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } },
385 
    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
386 
/* imm1: 1 bit immediate */
387 
  { "imm1", M32R_OPERAND_IMM1, HW_H_UINT, 15, 1,
388 
    { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_IMM1] } },
389 
    { 0|A(HASH_PREFIX), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } }  },
390 
/* accd: accumulator destination register */
391 
  { "accd", M32R_OPERAND_ACCD, HW_H_ACCUMS, 4, 2,
392 
    { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCD] } },
393 
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } }  },
394 
/* accs: accumulator source register */
395 
  { "accs", M32R_OPERAND_ACCS, HW_H_ACCUMS, 12, 2,
396 
    { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCS] } },
397 
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } }  },
398 
/* acc: accumulator reg (d) */
399 
  { "acc", M32R_OPERAND_ACC, HW_H_ACCUMS, 8, 1,
400 
    { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACC] } },
401 
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } }  },
402 
/* hash: # prefix */
403 
  { "hash", M32R_OPERAND_HASH, HW_H_SINT, 0, 0,
404 
    { 0, { (const PTR) 0 } },
405 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
406 
/* hi16: high 16 bit immediate, sign optional */
407 
  { "hi16", M32R_OPERAND_HI16, HW_H_HI16, 16, 16,
408 
    { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_HI16] } },
409 
    { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
410 
/* slo16: 16 bit signed immediate, for low() */
411 
  { "slo16", M32R_OPERAND_SLO16, HW_H_SLO16, 16, 16,
412 
    { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } },
413 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
414 
/* ulo16: 16 bit unsigned immediate, for low() */
415 
  { "ulo16", M32R_OPERAND_ULO16, HW_H_ULO16, 16, 16,
416 
    { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } },
417 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
418 
/* uimm24: 24 bit address */
419 
  { "uimm24", M32R_OPERAND_UIMM24, HW_H_ADDR, 8, 24,
420 
    { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM24] } },
421 
    { 0|A(HASH_PREFIX)|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
422 
/* disp8: 8 bit displacement */
423 
  { "disp8", M32R_OPERAND_DISP8, HW_H_IADDR, 8, 8,
424 
    { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP8] } },
425 
    { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
426 
/* disp16: 16 bit displacement */
427 
  { "disp16", M32R_OPERAND_DISP16, HW_H_IADDR, 16, 16,
428 
    { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP16] } },
429 
    { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
430 
/* disp24: 24 bit displacement */
431 
  { "disp24", M32R_OPERAND_DISP24, HW_H_IADDR, 8, 24,
432 
    { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP24] } },
433 
    { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
434 
/* condbit: condition bit */
435 
  { "condbit", M32R_OPERAND_CONDBIT, HW_H_COND, 0, 0,
436 
    { 0, { (const PTR) 0 } },
437 
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
438 
/* accum: accumulator */
439 
  { "accum", M32R_OPERAND_ACCUM, HW_H_ACCUM, 0, 0,
440 
    { 0, { (const PTR) 0 } },
441 
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
442 
/* sentinel */
443 
  { 0, 0, 0, 0, 0,
444 
    { 0, { (const PTR) 0 } },
445 
    { 0, { { { (1<<MACH_BASE), 0 } } } } }
446 
};
447 
 
448 
#undef A
449 
 
450 
 
451 
/* The instruction table.  */
452 
 
453 
#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
454 
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
455 
#define A(a) (1 << CGEN_INSN_##a)
456 
#else
457 
#define A(a) (1 << CGEN_INSN_/**/a)
458 
#endif
459 
 
460 
static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
461 
{
462 
  /* Special null first entry.
463 
     A `num' value of zero is thus invalid.
464 
     Also, the special `invalid' insn resides here.  */
465 
  { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } },
466 
/* add $dr,$sr */
467 
  {
468 
    M32R_INSN_ADD, "add", "add", 16,
469 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
470 
  },
471 
/* add3 $dr,$sr,$hash$slo16 */
472 
  {
473 
    M32R_INSN_ADD3, "add3", "add3", 32,
474 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
475 
  },
476 
/* and $dr,$sr */
477 
  {
478 
    M32R_INSN_AND, "and", "and", 16,
479 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
480 
  },
481 
/* and3 $dr,$sr,$uimm16 */
482 
  {
483 
    M32R_INSN_AND3, "and3", "and3", 32,
484 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
485 
  },
486 
/* or $dr,$sr */
487 
  {
488 
    M32R_INSN_OR, "or", "or", 16,
489 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
490 
  },
491 
/* or3 $dr,$sr,$hash$ulo16 */
492 
  {
493 
    M32R_INSN_OR3, "or3", "or3", 32,
494 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
495 
  },
496 
/* xor $dr,$sr */
497 
  {
498 
    M32R_INSN_XOR, "xor", "xor", 16,
499 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
500 
  },
501 
/* xor3 $dr,$sr,$uimm16 */
502 
  {
503 
    M32R_INSN_XOR3, "xor3", "xor3", 32,
504 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
505 
  },
506 
/* addi $dr,$simm8 */
507 
  {
508 
    M32R_INSN_ADDI, "addi", "addi", 16,
509 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
510 
  },
511 
/* addv $dr,$sr */
512 
  {
513 
    M32R_INSN_ADDV, "addv", "addv", 16,
514 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
515 
  },
516 
/* addv3 $dr,$sr,$simm16 */
517 
  {
518 
    M32R_INSN_ADDV3, "addv3", "addv3", 32,
519 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
520 
  },
521 
/* addx $dr,$sr */
522 
  {
523 
    M32R_INSN_ADDX, "addx", "addx", 16,
524 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
525 
  },
526 
/* bc.s $disp8 */
527 
  {
528 
    M32R_INSN_BC8, "bc8", "bc.s", 16,
529 
    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
530 
  },
531 
/* bc.l $disp24 */
532 
  {
533 
    M32R_INSN_BC24, "bc24", "bc.l", 32,
534 
    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
535 
  },
536 
/* beq $src1,$src2,$disp16 */
537 
  {
538 
    M32R_INSN_BEQ, "beq", "beq", 32,
539 
    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
540 
  },
541 
/* beqz $src2,$disp16 */
542 
  {
543 
    M32R_INSN_BEQZ, "beqz", "beqz", 32,
544 
    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
545 
  },
546 
/* bgez $src2,$disp16 */
547 
  {
548 
    M32R_INSN_BGEZ, "bgez", "bgez", 32,
549 
    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
550 
  },
551 
/* bgtz $src2,$disp16 */
552 
  {
553 
    M32R_INSN_BGTZ, "bgtz", "bgtz", 32,
554 
    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
555 
  },
556 
/* blez $src2,$disp16 */
557 
  {
558 
    M32R_INSN_BLEZ, "blez", "blez", 32,
559 
    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
560 
  },
561 
/* bltz $src2,$disp16 */
562 
  {
563 
    M32R_INSN_BLTZ, "bltz", "bltz", 32,
564 
    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
565 
  },
566 
/* bnez $src2,$disp16 */
567 
  {
568 
    M32R_INSN_BNEZ, "bnez", "bnez", 32,
569 
    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
570 
  },
571 
/* bl.s $disp8 */
572 
  {
573 
    M32R_INSN_BL8, "bl8", "bl.s", 16,
574 
    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
575 
  },
576 
/* bl.l $disp24 */
577 
  {
578 
    M32R_INSN_BL24, "bl24", "bl.l", 32,
579 
    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
580 
  },
581 
/* bcl.s $disp8 */
582 
  {
583 
    M32R_INSN_BCL8, "bcl8", "bcl.s", 16,
584 
    { 0|A(FILL_SLOT)|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
585 
  },
586 
/* bcl.l $disp24 */
587 
  {
588 
    M32R_INSN_BCL24, "bcl24", "bcl.l", 32,
589 
    { 0|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
590 
  },
591 
/* bnc.s $disp8 */
592 
  {
593 
    M32R_INSN_BNC8, "bnc8", "bnc.s", 16,
594 
    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
595 
  },
596 
/* bnc.l $disp24 */
597 
  {
598 
    M32R_INSN_BNC24, "bnc24", "bnc.l", 32,
599 
    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
600 
  },
601 
/* bne $src1,$src2,$disp16 */
602 
  {
603 
    M32R_INSN_BNE, "bne", "bne", 32,
604 
    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
605 
  },
606 
/* bra.s $disp8 */
607 
  {
608 
    M32R_INSN_BRA8, "bra8", "bra.s", 16,
609 
    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
610 
  },
611 
/* bra.l $disp24 */
612 
  {
613 
    M32R_INSN_BRA24, "bra24", "bra.l", 32,
614 
    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
615 
  },
616 
/* bncl.s $disp8 */
617 
  {
618 
    M32R_INSN_BNCL8, "bncl8", "bncl.s", 16,
619 
    { 0|A(FILL_SLOT)|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
620 
  },
621 
/* bncl.l $disp24 */
622 
  {
623 
    M32R_INSN_BNCL24, "bncl24", "bncl.l", 32,
624 
    { 0|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
625 
  },
626 
/* cmp $src1,$src2 */
627 
  {
628 
    M32R_INSN_CMP, "cmp", "cmp", 16,
629 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
630 
  },
631 
/* cmpi $src2,$simm16 */
632 
  {
633 
    M32R_INSN_CMPI, "cmpi", "cmpi", 32,
634 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
635 
  },
636 
/* cmpu $src1,$src2 */
637 
  {
638 
    M32R_INSN_CMPU, "cmpu", "cmpu", 16,
639 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
640 
  },
641 
/* cmpui $src2,$simm16 */
642 
  {
643 
    M32R_INSN_CMPUI, "cmpui", "cmpui", 32,
644 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
645 
  },
646 
/* cmpeq $src1,$src2 */
647 
  {
648 
    M32R_INSN_CMPEQ, "cmpeq", "cmpeq", 16,
649 
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_OS, 0 } } } }
650 
  },
651 
/* cmpz $src2 */
652 
  {
653 
    M32R_INSN_CMPZ, "cmpz", "cmpz", 16,
654 
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_OS, 0 } } } }
655 
  },
656 
/* div $dr,$sr */
657 
  {
658 
    M32R_INSN_DIV, "div", "div", 32,
659 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
660 
  },
661 
/* divu $dr,$sr */
662 
  {
663 
    M32R_INSN_DIVU, "divu", "divu", 32,
664 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
665 
  },
666 
/* rem $dr,$sr */
667 
  {
668 
    M32R_INSN_REM, "rem", "rem", 32,
669 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
670 
  },
671 
/* remu $dr,$sr */
672 
  {
673 
    M32R_INSN_REMU, "remu", "remu", 32,
674 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
675 
  },
676 
/* remh $dr,$sr */
677 
  {
678 
    M32R_INSN_REMH, "remh", "remh", 32,
679 
    { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
680 
  },
681 
/* remuh $dr,$sr */
682 
  {
683 
    M32R_INSN_REMUH, "remuh", "remuh", 32,
684 
    { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
685 
  },
686 
/* remb $dr,$sr */
687 
  {
688 
    M32R_INSN_REMB, "remb", "remb", 32,
689 
    { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
690 
  },
691 
/* remub $dr,$sr */
692 
  {
693 
    M32R_INSN_REMUB, "remub", "remub", 32,
694 
    { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
695 
  },
696 
/* divuh $dr,$sr */
697 
  {
698 
    M32R_INSN_DIVUH, "divuh", "divuh", 32,
699 
    { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
700 
  },
701 
/* divb $dr,$sr */
702 
  {
703 
    M32R_INSN_DIVB, "divb", "divb", 32,
704 
    { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
705 
  },
706 
/* divub $dr,$sr */
707 
  {
708 
    M32R_INSN_DIVUB, "divub", "divub", 32,
709 
    { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
710 
  },
711 
/* divh $dr,$sr */
712 
  {
713 
    M32R_INSN_DIVH, "divh", "divh", 32,
714 
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
715 
  },
716 
/* jc $sr */
717 
  {
718 
    M32R_INSN_JC, "jc", "jc", 16,
719 
    { 0|A(SPECIAL)|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
720 
  },
721 
/* jnc $sr */
722 
  {
723 
    M32R_INSN_JNC, "jnc", "jnc", 16,
724 
    { 0|A(SPECIAL)|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
725 
  },
726 
/* jl $sr */
727 
  {
728 
    M32R_INSN_JL, "jl", "jl", 16,
729 
    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
730 
  },
731 
/* jmp $sr */
732 
  {
733 
    M32R_INSN_JMP, "jmp", "jmp", 16,
734 
    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
735 
  },
736 
/* ld $dr,@$sr */
737 
  {
738 
    M32R_INSN_LD, "ld", "ld", 16,
739 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
740 
  },
741 
/* ld $dr,@($slo16,$sr) */
742 
  {
743 
    M32R_INSN_LD_D, "ld-d", "ld", 32,
744 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
745 
  },
746 
/* ldb $dr,@$sr */
747 
  {
748 
    M32R_INSN_LDB, "ldb", "ldb", 16,
749 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
750 
  },
751 
/* ldb $dr,@($slo16,$sr) */
752 
  {
753 
    M32R_INSN_LDB_D, "ldb-d", "ldb", 32,
754 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
755 
  },
756 
/* ldh $dr,@$sr */
757 
  {
758 
    M32R_INSN_LDH, "ldh", "ldh", 16,
759 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
760 
  },
761 
/* ldh $dr,@($slo16,$sr) */
762 
  {
763 
    M32R_INSN_LDH_D, "ldh-d", "ldh", 32,
764 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
765 
  },
766 
/* ldub $dr,@$sr */
767 
  {
768 
    M32R_INSN_LDUB, "ldub", "ldub", 16,
769 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
770 
  },
771 
/* ldub $dr,@($slo16,$sr) */
772 
  {
773 
    M32R_INSN_LDUB_D, "ldub-d", "ldub", 32,
774 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
775 
  },
776 
/* lduh $dr,@$sr */
777 
  {
778 
    M32R_INSN_LDUH, "lduh", "lduh", 16,
779 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
780 
  },
781 
/* lduh $dr,@($slo16,$sr) */
782 
  {
783 
    M32R_INSN_LDUH_D, "lduh-d", "lduh", 32,
784 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
785 
  },
786 
/* ld $dr,@$sr+ */
787 
  {
788 
    M32R_INSN_LD_PLUS, "ld-plus", "ld", 16,
789 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
790 
  },
791 
/* ld24 $dr,$uimm24 */
792 
  {
793 
    M32R_INSN_LD24, "ld24", "ld24", 32,
794 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
795 
  },
796 
/* ldi8 $dr,$simm8 */
797 
  {
798 
    M32R_INSN_LDI8, "ldi8", "ldi8", 16,
799 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
800 
  },
801 
/* ldi16 $dr,$hash$slo16 */
802 
  {
803 
    M32R_INSN_LDI16, "ldi16", "ldi16", 32,
804 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
805 
  },
806 
/* lock $dr,@$sr */
807 
  {
808 
    M32R_INSN_LOCK, "lock", "lock", 16,
809 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
810 
  },
811 
/* machi $src1,$src2 */
812 
  {
813 
    M32R_INSN_MACHI, "machi", "machi", 16,
814 
    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
815 
  },
816 
/* machi $src1,$src2,$acc */
817 
  {
818 
    M32R_INSN_MACHI_A, "machi-a", "machi", 16,
819 
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
820 
  },
821 
/* maclo $src1,$src2 */
822 
  {
823 
    M32R_INSN_MACLO, "maclo", "maclo", 16,
824 
    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
825 
  },
826 
/* maclo $src1,$src2,$acc */
827 
  {
828 
    M32R_INSN_MACLO_A, "maclo-a", "maclo", 16,
829 
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
830 
  },
831 
/* macwhi $src1,$src2 */
832 
  {
833 
    M32R_INSN_MACWHI, "macwhi", "macwhi", 16,
834 
    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
835 
  },
836 
/* macwhi $src1,$src2,$acc */
837 
  {
838 
    M32R_INSN_MACWHI_A, "macwhi-a", "macwhi", 16,
839 
    { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
840 
  },
841 
/* macwlo $src1,$src2 */
842 
  {
843 
    M32R_INSN_MACWLO, "macwlo", "macwlo", 16,
844 
    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
845 
  },
846 
/* macwlo $src1,$src2,$acc */
847 
  {
848 
    M32R_INSN_MACWLO_A, "macwlo-a", "macwlo", 16,
849 
    { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
850 
  },
851 
/* mul $dr,$sr */
852 
  {
853 
    M32R_INSN_MUL, "mul", "mul", 16,
854 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_S, 0 } } } }
855 
  },
856 
/* mulhi $src1,$src2 */
857 
  {
858 
    M32R_INSN_MULHI, "mulhi", "mulhi", 16,
859 
    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
860 
  },
861 
/* mulhi $src1,$src2,$acc */
862 
  {
863 
    M32R_INSN_MULHI_A, "mulhi-a", "mulhi", 16,
864 
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
865 
  },
866 
/* mullo $src1,$src2 */
867 
  {
868 
    M32R_INSN_MULLO, "mullo", "mullo", 16,
869 
    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
870 
  },
871 
/* mullo $src1,$src2,$acc */
872 
  {
873 
    M32R_INSN_MULLO_A, "mullo-a", "mullo", 16,
874 
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
875 
  },
876 
/* mulwhi $src1,$src2 */
877 
  {
878 
    M32R_INSN_MULWHI, "mulwhi", "mulwhi", 16,
879 
    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
880 
  },
881 
/* mulwhi $src1,$src2,$acc */
882 
  {
883 
    M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi", 16,
884 
    { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
885 
  },
886 
/* mulwlo $src1,$src2 */
887 
  {
888 
    M32R_INSN_MULWLO, "mulwlo", "mulwlo", 16,
889 
    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
890 
  },
891 
/* mulwlo $src1,$src2,$acc */
892 
  {
893 
    M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo", 16,
894 
    { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
895 
  },
896 
/* mv $dr,$sr */
897 
  {
898 
    M32R_INSN_MV, "mv", "mv", 16,
899 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
900 
  },
901 
/* mvfachi $dr */
902 
  {
903 
    M32R_INSN_MVFACHI, "mvfachi", "mvfachi", 16,
904 
    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
905 
  },
906 
/* mvfachi $dr,$accs */
907 
  {
908 
    M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi", 16,
909 
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
910 
  },
911 
/* mvfaclo $dr */
912 
  {
913 
    M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo", 16,
914 
    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
915 
  },
916 
/* mvfaclo $dr,$accs */
917 
  {
918 
    M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo", 16,
919 
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
920 
  },
921 
/* mvfacmi $dr */
922 
  {
923 
    M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi", 16,
924 
    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
925 
  },
926 
/* mvfacmi $dr,$accs */
927 
  {
928 
    M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi", 16,
929 
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
930 
  },
931 
/* mvfc $dr,$scr */
932 
  {
933 
    M32R_INSN_MVFC, "mvfc", "mvfc", 16,
934 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
935 
  },
936 
/* mvtachi $src1 */
937 
  {
938 
    M32R_INSN_MVTACHI, "mvtachi", "mvtachi", 16,
939 
    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
940 
  },
941 
/* mvtachi $src1,$accs */
942 
  {
943 
    M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi", 16,
944 
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
945 
  },
946 
/* mvtaclo $src1 */
947 
  {
948 
    M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo", 16,
949 
    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
950 
  },
951 
/* mvtaclo $src1,$accs */
952 
  {
953 
    M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo", 16,
954 
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
955 
  },
956 
/* mvtc $sr,$dcr */
957 
  {
958 
    M32R_INSN_MVTC, "mvtc", "mvtc", 16,
959 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
960 
  },
961 
/* neg $dr,$sr */
962 
  {
963 
    M32R_INSN_NEG, "neg", "neg", 16,
964 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
965 
  },
966 
/* nop */
967 
  {
968 
    M32R_INSN_NOP, "nop", "nop", 16,
969 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
970 
  },
971 
/* not $dr,$sr */
972 
  {
973 
    M32R_INSN_NOT, "not", "not", 16,
974 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
975 
  },
976 
/* rac */
977 
  {
978 
    M32R_INSN_RAC, "rac", "rac", 16,
979 
    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
980 
  },
981 
/* rac $accd,$accs,$imm1 */
982 
  {
983 
    M32R_INSN_RAC_DSI, "rac-dsi", "rac", 16,
984 
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
985 
  },
986 
/* rach */
987 
  {
988 
    M32R_INSN_RACH, "rach", "rach", 16,
989 
    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
990 
  },
991 
/* rach $accd,$accs,$imm1 */
992 
  {
993 
    M32R_INSN_RACH_DSI, "rach-dsi", "rach", 16,
994 
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
995 
  },
996 
/* rte */
997 
  {
998 
    M32R_INSN_RTE, "rte", "rte", 16,
999 
    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1000 
  },
1001 
/* seth $dr,$hash$hi16 */
1002 
  {
1003 
    M32R_INSN_SETH, "seth", "seth", 32,
1004 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1005 
  },
1006 
/* sll $dr,$sr */
1007 
  {
1008 
    M32R_INSN_SLL, "sll", "sll", 16,
1009 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
1010 
  },
1011 
/* sll3 $dr,$sr,$simm16 */
1012 
  {
1013 
    M32R_INSN_SLL3, "sll3", "sll3", 32,
1014 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1015 
  },
1016 
/* slli $dr,$uimm5 */
1017 
  {
1018 
    M32R_INSN_SLLI, "slli", "slli", 16,
1019 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
1020 
  },
1021 
/* sra $dr,$sr */
1022 
  {
1023 
    M32R_INSN_SRA, "sra", "sra", 16,
1024 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
1025 
  },
1026 
/* sra3 $dr,$sr,$simm16 */
1027 
  {
1028 
    M32R_INSN_SRA3, "sra3", "sra3", 32,
1029 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1030 
  },
1031 
/* srai $dr,$uimm5 */
1032 
  {
1033 
    M32R_INSN_SRAI, "srai", "srai", 16,
1034 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
1035 
  },
1036 
/* srl $dr,$sr */
1037 
  {
1038 
    M32R_INSN_SRL, "srl", "srl", 16,
1039 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
1040 
  },
1041 
/* srl3 $dr,$sr,$simm16 */
1042 
  {
1043 
    M32R_INSN_SRL3, "srl3", "srl3", 32,
1044 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1045 
  },
1046 
/* srli $dr,$uimm5 */
1047 
  {
1048 
    M32R_INSN_SRLI, "srli", "srli", 16,
1049 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
1050 
  },
1051 
/* st $src1,@$src2 */
1052 
  {
1053 
    M32R_INSN_ST, "st", "st", 16,
1054 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1055 
  },
1056 
/* st $src1,@($slo16,$src2) */
1057 
  {
1058 
    M32R_INSN_ST_D, "st-d", "st", 32,
1059 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1060 
  },
1061 
/* stb $src1,@$src2 */
1062 
  {
1063 
    M32R_INSN_STB, "stb", "stb", 16,
1064 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1065 
  },
1066 
/* stb $src1,@($slo16,$src2) */
1067 
  {
1068 
    M32R_INSN_STB_D, "stb-d", "stb", 32,
1069 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1070 
  },
1071 
/* sth $src1,@$src2 */
1072 
  {
1073 
    M32R_INSN_STH, "sth", "sth", 16,
1074 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1075 
  },
1076 
/* sth $src1,@($slo16,$src2) */
1077 
  {
1078 
    M32R_INSN_STH_D, "sth-d", "sth", 32,
1079 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1080 
  },
1081 
/* st $src1,@+$src2 */
1082 
  {
1083 
    M32R_INSN_ST_PLUS, "st-plus", "st", 16,
1084 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1085 
  },
1086 
/* sth $src1,@$src2+ */
1087 
  {
1088 
    M32R_INSN_STH_PLUS, "sth-plus", "sth", 16,
1089 
    { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
1090 
  },
1091 
/* stb $src1,@$src2+ */
1092 
  {
1093 
    M32R_INSN_STB_PLUS, "stb-plus", "stb", 16,
1094 
    { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
1095 
  },
1096 
/* st $src1,@-$src2 */
1097 
  {
1098 
    M32R_INSN_ST_MINUS, "st-minus", "st", 16,
1099 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1100 
  },
1101 
/* sub $dr,$sr */
1102 
  {
1103 
    M32R_INSN_SUB, "sub", "sub", 16,
1104 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1105 
  },
1106 
/* subv $dr,$sr */
1107 
  {
1108 
    M32R_INSN_SUBV, "subv", "subv", 16,
1109 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1110 
  },
1111 
/* subx $dr,$sr */
1112 
  {
1113 
    M32R_INSN_SUBX, "subx", "subx", 16,
1114 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1115 
  },
1116 
/* trap $uimm4 */
1117 
  {
1118 
    M32R_INSN_TRAP, "trap", "trap", 16,
1119 
    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1120 
  },
1121 
/* unlock $src1,@$src2 */
1122 
  {
1123 
    M32R_INSN_UNLOCK, "unlock", "unlock", 16,
1124 
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1125 
  },
1126 
/* satb $dr,$sr */
1127 
  {
1128 
    M32R_INSN_SATB, "satb", "satb", 32,
1129 
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
1130 
  },
1131 
/* sath $dr,$sr */
1132 
  {
1133 
    M32R_INSN_SATH, "sath", "sath", 32,
1134 
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
1135 
  },
1136 
/* sat $dr,$sr */
1137 
  {
1138 
    M32R_INSN_SAT, "sat", "sat", 32,
1139 
    { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
1140 
  },
1141 
/* pcmpbz $src2 */
1142 
  {
1143 
    M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz", 16,
1144 
    { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_OS, 0 } } } }
1145 
  },
1146 
/* sadd */
1147 
  {
1148 
    M32R_INSN_SADD, "sadd", "sadd", 16,
1149 
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
1150 
  },
1151 
/* macwu1 $src1,$src2 */
1152 
  {
1153 
    M32R_INSN_MACWU1, "macwu1", "macwu1", 16,
1154 
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
1155 
  },
1156 
/* msblo $src1,$src2 */
1157 
  {
1158 
    M32R_INSN_MSBLO, "msblo", "msblo", 16,
1159 
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
1160 
  },
1161 
/* mulwu1 $src1,$src2 */
1162 
  {
1163 
    M32R_INSN_MULWU1, "mulwu1", "mulwu1", 16,
1164 
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
1165 
  },
1166 
/* maclh1 $src1,$src2 */
1167 
  {
1168 
    M32R_INSN_MACLH1, "maclh1", "maclh1", 16,
1169 
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
1170 
  },
1171 
/* sc */
1172 
  {
1173 
    M32R_INSN_SC, "sc", "sc", 16,
1174 
    { 0|A(SPECIAL)|A(SKIP_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
1175 
  },
1176 
/* snc */
1177 
  {
1178 
    M32R_INSN_SNC, "snc", "snc", 16,
1179 
    { 0|A(SPECIAL)|A(SKIP_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
1180 
  },
1181 
/* clrpsw $uimm8 */
1182 
  {
1183 
    M32R_INSN_CLRPSW, "clrpsw", "clrpsw", 16,
1184 
    { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1185 
  },
1186 
/* setpsw $uimm8 */
1187 
  {
1188 
    M32R_INSN_SETPSW, "setpsw", "setpsw", 16,
1189 
    { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1190 
  },
1191 
/* bset $uimm3,@($slo16,$sr) */
1192 
  {
1193 
    M32R_INSN_BSET, "bset", "bset", 32,
1194 
    { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1195 
  },
1196 
/* bclr $uimm3,@($slo16,$sr) */
1197 
  {
1198 
    M32R_INSN_BCLR, "bclr", "bclr", 32,
1199 
    { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1200 
  },
1201 
/* btst $uimm3,$sr */
1202 
  {
1203 
    M32R_INSN_BTST, "btst", "btst", 16,
1204 
    { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1205 
  },
1206 
};
1207 
 
1208 
#undef OP
1209 
#undef A
1210 
 
1211 
/* Initialize anything needed to be done once, before any cpu_open call.  */
1212 
 
1213 
static void
1214 
init_tables (void)
1215 
{
1216 
}
1217 
 
1218 
static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
1219 
static void build_hw_table      (CGEN_CPU_TABLE *);
1220 
static void build_ifield_table  (CGEN_CPU_TABLE *);
1221 
static void build_operand_table (CGEN_CPU_TABLE *);
1222 
static void build_insn_table    (CGEN_CPU_TABLE *);
1223 
static void m32r_cgen_rebuild_tables (CGEN_CPU_TABLE *);
1224 
 
1225 
/* Subroutine of m32r_cgen_cpu_open to look up a mach via its bfd name.  */
1226 
 
1227 
static const CGEN_MACH *
1228 
lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
1229 
{
1230 
  while (table->name)
1231 
    {
1232 
      if (strcmp (name, table->bfd_name) == 0)
1233 
        return table;
1234 
      ++table;
1235 
    }
1236 
  abort ();
1237 
}
1238 
 
1239 
/* Subroutine of m32r_cgen_cpu_open to build the hardware table.  */
1240 
 
1241 
static void
1242 
build_hw_table (CGEN_CPU_TABLE *cd)
1243 
{
1244 
  int i;
1245 
  int machs = cd->machs;
1246 
  const CGEN_HW_ENTRY *init = & m32r_cgen_hw_table[0];
1247 
  /* MAX_HW is only an upper bound on the number of selected entries.
1248 
     However each entry is indexed by it's enum so there can be holes in
1249 
     the table.  */
1250 
  const CGEN_HW_ENTRY **selected =
1251 
    (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1252 
 
1253 
  cd->hw_table.init_entries = init;
1254 
  cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1255 
  memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1256 
  /* ??? For now we just use machs to determine which ones we want.  */
1257 
  for (i = 0; init[i].name != NULL; ++i)
1258 
    if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1259 
        & machs)
1260 
      selected[init[i].type] = &init[i];
1261 
  cd->hw_table.entries = selected;
1262 
  cd->hw_table.num_entries = MAX_HW;
1263 
}
1264 
 
1265 
/* Subroutine of m32r_cgen_cpu_open to build the hardware table.  */
1266 
 
1267 
static void
1268 
build_ifield_table (CGEN_CPU_TABLE *cd)
1269 
{
1270 
  cd->ifld_table = & m32r_cgen_ifld_table[0];
1271 
}
1272 
 
1273 
/* Subroutine of m32r_cgen_cpu_open to build the hardware table.  */
1274 
 
1275 
static void
1276 
build_operand_table (CGEN_CPU_TABLE *cd)
1277 
{
1278 
  int i;
1279 
  int machs = cd->machs;
1280 
  const CGEN_OPERAND *init = & m32r_cgen_operand_table[0];
1281 
  /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1282 
     However each entry is indexed by it's enum so there can be holes in
1283 
     the table.  */
1284 
  const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
1285 
 
1286 
  cd->operand_table.init_entries = init;
1287 
  cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1288 
  memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1289 
  /* ??? For now we just use mach to determine which ones we want.  */
1290 
  for (i = 0; init[i].name != NULL; ++i)
1291 
    if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1292 
        & machs)
1293 
      selected[init[i].type] = &init[i];
1294 
  cd->operand_table.entries = selected;
1295 
  cd->operand_table.num_entries = MAX_OPERANDS;
1296 
}
1297 
 
1298 
/* Subroutine of m32r_cgen_cpu_open to build the hardware table.
1299 
   ??? This could leave out insns not supported by the specified mach/isa,
1300 
   but that would cause errors like "foo only supported by bar" to become
1301 
   "unknown insn", so for now we include all insns and require the app to
1302 
   do the checking later.
1303 
   ??? On the other hand, parsing of such insns may require their hardware or
1304 
   operand elements to be in the table [which they mightn't be].  */
1305 
 
1306 
static void
1307 
build_insn_table (CGEN_CPU_TABLE *cd)
1308 
{
1309 
  int i;
1310 
  const CGEN_IBASE *ib = & m32r_cgen_insn_table[0];
1311 
  CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
1312 
 
1313 
  memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1314 
  for (i = 0; i < MAX_INSNS; ++i)
1315 
    insns[i].base = &ib[i];
1316 
  cd->insn_table.init_entries = insns;
1317 
  cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1318 
  cd->insn_table.num_init_entries = MAX_INSNS;
1319 
}
1320 
 
1321 
/* Subroutine of m32r_cgen_cpu_open to rebuild the tables.  */
1322 
 
1323 
static void
1324 
m32r_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
1325 
{
1326 
  int i;
1327 
  CGEN_BITSET *isas = cd->isas;
1328 
  unsigned int machs = cd->machs;
1329 
 
1330 
  cd->int_insn_p = CGEN_INT_INSN_P;
1331 
 
1332 
  /* Data derived from the isa spec.  */
1333 
#define UNSET (CGEN_SIZE_UNKNOWN + 1)
1334 
  cd->default_insn_bitsize = UNSET;
1335 
  cd->base_insn_bitsize = UNSET;
1336 
  cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
1337 
  cd->max_insn_bitsize = 0;
1338 
  for (i = 0; i < MAX_ISAS; ++i)
1339 
    if (cgen_bitset_contains (isas, i))
1340 
      {
1341 
        const CGEN_ISA *isa = & m32r_cgen_isa_table[i];
1342 
 
1343 
        /* Default insn sizes of all selected isas must be
1344 
           equal or we set the result to 0, meaning "unknown".  */
1345 
        if (cd->default_insn_bitsize == UNSET)
1346 
          cd->default_insn_bitsize = isa->default_insn_bitsize;
1347 
        else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
1348 
          ; /* This is ok.  */
1349 
        else
1350 
          cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
1351 
 
1352 
        /* Base insn sizes of all selected isas must be equal
1353 
           or we set the result to 0, meaning "unknown".  */
1354 
        if (cd->base_insn_bitsize == UNSET)
1355 
          cd->base_insn_bitsize = isa->base_insn_bitsize;
1356 
        else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
1357 
          ; /* This is ok.  */
1358 
        else
1359 
          cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
1360 
 
1361 
        /* Set min,max insn sizes.  */
1362 
        if (isa->min_insn_bitsize < cd->min_insn_bitsize)
1363 
          cd->min_insn_bitsize = isa->min_insn_bitsize;
1364 
        if (isa->max_insn_bitsize > cd->max_insn_bitsize)
1365 
          cd->max_insn_bitsize = isa->max_insn_bitsize;
1366 
      }
1367 
 
1368 
  /* Data derived from the mach spec.  */
1369 
  for (i = 0; i < MAX_MACHS; ++i)
1370 
    if (((1 << i) & machs) != 0)
1371 
      {
1372 
        const CGEN_MACH *mach = & m32r_cgen_mach_table[i];
1373 
 
1374 
        if (mach->insn_chunk_bitsize != 0)
1375 
        {
1376 
          if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
1377 
            {
1378 
              fprintf (stderr, "m32r_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
1379 
                       cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
1380 
              abort ();
1381 
            }
1382 
 
1383 
          cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
1384 
        }
1385 
      }
1386 
 
1387 
  /* Determine which hw elements are used by MACH.  */
1388 
  build_hw_table (cd);
1389 
 
1390 
  /* Build the ifield table.  */
1391 
  build_ifield_table (cd);
1392 
 
1393 
  /* Determine which operands are used by MACH/ISA.  */
1394 
  build_operand_table (cd);
1395 
 
1396 
  /* Build the instruction table.  */
1397 
  build_insn_table (cd);
1398 
}
1399 
 
1400 
/* Initialize a cpu table and return a descriptor.
1401 
   It's much like opening a file, and must be the first function called.
1402 
   The arguments are a set of (type/value) pairs, terminated with
1403 
   CGEN_CPU_OPEN_END.
1404 
 
1405 
   Currently supported values:
1406 
   CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
1407 
   CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
1408 
   CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
1409 
   CGEN_CPU_OPEN_ENDIAN:  specify endian choice
1410 
   CGEN_CPU_OPEN_END:     terminates arguments
1411 
 
1412 
   ??? Simultaneous multiple isas might not make sense, but it's not (yet)
1413 
   precluded.
1414 
 
1415 
   ??? We only support ISO C stdargs here, not K&R.
1416 
   Laziness, plus experiment to see if anything requires K&R - eventually
1417 
   K&R will no longer be supported - e.g. GDB is currently trying this.  */
1418 
 
1419 
CGEN_CPU_DESC
1420 
m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
1421 
{
1422 
  CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
1423 
  static int init_p;
1424 
  CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
1425 
  unsigned int machs = 0; /* 0 = "unspecified" */
1426 
  enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
1427 
  va_list ap;
1428 
 
1429 
  if (! init_p)
1430 
    {
1431 
      init_tables ();
1432 
      init_p = 1;
1433 
    }
1434 
 
1435 
  memset (cd, 0, sizeof (*cd));
1436 
 
1437 
  va_start (ap, arg_type);
1438 
  while (arg_type != CGEN_CPU_OPEN_END)
1439 
    {
1440 
      switch (arg_type)
1441 
        {
1442 
        case CGEN_CPU_OPEN_ISAS :
1443 
          isas = va_arg (ap, CGEN_BITSET *);
1444 
          break;
1445 
        case CGEN_CPU_OPEN_MACHS :
1446 
          machs = va_arg (ap, unsigned int);
1447 
          break;
1448 
        case CGEN_CPU_OPEN_BFDMACH :
1449 
          {
1450 
            const char *name = va_arg (ap, const char *);
1451 
            const CGEN_MACH *mach =
1452 
              lookup_mach_via_bfd_name (m32r_cgen_mach_table, name);
1453 
 
1454 
            machs |= 1 << mach->num;
1455 
            break;
1456 
          }
1457 
        case CGEN_CPU_OPEN_ENDIAN :
1458 
          endian = va_arg (ap, enum cgen_endian);
1459 
          break;
1460 
        default :
1461 
          fprintf (stderr, "m32r_cgen_cpu_open: unsupported argument `%d'\n",
1462 
                   arg_type);
1463 
          abort (); /* ??? return NULL? */
1464 
        }
1465 
      arg_type = va_arg (ap, enum cgen_cpu_open_arg);
1466 
    }
1467 
  va_end (ap);
1468 
 
1469 
  /* Mach unspecified means "all".  */
1470 
  if (machs == 0)
1471 
    machs = (1 << MAX_MACHS) - 1;
1472 
  /* Base mach is always selected.  */
1473 
  machs |= 1;
1474 
  if (endian == CGEN_ENDIAN_UNKNOWN)
1475 
    {
1476 
      /* ??? If target has only one, could have a default.  */
1477 
      fprintf (stderr, "m32r_cgen_cpu_open: no endianness specified\n");
1478 
      abort ();
1479 
    }
1480 
 
1481 
  cd->isas = cgen_bitset_copy (isas);
1482 
  cd->machs = machs;
1483 
  cd->endian = endian;
1484 
  /* FIXME: for the sparc case we can determine insn-endianness statically.
1485 
     The worry here is where both data and insn endian can be independently
1486 
     chosen, in which case this function will need another argument.
1487 
     Actually, will want to allow for more arguments in the future anyway.  */
1488 
  cd->insn_endian = endian;
1489 
 
1490 
  /* Table (re)builder.  */
1491 
  cd->rebuild_tables = m32r_cgen_rebuild_tables;
1492 
  m32r_cgen_rebuild_tables (cd);
1493 
 
1494 
  /* Default to not allowing signed overflow.  */
1495 
  cd->signed_overflow_ok_p = 0;
1496 
 
1497 
  return (CGEN_CPU_DESC) cd;
1498 
}
1499 
 
1500 
/* Cover fn to m32r_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
1501 
   MACH_NAME is the bfd name of the mach.  */
1502 
 
1503 
CGEN_CPU_DESC
1504 
m32r_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
1505 
{
1506 
  return m32r_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
1507 
                               CGEN_CPU_OPEN_ENDIAN, endian,
1508 
                               CGEN_CPU_OPEN_END);
1509 
}
1510 
 
1511 
/* Close a cpu table.
1512 
   ??? This can live in a machine independent file, but there's currently
1513 
   no place to put this file (there's no libcgen).  libopcodes is the wrong
1514 
   place as some simulator ports use this but they don't use libopcodes.  */
1515 
 
1516 
void
1517 
m32r_cgen_cpu_close (CGEN_CPU_DESC cd)
1518 
{
1519 
  unsigned int i;
1520 
  const CGEN_INSN *insns;
1521 
 
1522 
  if (cd->macro_insn_table.init_entries)
1523 
    {
1524 
      insns = cd->macro_insn_table.init_entries;
1525 
      for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
1526 
        if (CGEN_INSN_RX ((insns)))
1527 
          regfree (CGEN_INSN_RX (insns));
1528 
    }
1529 
 
1530 
  if (cd->insn_table.init_entries)
1531 
    {
1532 
      insns = cd->insn_table.init_entries;
1533 
      for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
1534 
        if (CGEN_INSN_RX (insns))
1535 
          regfree (CGEN_INSN_RX (insns));
1536 
    }
1537 
 
1538 
  if (cd->macro_insn_table.init_entries)
1539 
    free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
1540 
 
1541 
  if (cd->insn_table.init_entries)
1542 
    free ((CGEN_INSN *) cd->insn_table.init_entries);
1543 
 
1544 
  if (cd->hw_table.entries)
1545 
    free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
1546 
 
1547 
  if (cd->operand_table.entries)
1548 
    free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
1549 
 
1550 
  free (cd);
1551 
}
1552 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.