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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [opcodes/] [mt-desc.c] - Blame information for rev 321

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1 24 jeremybenn
/* CPU data for mt.
2
 
3
THIS FILE IS MACHINE GENERATED WITH CGEN.
4
 
5 225 jeremybenn
Copyright 1996-2009 Free Software Foundation, Inc.
6 24 jeremybenn
 
7
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8
 
9
   This file is free software; you can redistribute it and/or modify
10
   it under the terms of the GNU General Public License as published by
11
   the Free Software Foundation; either version 3, or (at your option)
12
   any later version.
13
 
14
   It is distributed in the hope that it will be useful, but WITHOUT
15
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
17
   License for more details.
18
 
19
   You should have received a copy of the GNU General Public License along
20
   with this program; if not, write to the Free Software Foundation, Inc.,
21
   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
22
 
23
*/
24
 
25
#include "sysdep.h"
26
#include <stdio.h>
27
#include <stdarg.h>
28
#include "ansidecl.h"
29
#include "bfd.h"
30
#include "symcat.h"
31
#include "mt-desc.h"
32
#include "mt-opc.h"
33
#include "opintl.h"
34
#include "libiberty.h"
35
#include "xregex.h"
36
 
37
/* Attributes.  */
38
 
39
static const CGEN_ATTR_ENTRY bool_attr[] =
40
{
41
  { "#f", 0 },
42
  { "#t", 1 },
43
  { 0, 0 }
44
};
45
 
46
static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
47
{
48
  { "base", MACH_BASE },
49
  { "ms1", MACH_MS1 },
50
  { "ms1_003", MACH_MS1_003 },
51
  { "ms2", MACH_MS2 },
52
  { "max", MACH_MAX },
53
  { 0, 0 }
54
};
55
 
56
static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
57
{
58
  { "mt", ISA_MT },
59
  { "max", ISA_MAX },
60
  { 0, 0 }
61
};
62
 
63
const CGEN_ATTR_TABLE mt_cgen_ifield_attr_table[] =
64
{
65
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
66
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
67
  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
68
  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
69
  { "RESERVED", &bool_attr[0], &bool_attr[0] },
70
  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
71
  { "SIGNED", &bool_attr[0], &bool_attr[0] },
72
  { 0, 0, 0 }
73
};
74
 
75
const CGEN_ATTR_TABLE mt_cgen_hardware_attr_table[] =
76
{
77
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
78
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
79
  { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
80
  { "PC", &bool_attr[0], &bool_attr[0] },
81
  { "PROFILE", &bool_attr[0], &bool_attr[0] },
82
  { 0, 0, 0 }
83
};
84
 
85
const CGEN_ATTR_TABLE mt_cgen_operand_attr_table[] =
86
{
87
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
88
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
89
  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
90
  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
91
  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
92
  { "SIGNED", &bool_attr[0], &bool_attr[0] },
93
  { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
94
  { "RELAX", &bool_attr[0], &bool_attr[0] },
95
  { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
96
  { 0, 0, 0 }
97
};
98
 
99
const CGEN_ATTR_TABLE mt_cgen_insn_attr_table[] =
100
{
101
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
102
  { "ALIAS", &bool_attr[0], &bool_attr[0] },
103
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
104
  { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
105
  { "COND-CTI", &bool_attr[0], &bool_attr[0] },
106
  { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
107
  { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
108
  { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
109
  { "RELAXED", &bool_attr[0], &bool_attr[0] },
110
  { "NO-DIS", &bool_attr[0], &bool_attr[0] },
111
  { "PBB", &bool_attr[0], &bool_attr[0] },
112
  { "LOAD-DELAY", &bool_attr[0], &bool_attr[0] },
113
  { "MEMORY-ACCESS", &bool_attr[0], &bool_attr[0] },
114
  { "AL-INSN", &bool_attr[0], &bool_attr[0] },
115
  { "IO-INSN", &bool_attr[0], &bool_attr[0] },
116
  { "BR-INSN", &bool_attr[0], &bool_attr[0] },
117
  { "JAL-HAZARD", &bool_attr[0], &bool_attr[0] },
118
  { "USES-FRDR", &bool_attr[0], &bool_attr[0] },
119
  { "USES-FRDRRR", &bool_attr[0], &bool_attr[0] },
120
  { "USES-FRSR1", &bool_attr[0], &bool_attr[0] },
121
  { "USES-FRSR2", &bool_attr[0], &bool_attr[0] },
122
  { "SKIPA", &bool_attr[0], &bool_attr[0] },
123
  { 0, 0, 0 }
124
};
125
 
126
/* Instruction set variants.  */
127
 
128
static const CGEN_ISA mt_cgen_isa_table[] = {
129
  { "mt", 32, 32, 32, 32 },
130
  { 0, 0, 0, 0, 0 }
131
};
132
 
133
/* Machine variants.  */
134
 
135
static const CGEN_MACH mt_cgen_mach_table[] = {
136
  { "ms1", "ms1", MACH_MS1, 0 },
137
  { "ms1-003", "ms1-003", MACH_MS1_003, 0 },
138
  { "ms2", "ms2", MACH_MS2, 0 },
139
  { 0, 0, 0, 0 }
140
};
141
 
142
static CGEN_KEYWORD_ENTRY mt_cgen_opval_msys_syms_entries[] =
143
{
144
  { "DUP", 1, {0, {{{0, 0}}}}, 0, 0 },
145
  { "XX", 0, {0, {{{0, 0}}}}, 0, 0 }
146
};
147
 
148
CGEN_KEYWORD mt_cgen_opval_msys_syms =
149
{
150
  & mt_cgen_opval_msys_syms_entries[0],
151
  2,
152
  0, 0, 0, 0, ""
153
};
154
 
155
static CGEN_KEYWORD_ENTRY mt_cgen_opval_h_spr_entries[] =
156
{
157
  { "R0", 0, {0, {{{0, 0}}}}, 0, 0 },
158
  { "R1", 1, {0, {{{0, 0}}}}, 0, 0 },
159
  { "R2", 2, {0, {{{0, 0}}}}, 0, 0 },
160
  { "R3", 3, {0, {{{0, 0}}}}, 0, 0 },
161
  { "R4", 4, {0, {{{0, 0}}}}, 0, 0 },
162
  { "R5", 5, {0, {{{0, 0}}}}, 0, 0 },
163
  { "R6", 6, {0, {{{0, 0}}}}, 0, 0 },
164
  { "R7", 7, {0, {{{0, 0}}}}, 0, 0 },
165
  { "R8", 8, {0, {{{0, 0}}}}, 0, 0 },
166
  { "R9", 9, {0, {{{0, 0}}}}, 0, 0 },
167
  { "R10", 10, {0, {{{0, 0}}}}, 0, 0 },
168
  { "R11", 11, {0, {{{0, 0}}}}, 0, 0 },
169
  { "R12", 12, {0, {{{0, 0}}}}, 0, 0 },
170
  { "fp", 12, {0, {{{0, 0}}}}, 0, 0 },
171
  { "R13", 13, {0, {{{0, 0}}}}, 0, 0 },
172
  { "sp", 13, {0, {{{0, 0}}}}, 0, 0 },
173
  { "R14", 14, {0, {{{0, 0}}}}, 0, 0 },
174
  { "ra", 14, {0, {{{0, 0}}}}, 0, 0 },
175
  { "R15", 15, {0, {{{0, 0}}}}, 0, 0 },
176
  { "ira", 15, {0, {{{0, 0}}}}, 0, 0 }
177
};
178
 
179
CGEN_KEYWORD mt_cgen_opval_h_spr =
180
{
181
  & mt_cgen_opval_h_spr_entries[0],
182
  20,
183
  0, 0, 0, 0, ""
184
};
185
 
186
 
187
/* The hardware table.  */
188
 
189
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
190
#define A(a) (1 << CGEN_HW_##a)
191
#else
192
#define A(a) (1 << CGEN_HW_/**/a)
193
#endif
194
 
195
const CGEN_HW_ENTRY mt_cgen_hw_table[] =
196
{
197
  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
198
  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
199
  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
200
  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
201
  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
202
  { "h-spr", HW_H_SPR, CGEN_ASM_KEYWORD, (PTR) & mt_cgen_opval_h_spr, { 0, { { { (1<<MACH_BASE), 0 } } } } },
203
  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
204
  { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
205
};
206
 
207
#undef A
208
 
209
 
210
/* The instruction field table.  */
211
 
212
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
213
#define A(a) (1 << CGEN_IFLD_##a)
214
#else
215
#define A(a) (1 << CGEN_IFLD_/**/a)
216
#endif
217
 
218
const CGEN_IFLD mt_cgen_ifld_table[] =
219
{
220
  { MT_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
221
  { MT_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
222
  { MT_F_MSYS, "f-msys", 0, 32, 31, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
223
  { MT_F_OPC, "f-opc", 0, 32, 30, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
224
  { MT_F_IMM, "f-imm", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
225
  { MT_F_UU24, "f-uu24", 0, 32, 23, 24, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
226
  { MT_F_SR1, "f-sr1", 0, 32, 23, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
227
  { MT_F_SR2, "f-sr2", 0, 32, 19, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
228
  { MT_F_DR, "f-dr", 0, 32, 19, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
229
  { MT_F_DRRR, "f-drrr", 0, 32, 15, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
230
  { MT_F_IMM16U, "f-imm16u", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
231
  { MT_F_IMM16S, "f-imm16s", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
232
  { MT_F_IMM16A, "f-imm16a", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
233
  { MT_F_UU4A, "f-uu4a", 0, 32, 19, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
234
  { MT_F_UU4B, "f-uu4b", 0, 32, 23, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
235
  { MT_F_UU12, "f-uu12", 0, 32, 11, 12, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
236
  { MT_F_UU8, "f-uu8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
237
  { MT_F_UU16, "f-uu16", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
238
  { MT_F_UU1, "f-uu1", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
239
  { MT_F_MSOPC, "f-msopc", 0, 32, 30, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
240
  { MT_F_UU_26_25, "f-uu-26-25", 0, 32, 25, 26, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
241
  { MT_F_MASK, "f-mask", 0, 32, 25, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
242
  { MT_F_BANKADDR, "f-bankaddr", 0, 32, 25, 13, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
243
  { MT_F_RDA, "f-rda", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
244
  { MT_F_UU_2_25, "f-uu-2-25", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
245
  { MT_F_RBBC, "f-rbbc", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
246
  { MT_F_PERM, "f-perm", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
247
  { MT_F_MODE, "f-mode", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
248
  { MT_F_UU_1_24, "f-uu-1-24", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
249
  { MT_F_WR, "f-wr", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
250
  { MT_F_FBINCR, "f-fbincr", 0, 32, 23, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
251
  { MT_F_UU_2_23, "f-uu-2-23", 0, 32, 23, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
252
  { MT_F_XMODE, "f-xmode", 0, 32, 23, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
253
  { MT_F_A23, "f-a23", 0, 32, 23, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
254
  { MT_F_MASK1, "f-mask1", 0, 32, 22, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
255
  { MT_F_CR, "f-cr", 0, 32, 22, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
256
  { MT_F_TYPE, "f-type", 0, 32, 21, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
257
  { MT_F_INCAMT, "f-incamt", 0, 32, 19, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
258
  { MT_F_CBS, "f-cbs", 0, 32, 19, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
259
  { MT_F_UU_1_19, "f-uu-1-19", 0, 32, 19, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
260
  { MT_F_BALL, "f-ball", 0, 32, 19, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
261
  { MT_F_COLNUM, "f-colnum", 0, 32, 18, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
262
  { MT_F_BRC, "f-brc", 0, 32, 18, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
263
  { MT_F_INCR, "f-incr", 0, 32, 17, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
264
  { MT_F_FBDISP, "f-fbdisp", 0, 32, 15, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
265
  { MT_F_UU_4_15, "f-uu-4-15", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
266
  { MT_F_LENGTH, "f-length", 0, 32, 15, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
267
  { MT_F_UU_1_15, "f-uu-1-15", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
268
  { MT_F_RC, "f-rc", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
269
  { MT_F_RCNUM, "f-rcnum", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
270
  { MT_F_ROWNUM, "f-rownum", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
271
  { MT_F_CBX, "f-cbx", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
272
  { MT_F_ID, "f-id", 0, 32, 14, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
273
  { MT_F_SIZE, "f-size", 0, 32, 13, 14, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
274
  { MT_F_ROWNUM1, "f-rownum1", 0, 32, 12, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
275
  { MT_F_UU_3_11, "f-uu-3-11", 0, 32, 11, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
276
  { MT_F_RC1, "f-rc1", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
277
  { MT_F_CCB, "f-ccb", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
278
  { MT_F_CBRB, "f-cbrb", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
279
  { MT_F_CDB, "f-cdb", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
280
  { MT_F_ROWNUM2, "f-rownum2", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
281
  { MT_F_CELL, "f-cell", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
282
  { MT_F_UU_3_9, "f-uu-3-9", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
283
  { MT_F_CONTNUM, "f-contnum", 0, 32, 8, 9, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
284
  { MT_F_UU_1_6, "f-uu-1-6", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
285
  { MT_F_DUP, "f-dup", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
286
  { MT_F_RC2, "f-rc2", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
287
  { MT_F_CTXDISP, "f-ctxdisp", 0, 32, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
288
  { MT_F_IMM16L, "f-imm16l", 0, 32, 23, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
289
  { MT_F_LOOPO, "f-loopo", 0, 32, 7, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
290
  { MT_F_CB1SEL, "f-cb1sel", 0, 32, 25, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
291
  { MT_F_CB2SEL, "f-cb2sel", 0, 32, 22, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
292
  { MT_F_CB1INCR, "f-cb1incr", 0, 32, 19, 6, { 0|A(SIGNED), { { { (1<<MACH_BASE), 0 } } } }  },
293
  { MT_F_CB2INCR, "f-cb2incr", 0, 32, 13, 6, { 0|A(SIGNED), { { { (1<<MACH_BASE), 0 } } } }  },
294
  { MT_F_RC3, "f-rc3", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
295
  { MT_F_MSYSFRSR2, "f-msysfrsr2", 0, 32, 19, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
296
  { MT_F_BRC2, "f-brc2", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
297
  { MT_F_BALL2, "f-ball2", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
298
  { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
299
};
300
 
301
#undef A
302
 
303
 
304
 
305
/* multi ifield declarations */
306
 
307
 
308
 
309
/* multi ifield definitions */
310
 
311
 
312
/* The operand table.  */
313
 
314
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
315
#define A(a) (1 << CGEN_OPERAND_##a)
316
#else
317
#define A(a) (1 << CGEN_OPERAND_/**/a)
318
#endif
319
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
320
#define OPERAND(op) MT_OPERAND_##op
321
#else
322
#define OPERAND(op) MT_OPERAND_/**/op
323
#endif
324
 
325
const CGEN_OPERAND mt_cgen_operand_table[] =
326
{
327
/* pc: program counter */
328
  { "pc", MT_OPERAND_PC, HW_H_PC, 0, 0,
329
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_NIL] } },
330
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
331
/* frsr1: register */
332
  { "frsr1", MT_OPERAND_FRSR1, HW_H_SPR, 23, 4,
333
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SR1] } },
334
    { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
335
/* frsr2: register */
336
  { "frsr2", MT_OPERAND_FRSR2, HW_H_SPR, 19, 4,
337
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SR2] } },
338
    { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
339
/* frdr: register */
340
  { "frdr", MT_OPERAND_FRDR, HW_H_SPR, 19, 4,
341
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DR] } },
342
    { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
343
/* frdrrr: register */
344
  { "frdrrr", MT_OPERAND_FRDRRR, HW_H_SPR, 15, 4,
345
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DRRR] } },
346
    { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
347
/* imm16: immediate value - sign extd */
348
  { "imm16", MT_OPERAND_IMM16, HW_H_SINT, 15, 16,
349
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16S] } },
350
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
351
/* imm16z: immediate value - zero extd */
352
  { "imm16z", MT_OPERAND_IMM16Z, HW_H_UINT, 15, 16,
353
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16U] } },
354
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
355
/* imm16o: immediate value */
356
  { "imm16o", MT_OPERAND_IMM16O, HW_H_UINT, 15, 16,
357
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16S] } },
358
    { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
359
/* rc: rc */
360
  { "rc", MT_OPERAND_RC, HW_H_UINT, 15, 1,
361
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC] } },
362
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
363
/* rcnum: rcnum */
364
  { "rcnum", MT_OPERAND_RCNUM, HW_H_UINT, 14, 3,
365
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RCNUM] } },
366
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
367
/* contnum: context number */
368
  { "contnum", MT_OPERAND_CONTNUM, HW_H_UINT, 8, 9,
369
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CONTNUM] } },
370
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
371
/* rbbc: omega network configuration */
372
  { "rbbc", MT_OPERAND_RBBC, HW_H_UINT, 25, 2,
373
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RBBC] } },
374
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
375
/* colnum: column number */
376
  { "colnum", MT_OPERAND_COLNUM, HW_H_UINT, 18, 3,
377
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_COLNUM] } },
378
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
379
/* rownum: row number */
380
  { "rownum", MT_OPERAND_ROWNUM, HW_H_UINT, 14, 3,
381
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM] } },
382
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
383
/* rownum1: row number */
384
  { "rownum1", MT_OPERAND_ROWNUM1, HW_H_UINT, 12, 3,
385
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM1] } },
386
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
387
/* rownum2: row number */
388
  { "rownum2", MT_OPERAND_ROWNUM2, HW_H_UINT, 9, 3,
389
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM2] } },
390
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
391
/* rc1: rc1 */
392
  { "rc1", MT_OPERAND_RC1, HW_H_UINT, 11, 1,
393
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC1] } },
394
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
395
/* rc2: rc2 */
396
  { "rc2", MT_OPERAND_RC2, HW_H_UINT, 6, 1,
397
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC2] } },
398
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
399
/* cbrb: data-bus orientation */
400
  { "cbrb", MT_OPERAND_CBRB, HW_H_UINT, 10, 1,
401
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBRB] } },
402
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
403
/* cell: cell */
404
  { "cell", MT_OPERAND_CELL, HW_H_UINT, 9, 3,
405
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CELL] } },
406
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
407
/* dup: dup */
408
  { "dup", MT_OPERAND_DUP, HW_H_UINT, 6, 1,
409
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DUP] } },
410
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
411
/* ctxdisp: context displacement */
412
  { "ctxdisp", MT_OPERAND_CTXDISP, HW_H_UINT, 5, 6,
413
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CTXDISP] } },
414
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
415
/* fbdisp: frame buffer displacement */
416
  { "fbdisp", MT_OPERAND_FBDISP, HW_H_UINT, 15, 6,
417
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_FBDISP] } },
418
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
419
/* type: type */
420
  { "type", MT_OPERAND_TYPE, HW_H_UINT, 21, 2,
421
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_TYPE] } },
422
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
423
/* mask: mask */
424
  { "mask", MT_OPERAND_MASK, HW_H_UINT, 25, 16,
425
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MASK] } },
426
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
427
/* bankaddr: bank address */
428
  { "bankaddr", MT_OPERAND_BANKADDR, HW_H_UINT, 25, 13,
429
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BANKADDR] } },
430
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
431
/* incamt: increment amount */
432
  { "incamt", MT_OPERAND_INCAMT, HW_H_UINT, 19, 8,
433
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_INCAMT] } },
434
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
435
/* xmode: xmode */
436
  { "xmode", MT_OPERAND_XMODE, HW_H_UINT, 23, 1,
437
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_XMODE] } },
438
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
439
/* mask1: mask1 */
440
  { "mask1", MT_OPERAND_MASK1, HW_H_UINT, 22, 3,
441
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MASK1] } },
442
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
443
/* ball: b_all */
444
  { "ball", MT_OPERAND_BALL, HW_H_UINT, 19, 1,
445
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BALL] } },
446
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
447
/* brc: b_r_c */
448
  { "brc", MT_OPERAND_BRC, HW_H_UINT, 18, 3,
449
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BRC] } },
450
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
451
/* rda: rd */
452
  { "rda", MT_OPERAND_RDA, HW_H_UINT, 25, 1,
453
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RDA] } },
454
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
455
/* wr: wr */
456
  { "wr", MT_OPERAND_WR, HW_H_UINT, 24, 1,
457
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_WR] } },
458
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
459
/* ball2: b_all2 */
460
  { "ball2", MT_OPERAND_BALL2, HW_H_UINT, 15, 1,
461
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BALL2] } },
462
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
463
/* brc2: b_r_c2 */
464
  { "brc2", MT_OPERAND_BRC2, HW_H_UINT, 14, 3,
465
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BRC2] } },
466
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
467
/* perm: perm */
468
  { "perm", MT_OPERAND_PERM, HW_H_UINT, 25, 2,
469
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_PERM] } },
470
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
471
/* a23: a23 */
472
  { "a23", MT_OPERAND_A23, HW_H_UINT, 23, 1,
473
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_A23] } },
474
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
475
/* cr: c-r */
476
  { "cr", MT_OPERAND_CR, HW_H_UINT, 22, 3,
477
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CR] } },
478
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
479
/* cbs: cbs */
480
  { "cbs", MT_OPERAND_CBS, HW_H_UINT, 19, 2,
481
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBS] } },
482
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
483
/* incr: incr */
484
  { "incr", MT_OPERAND_INCR, HW_H_UINT, 17, 6,
485
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_INCR] } },
486
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
487
/* length: length */
488
  { "length", MT_OPERAND_LENGTH, HW_H_UINT, 15, 3,
489
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_LENGTH] } },
490
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
491
/* cbx: cbx */
492
  { "cbx", MT_OPERAND_CBX, HW_H_UINT, 14, 3,
493
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBX] } },
494
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
495
/* ccb: ccb */
496
  { "ccb", MT_OPERAND_CCB, HW_H_UINT, 11, 1,
497
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CCB] } },
498
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
499
/* cdb: cdb */
500
  { "cdb", MT_OPERAND_CDB, HW_H_UINT, 10, 1,
501
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CDB] } },
502
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
503
/* mode: mode */
504
  { "mode", MT_OPERAND_MODE, HW_H_UINT, 25, 2,
505
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MODE] } },
506
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
507
/* id: i/d */
508
  { "id", MT_OPERAND_ID, HW_H_UINT, 14, 1,
509
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ID] } },
510
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
511
/* size: size */
512
  { "size", MT_OPERAND_SIZE, HW_H_UINT, 13, 14,
513
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SIZE] } },
514
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
515
/* fbincr: fb incr */
516
  { "fbincr", MT_OPERAND_FBINCR, HW_H_UINT, 23, 4,
517
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_FBINCR] } },
518
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
519
/* loopsize: immediate value */
520
  { "loopsize", MT_OPERAND_LOOPSIZE, HW_H_UINT, 7, 8,
521
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_LOOPO] } },
522
    { 0|A(PCREL_ADDR), { { { (1<<MACH_MS2), 0 } } } }  },
523
/* imm16l: immediate value */
524
  { "imm16l", MT_OPERAND_IMM16L, HW_H_UINT, 23, 16,
525
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16L] } },
526
    { 0, { { { (1<<MACH_MS2), 0 } } } }  },
527
/* rc3: rc3 */
528
  { "rc3", MT_OPERAND_RC3, HW_H_UINT, 7, 1,
529
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC3] } },
530
    { 0, { { { (1<<MACH_MS2), 0 } } } }  },
531
/* cb1sel: cb1sel */
532
  { "cb1sel", MT_OPERAND_CB1SEL, HW_H_UINT, 25, 3,
533
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB1SEL] } },
534
    { 0, { { { (1<<MACH_MS2), 0 } } } }  },
535
/* cb2sel: cb2sel */
536
  { "cb2sel", MT_OPERAND_CB2SEL, HW_H_UINT, 22, 3,
537
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB2SEL] } },
538
    { 0, { { { (1<<MACH_MS2), 0 } } } }  },
539
/* cb1incr: cb1incr */
540
  { "cb1incr", MT_OPERAND_CB1INCR, HW_H_SINT, 19, 6,
541
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB1INCR] } },
542
    { 0|A(SIGNED), { { { (1<<MACH_MS2), 0 } } } }  },
543
/* cb2incr: cb2incr */
544
  { "cb2incr", MT_OPERAND_CB2INCR, HW_H_SINT, 13, 6,
545
    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB2INCR] } },
546
    { 0|A(SIGNED), { { { (1<<MACH_MS2), 0 } } } }  },
547
/* sentinel */
548
  { 0, 0, 0, 0, 0,
549
    { 0, { (const PTR) 0 } },
550
    { 0, { { { (1<<MACH_BASE), 0 } } } } }
551
};
552
 
553
#undef A
554
 
555
 
556
/* The instruction table.  */
557
 
558
#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
559
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
560
#define A(a) (1 << CGEN_INSN_##a)
561
#else
562
#define A(a) (1 << CGEN_INSN_/**/a)
563
#endif
564
 
565
static const CGEN_IBASE mt_cgen_insn_table[MAX_INSNS] =
566
{
567
  /* Special null first entry.
568
     A `num' value of zero is thus invalid.
569
     Also, the special `invalid' insn resides here.  */
570
  { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
571
/* add $frdrrr,$frsr1,$frsr2 */
572
  {
573
    MT_INSN_ADD, "add", "add", 32,
574
    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
575
  },
576
/* addu $frdrrr,$frsr1,$frsr2 */
577
  {
578
    MT_INSN_ADDU, "addu", "addu", 32,
579
    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
580
  },
581
/* addi $frdr,$frsr1,#$imm16 */
582
  {
583
    MT_INSN_ADDI, "addi", "addi", 32,
584
    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
585
  },
586
/* addui $frdr,$frsr1,#$imm16z */
587
  {
588
    MT_INSN_ADDUI, "addui", "addui", 32,
589
    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
590
  },
591
/* sub $frdrrr,$frsr1,$frsr2 */
592
  {
593
    MT_INSN_SUB, "sub", "sub", 32,
594
    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
595
  },
596
/* subu $frdrrr,$frsr1,$frsr2 */
597
  {
598
    MT_INSN_SUBU, "subu", "subu", 32,
599
    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
600
  },
601
/* subi $frdr,$frsr1,#$imm16 */
602
  {
603
    MT_INSN_SUBI, "subi", "subi", 32,
604
    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
605
  },
606
/* subui $frdr,$frsr1,#$imm16z */
607
  {
608
    MT_INSN_SUBUI, "subui", "subui", 32,
609
    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
610
  },
611
/* mul $frdrrr,$frsr1,$frsr2 */
612
  {
613
    MT_INSN_MUL, "mul", "mul", 32,
614
    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
615
  },
616
/* muli $frdr,$frsr1,#$imm16 */
617
  {
618
    MT_INSN_MULI, "muli", "muli", 32,
619
    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
620
  },
621
/* and $frdrrr,$frsr1,$frsr2 */
622
  {
623
    MT_INSN_AND, "and", "and", 32,
624
    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
625
  },
626
/* andi $frdr,$frsr1,#$imm16z */
627
  {
628
    MT_INSN_ANDI, "andi", "andi", 32,
629
    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
630
  },
631
/* or $frdrrr,$frsr1,$frsr2 */
632
  {
633
    MT_INSN_OR, "or", "or", 32,
634
    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
635
  },
636
/* nop */
637
  {
638
    MT_INSN_NOP, "nop", "nop", 32,
639
    { 0, { { { (1<<MACH_BASE), 0 } } } }
640
  },
641
/* ori $frdr,$frsr1,#$imm16z */
642
  {
643
    MT_INSN_ORI, "ori", "ori", 32,
644
    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
645
  },
646
/* xor $frdrrr,$frsr1,$frsr2 */
647
  {
648
    MT_INSN_XOR, "xor", "xor", 32,
649
    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
650
  },
651
/* xori $frdr,$frsr1,#$imm16z */
652
  {
653
    MT_INSN_XORI, "xori", "xori", 32,
654
    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
655
  },
656
/* nand $frdrrr,$frsr1,$frsr2 */
657
  {
658
    MT_INSN_NAND, "nand", "nand", 32,
659
    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
660
  },
661
/* nandi $frdr,$frsr1,#$imm16z */
662
  {
663
    MT_INSN_NANDI, "nandi", "nandi", 32,
664
    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
665
  },
666
/* nor $frdrrr,$frsr1,$frsr2 */
667
  {
668
    MT_INSN_NOR, "nor", "nor", 32,
669
    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
670
  },
671
/* nori $frdr,$frsr1,#$imm16z */
672
  {
673
    MT_INSN_NORI, "nori", "nori", 32,
674
    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
675
  },
676
/* xnor $frdrrr,$frsr1,$frsr2 */
677
  {
678
    MT_INSN_XNOR, "xnor", "xnor", 32,
679
    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
680
  },
681
/* xnori $frdr,$frsr1,#$imm16z */
682
  {
683
    MT_INSN_XNORI, "xnori", "xnori", 32,
684
    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
685
  },
686
/* ldui $frdr,#$imm16z */
687
  {
688
    MT_INSN_LDUI, "ldui", "ldui", 32,
689
    { 0|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
690
  },
691
/* lsl $frdrrr,$frsr1,$frsr2 */
692
  {
693
    MT_INSN_LSL, "lsl", "lsl", 32,
694
    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR), { { { (1<<MACH_BASE), 0 } } } }
695
  },
696
/* lsli $frdr,$frsr1,#$imm16 */
697
  {
698
    MT_INSN_LSLI, "lsli", "lsli", 32,
699
    { 0|A(USES_FRSR1)|A(USES_FRDR), { { { (1<<MACH_BASE), 0 } } } }
700
  },
701
/* lsr $frdrrr,$frsr1,$frsr2 */
702
  {
703
    MT_INSN_LSR, "lsr", "lsr", 32,
704
    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR), { { { (1<<MACH_BASE), 0 } } } }
705
  },
706
/* lsri $frdr,$frsr1,#$imm16 */
707
  {
708
    MT_INSN_LSRI, "lsri", "lsri", 32,
709
    { 0|A(USES_FRSR1)|A(USES_FRDR), { { { (1<<MACH_BASE), 0 } } } }
710
  },
711
/* asr $frdrrr,$frsr1,$frsr2 */
712
  {
713
    MT_INSN_ASR, "asr", "asr", 32,
714
    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR), { { { (1<<MACH_BASE), 0 } } } }
715
  },
716
/* asri $frdr,$frsr1,#$imm16 */
717
  {
718
    MT_INSN_ASRI, "asri", "asri", 32,
719
    { 0|A(USES_FRSR1)|A(USES_FRDR), { { { (1<<MACH_BASE), 0 } } } }
720
  },
721
/* brlt $frsr1,$frsr2,$imm16o */
722
  {
723
    MT_INSN_BRLT, "brlt", "brlt", 32,
724
    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_BASE), 0 } } } }
725
  },
726
/* brle $frsr1,$frsr2,$imm16o */
727
  {
728
    MT_INSN_BRLE, "brle", "brle", 32,
729
    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_BASE), 0 } } } }
730
  },
731
/* breq $frsr1,$frsr2,$imm16o */
732
  {
733
    MT_INSN_BREQ, "breq", "breq", 32,
734
    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_BASE), 0 } } } }
735
  },
736
/* brne $frsr1,$frsr2,$imm16o */
737
  {
738
    MT_INSN_BRNE, "brne", "brne", 32,
739
    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_BASE), 0 } } } }
740
  },
741
/* jmp $imm16o */
742
  {
743
    MT_INSN_JMP, "jmp", "jmp", 32,
744
    { 0|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
745
  },
746
/* jal $frdrrr,$frsr1 */
747
  {
748
    MT_INSN_JAL, "jal", "jal", 32,
749
    { 0|A(JAL_HAZARD)|A(USES_FRSR1)|A(USES_FRDR)|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
750
  },
751
/* dbnz $frsr1,$imm16o */
752
  {
753
    MT_INSN_DBNZ, "dbnz", "dbnz", 32,
754
    { 0|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
755
  },
756
/* ei */
757
  {
758
    MT_INSN_EI, "ei", "ei", 32,
759
    { 0, { { { (1<<MACH_BASE), 0 } } } }
760
  },
761
/* di */
762
  {
763
    MT_INSN_DI, "di", "di", 32,
764
    { 0, { { { (1<<MACH_BASE), 0 } } } }
765
  },
766
/* si $frdrrr */
767
  {
768
    MT_INSN_SI, "si", "si", 32,
769
    { 0|A(USES_FRDR)|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
770
  },
771
/* reti $frsr1 */
772
  {
773
    MT_INSN_RETI, "reti", "reti", 32,
774
    { 0|A(JAL_HAZARD)|A(USES_FRSR1)|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
775
  },
776
/* ldw $frdr,$frsr1,#$imm16 */
777
  {
778
    MT_INSN_LDW, "ldw", "ldw", 32,
779
    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(MEMORY_ACCESS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } }
780
  },
781
/* stw $frsr2,$frsr1,#$imm16 */
782
  {
783
    MT_INSN_STW, "stw", "stw", 32,
784
    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(MEMORY_ACCESS), { { { (1<<MACH_BASE), 0 } } } }
785
  },
786
/* break */
787
  {
788
    MT_INSN_BREAK, "break", "break", 32,
789
    { 0, { { { (1<<MACH_BASE), 0 } } } }
790
  },
791
/* iflush */
792
  {
793
    MT_INSN_IFLUSH, "iflush", "iflush", 32,
794
    { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
795
  },
796
/* ldctxt $frsr1,$frsr2,#$rc,#$rcnum,#$contnum */
797
  {
798
    MT_INSN_LDCTXT, "ldctxt", "ldctxt", 32,
799
    { 0, { { { (1<<MACH_MS1), 0 } } } }
800
  },
801
/* ldfb $frsr1,$frsr2,#$imm16z */
802
  {
803
    MT_INSN_LDFB, "ldfb", "ldfb", 32,
804
    { 0, { { { (1<<MACH_MS1), 0 } } } }
805
  },
806
/* stfb $frsr1,$frsr2,#$imm16z */
807
  {
808
    MT_INSN_STFB, "stfb", "stfb", 32,
809
    { 0, { { { (1<<MACH_MS1), 0 } } } }
810
  },
811
/* fbcb $frsr1,#$rbbc,#$ball,#$brc,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
812
  {
813
    MT_INSN_FBCB, "fbcb", "fbcb", 32,
814
    { 0, { { { (1<<MACH_MS1)|(1<<MACH_MS1_003), 0 } } } }
815
  },
816
/* mfbcb $frsr1,#$rbbc,$frsr2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
817
  {
818
    MT_INSN_MFBCB, "mfbcb", "mfbcb", 32,
819
    { 0, { { { (1<<MACH_BASE), 0 } } } }
820
  },
821
/* fbcci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */
822
  {
823
    MT_INSN_FBCCI, "fbcci", "fbcci", 32,
824
    { 0, { { { (1<<MACH_BASE), 0 } } } }
825
  },
826
/* fbrci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */
827
  {
828
    MT_INSN_FBRCI, "fbrci", "fbrci", 32,
829
    { 0, { { { (1<<MACH_BASE), 0 } } } }
830
  },
831
/* fbcri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */
832
  {
833
    MT_INSN_FBCRI, "fbcri", "fbcri", 32,
834
    { 0, { { { (1<<MACH_BASE), 0 } } } }
835
  },
836
/* fbrri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */
837
  {
838
    MT_INSN_FBRRI, "fbrri", "fbrri", 32,
839
    { 0, { { { (1<<MACH_BASE), 0 } } } }
840
  },
841
/* mfbcci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */
842
  {
843
    MT_INSN_MFBCCI, "mfbcci", "mfbcci", 32,
844
    { 0, { { { (1<<MACH_BASE), 0 } } } }
845
  },
846
/* mfbrci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */
847
  {
848
    MT_INSN_MFBRCI, "mfbrci", "mfbrci", 32,
849
    { 0, { { { (1<<MACH_BASE), 0 } } } }
850
  },
851
/* mfbcri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */
852
  {
853
    MT_INSN_MFBCRI, "mfbcri", "mfbcri", 32,
854
    { 0, { { { (1<<MACH_BASE), 0 } } } }
855
  },
856
/* mfbrri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */
857
  {
858
    MT_INSN_MFBRRI, "mfbrri", "mfbrri", 32,
859
    { 0, { { { (1<<MACH_BASE), 0 } } } }
860
  },
861
/* fbcbdr $frsr1,#$rbbc,$frsr2,#$ball2,#$brc2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
862
  {
863
    MT_INSN_FBCBDR, "fbcbdr", "fbcbdr", 32,
864
    { 0, { { { (1<<MACH_BASE), 0 } } } }
865
  },
866
/* rcfbcb #$rbbc,#$type,#$ball,#$brc,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
867
  {
868
    MT_INSN_RCFBCB, "rcfbcb", "rcfbcb", 32,
869
    { 0, { { { (1<<MACH_BASE), 0 } } } }
870
  },
871
/* mrcfbcb $frsr2,#$rbbc,#$type,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
872
  {
873
    MT_INSN_MRCFBCB, "mrcfbcb", "mrcfbcb", 32,
874
    { 0, { { { (1<<MACH_BASE), 0 } } } }
875
  },
876
/* cbcast #$mask,#$rc2,#$ctxdisp */
877
  {
878
    MT_INSN_CBCAST, "cbcast", "cbcast", 32,
879
    { 0, { { { (1<<MACH_BASE), 0 } } } }
880
  },
881
/* dupcbcast #$mask,#$cell,#$rc2,#$ctxdisp */
882
  {
883
    MT_INSN_DUPCBCAST, "dupcbcast", "dupcbcast", 32,
884
    { 0, { { { (1<<MACH_BASE), 0 } } } }
885
  },
886
/* wfbi #$bankaddr,#$rownum1,#$cell,#$dup,#$ctxdisp */
887
  {
888
    MT_INSN_WFBI, "wfbi", "wfbi", 32,
889
    { 0, { { { (1<<MACH_BASE), 0 } } } }
890
  },
891
/* wfb $frsr1,$frsr2,#$fbdisp,#$rownum2,#$ctxdisp */
892
  {
893
    MT_INSN_WFB, "wfb", "wfb", 32,
894
    { 0, { { { (1<<MACH_BASE), 0 } } } }
895
  },
896
/* rcrisc $frdrrr,#$rbbc,$frsr1,#$colnum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
897
  {
898
    MT_INSN_RCRISC, "rcrisc", "rcrisc", 32,
899
    { 0, { { { (1<<MACH_BASE), 0 } } } }
900
  },
901
/* fbcbinc $frsr1,#$rbbc,#$incamt,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
902
  {
903
    MT_INSN_FBCBINC, "fbcbinc", "fbcbinc", 32,
904
    { 0, { { { (1<<MACH_BASE), 0 } } } }
905
  },
906
/* rcxmode $frsr2,#$rda,#$wr,#$xmode,#$mask1,#$fbdisp,#$rownum2,#$rc2,#$ctxdisp */
907
  {
908
    MT_INSN_RCXMODE, "rcxmode", "rcxmode", 32,
909
    { 0, { { { (1<<MACH_BASE), 0 } } } }
910
  },
911
/* intlvr $frsr1,#$mode,$frsr2,#$id,#$size */
912
  {
913
    MT_INSN_INTERLEAVER, "interleaver", "intlvr", 32,
914
    { 0, { { { (1<<MACH_BASE), 0 } } } }
915
  },
916
/* wfbinc #$rda,#$wr,#$fbincr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
917
  {
918
    MT_INSN_WFBINC, "wfbinc", "wfbinc", 32,
919
    { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
920
  },
921
/* mwfbinc $frsr2,#$rda,#$wr,#$fbincr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
922
  {
923
    MT_INSN_MWFBINC, "mwfbinc", "mwfbinc", 32,
924
    { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
925
  },
926
/* wfbincr $frsr1,#$rda,#$wr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
927
  {
928
    MT_INSN_WFBINCR, "wfbincr", "wfbincr", 32,
929
    { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
930
  },
931
/* mwfbincr $frsr1,$frsr2,#$rda,#$wr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
932
  {
933
    MT_INSN_MWFBINCR, "mwfbincr", "mwfbincr", 32,
934
    { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
935
  },
936
/* fbcbincs #$perm,#$a23,#$cr,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
937
  {
938
    MT_INSN_FBCBINCS, "fbcbincs", "fbcbincs", 32,
939
    { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
940
  },
941
/* mfbcbincs $frsr1,#$perm,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
942
  {
943
    MT_INSN_MFBCBINCS, "mfbcbincs", "mfbcbincs", 32,
944
    { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
945
  },
946
/* fbcbincrs $frsr1,#$perm,#$ball,#$colnum,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
947
  {
948
    MT_INSN_FBCBINCRS, "fbcbincrs", "fbcbincrs", 32,
949
    { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
950
  },
951
/* mfbcbincrs $frsr1,$frsr2,#$perm,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
952
  {
953
    MT_INSN_MFBCBINCRS, "mfbcbincrs", "mfbcbincrs", 32,
954
    { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
955
  },
956
/* loop $frsr1,$loopsize */
957
  {
958
    MT_INSN_LOOP, "loop", "loop", 32,
959
    { 0|A(USES_FRSR1)|A(DELAY_SLOT), { { { (1<<MACH_MS2), 0 } } } }
960
  },
961
/* loopi #$imm16l,$loopsize */
962
  {
963
    MT_INSN_LOOPI, "loopi", "loopi", 32,
964
    { 0|A(DELAY_SLOT), { { { (1<<MACH_MS2), 0 } } } }
965
  },
966
/* dfbc #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp */
967
  {
968
    MT_INSN_DFBC, "dfbc", "dfbc", 32,
969
    { 0, { { { (1<<MACH_MS2), 0 } } } }
970
  },
971
/* dwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc2,#$ctxdisp */
972
  {
973
    MT_INSN_DWFB, "dwfb", "dwfb", 32,
974
    { 0, { { { (1<<MACH_MS2), 0 } } } }
975
  },
976
/* fbwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp */
977
  {
978
    MT_INSN_FBWFB, "fbwfb", "fbwfb", 32,
979
    { 0, { { { (1<<MACH_MS2), 0 } } } }
980
  },
981
/* dfbr #$cb1sel,#$cb2sel,$frsr2,#$length,#$rownum1,#$rownum2,#$rc2,#$ctxdisp */
982
  {
983
    MT_INSN_DFBR, "dfbr", "dfbr", 32,
984
    { 0|A(USES_FRSR2), { { { (1<<MACH_MS2), 0 } } } }
985
  },
986
};
987
 
988
#undef OP
989
#undef A
990
 
991
/* Initialize anything needed to be done once, before any cpu_open call.  */
992
 
993
static void
994
init_tables (void)
995
{
996
}
997
 
998
static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
999
static void build_hw_table      (CGEN_CPU_TABLE *);
1000
static void build_ifield_table  (CGEN_CPU_TABLE *);
1001
static void build_operand_table (CGEN_CPU_TABLE *);
1002
static void build_insn_table    (CGEN_CPU_TABLE *);
1003
static void mt_cgen_rebuild_tables (CGEN_CPU_TABLE *);
1004
 
1005
/* Subroutine of mt_cgen_cpu_open to look up a mach via its bfd name.  */
1006
 
1007
static const CGEN_MACH *
1008
lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
1009
{
1010
  while (table->name)
1011
    {
1012
      if (strcmp (name, table->bfd_name) == 0)
1013
        return table;
1014
      ++table;
1015
    }
1016
  abort ();
1017
}
1018
 
1019
/* Subroutine of mt_cgen_cpu_open to build the hardware table.  */
1020
 
1021
static void
1022
build_hw_table (CGEN_CPU_TABLE *cd)
1023
{
1024
  int i;
1025
  int machs = cd->machs;
1026
  const CGEN_HW_ENTRY *init = & mt_cgen_hw_table[0];
1027
  /* MAX_HW is only an upper bound on the number of selected entries.
1028
     However each entry is indexed by it's enum so there can be holes in
1029
     the table.  */
1030
  const CGEN_HW_ENTRY **selected =
1031
    (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1032
 
1033
  cd->hw_table.init_entries = init;
1034
  cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1035
  memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1036
  /* ??? For now we just use machs to determine which ones we want.  */
1037
  for (i = 0; init[i].name != NULL; ++i)
1038
    if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1039
        & machs)
1040
      selected[init[i].type] = &init[i];
1041
  cd->hw_table.entries = selected;
1042
  cd->hw_table.num_entries = MAX_HW;
1043
}
1044
 
1045
/* Subroutine of mt_cgen_cpu_open to build the hardware table.  */
1046
 
1047
static void
1048
build_ifield_table (CGEN_CPU_TABLE *cd)
1049
{
1050
  cd->ifld_table = & mt_cgen_ifld_table[0];
1051
}
1052
 
1053
/* Subroutine of mt_cgen_cpu_open to build the hardware table.  */
1054
 
1055
static void
1056
build_operand_table (CGEN_CPU_TABLE *cd)
1057
{
1058
  int i;
1059
  int machs = cd->machs;
1060
  const CGEN_OPERAND *init = & mt_cgen_operand_table[0];
1061
  /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1062
     However each entry is indexed by it's enum so there can be holes in
1063
     the table.  */
1064
  const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
1065
 
1066
  cd->operand_table.init_entries = init;
1067
  cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1068
  memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1069
  /* ??? For now we just use mach to determine which ones we want.  */
1070
  for (i = 0; init[i].name != NULL; ++i)
1071
    if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1072
        & machs)
1073
      selected[init[i].type] = &init[i];
1074
  cd->operand_table.entries = selected;
1075
  cd->operand_table.num_entries = MAX_OPERANDS;
1076
}
1077
 
1078
/* Subroutine of mt_cgen_cpu_open to build the hardware table.
1079
   ??? This could leave out insns not supported by the specified mach/isa,
1080
   but that would cause errors like "foo only supported by bar" to become
1081
   "unknown insn", so for now we include all insns and require the app to
1082
   do the checking later.
1083
   ??? On the other hand, parsing of such insns may require their hardware or
1084
   operand elements to be in the table [which they mightn't be].  */
1085
 
1086
static void
1087
build_insn_table (CGEN_CPU_TABLE *cd)
1088
{
1089
  int i;
1090
  const CGEN_IBASE *ib = & mt_cgen_insn_table[0];
1091
  CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
1092
 
1093
  memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1094
  for (i = 0; i < MAX_INSNS; ++i)
1095
    insns[i].base = &ib[i];
1096
  cd->insn_table.init_entries = insns;
1097
  cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1098
  cd->insn_table.num_init_entries = MAX_INSNS;
1099
}
1100
 
1101
/* Subroutine of mt_cgen_cpu_open to rebuild the tables.  */
1102
 
1103
static void
1104
mt_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
1105
{
1106
  int i;
1107
  CGEN_BITSET *isas = cd->isas;
1108
  unsigned int machs = cd->machs;
1109
 
1110
  cd->int_insn_p = CGEN_INT_INSN_P;
1111
 
1112
  /* Data derived from the isa spec.  */
1113
#define UNSET (CGEN_SIZE_UNKNOWN + 1)
1114
  cd->default_insn_bitsize = UNSET;
1115
  cd->base_insn_bitsize = UNSET;
1116
  cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
1117
  cd->max_insn_bitsize = 0;
1118
  for (i = 0; i < MAX_ISAS; ++i)
1119
    if (cgen_bitset_contains (isas, i))
1120
      {
1121
        const CGEN_ISA *isa = & mt_cgen_isa_table[i];
1122
 
1123
        /* Default insn sizes of all selected isas must be
1124
           equal or we set the result to 0, meaning "unknown".  */
1125
        if (cd->default_insn_bitsize == UNSET)
1126
          cd->default_insn_bitsize = isa->default_insn_bitsize;
1127
        else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
1128
          ; /* This is ok.  */
1129
        else
1130
          cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
1131
 
1132
        /* Base insn sizes of all selected isas must be equal
1133
           or we set the result to 0, meaning "unknown".  */
1134
        if (cd->base_insn_bitsize == UNSET)
1135
          cd->base_insn_bitsize = isa->base_insn_bitsize;
1136
        else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
1137
          ; /* This is ok.  */
1138
        else
1139
          cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
1140
 
1141
        /* Set min,max insn sizes.  */
1142
        if (isa->min_insn_bitsize < cd->min_insn_bitsize)
1143
          cd->min_insn_bitsize = isa->min_insn_bitsize;
1144
        if (isa->max_insn_bitsize > cd->max_insn_bitsize)
1145
          cd->max_insn_bitsize = isa->max_insn_bitsize;
1146
      }
1147
 
1148
  /* Data derived from the mach spec.  */
1149
  for (i = 0; i < MAX_MACHS; ++i)
1150
    if (((1 << i) & machs) != 0)
1151
      {
1152
        const CGEN_MACH *mach = & mt_cgen_mach_table[i];
1153
 
1154
        if (mach->insn_chunk_bitsize != 0)
1155
        {
1156
          if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
1157
            {
1158
              fprintf (stderr, "mt_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
1159
                       cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
1160
              abort ();
1161
            }
1162
 
1163
          cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
1164
        }
1165
      }
1166
 
1167
  /* Determine which hw elements are used by MACH.  */
1168
  build_hw_table (cd);
1169
 
1170
  /* Build the ifield table.  */
1171
  build_ifield_table (cd);
1172
 
1173
  /* Determine which operands are used by MACH/ISA.  */
1174
  build_operand_table (cd);
1175
 
1176
  /* Build the instruction table.  */
1177
  build_insn_table (cd);
1178
}
1179
 
1180
/* Initialize a cpu table and return a descriptor.
1181
   It's much like opening a file, and must be the first function called.
1182
   The arguments are a set of (type/value) pairs, terminated with
1183
   CGEN_CPU_OPEN_END.
1184
 
1185
   Currently supported values:
1186
   CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
1187
   CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
1188
   CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
1189
   CGEN_CPU_OPEN_ENDIAN:  specify endian choice
1190
   CGEN_CPU_OPEN_END:     terminates arguments
1191
 
1192
   ??? Simultaneous multiple isas might not make sense, but it's not (yet)
1193
   precluded.
1194
 
1195
   ??? We only support ISO C stdargs here, not K&R.
1196
   Laziness, plus experiment to see if anything requires K&R - eventually
1197
   K&R will no longer be supported - e.g. GDB is currently trying this.  */
1198
 
1199
CGEN_CPU_DESC
1200
mt_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
1201
{
1202
  CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
1203
  static int init_p;
1204
  CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
1205
  unsigned int machs = 0; /* 0 = "unspecified" */
1206
  enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
1207
  va_list ap;
1208
 
1209
  if (! init_p)
1210
    {
1211
      init_tables ();
1212
      init_p = 1;
1213
    }
1214
 
1215
  memset (cd, 0, sizeof (*cd));
1216
 
1217
  va_start (ap, arg_type);
1218
  while (arg_type != CGEN_CPU_OPEN_END)
1219
    {
1220
      switch (arg_type)
1221
        {
1222
        case CGEN_CPU_OPEN_ISAS :
1223
          isas = va_arg (ap, CGEN_BITSET *);
1224
          break;
1225
        case CGEN_CPU_OPEN_MACHS :
1226
          machs = va_arg (ap, unsigned int);
1227
          break;
1228
        case CGEN_CPU_OPEN_BFDMACH :
1229
          {
1230
            const char *name = va_arg (ap, const char *);
1231
            const CGEN_MACH *mach =
1232
              lookup_mach_via_bfd_name (mt_cgen_mach_table, name);
1233
 
1234
            machs |= 1 << mach->num;
1235
            break;
1236
          }
1237
        case CGEN_CPU_OPEN_ENDIAN :
1238
          endian = va_arg (ap, enum cgen_endian);
1239
          break;
1240
        default :
1241
          fprintf (stderr, "mt_cgen_cpu_open: unsupported argument `%d'\n",
1242
                   arg_type);
1243
          abort (); /* ??? return NULL? */
1244
        }
1245
      arg_type = va_arg (ap, enum cgen_cpu_open_arg);
1246
    }
1247
  va_end (ap);
1248
 
1249
  /* Mach unspecified means "all".  */
1250
  if (machs == 0)
1251
    machs = (1 << MAX_MACHS) - 1;
1252
  /* Base mach is always selected.  */
1253
  machs |= 1;
1254
  if (endian == CGEN_ENDIAN_UNKNOWN)
1255
    {
1256
      /* ??? If target has only one, could have a default.  */
1257
      fprintf (stderr, "mt_cgen_cpu_open: no endianness specified\n");
1258
      abort ();
1259
    }
1260
 
1261
  cd->isas = cgen_bitset_copy (isas);
1262
  cd->machs = machs;
1263
  cd->endian = endian;
1264
  /* FIXME: for the sparc case we can determine insn-endianness statically.
1265
     The worry here is where both data and insn endian can be independently
1266
     chosen, in which case this function will need another argument.
1267
     Actually, will want to allow for more arguments in the future anyway.  */
1268
  cd->insn_endian = endian;
1269
 
1270
  /* Table (re)builder.  */
1271
  cd->rebuild_tables = mt_cgen_rebuild_tables;
1272
  mt_cgen_rebuild_tables (cd);
1273
 
1274
  /* Default to not allowing signed overflow.  */
1275
  cd->signed_overflow_ok_p = 0;
1276
 
1277
  return (CGEN_CPU_DESC) cd;
1278
}
1279
 
1280
/* Cover fn to mt_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
1281
   MACH_NAME is the bfd name of the mach.  */
1282
 
1283
CGEN_CPU_DESC
1284
mt_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
1285
{
1286
  return mt_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
1287
                               CGEN_CPU_OPEN_ENDIAN, endian,
1288
                               CGEN_CPU_OPEN_END);
1289
}
1290
 
1291
/* Close a cpu table.
1292
   ??? This can live in a machine independent file, but there's currently
1293
   no place to put this file (there's no libcgen).  libopcodes is the wrong
1294
   place as some simulator ports use this but they don't use libopcodes.  */
1295
 
1296
void
1297
mt_cgen_cpu_close (CGEN_CPU_DESC cd)
1298
{
1299
  unsigned int i;
1300
  const CGEN_INSN *insns;
1301
 
1302
  if (cd->macro_insn_table.init_entries)
1303
    {
1304
      insns = cd->macro_insn_table.init_entries;
1305
      for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
1306
        if (CGEN_INSN_RX ((insns)))
1307
          regfree (CGEN_INSN_RX (insns));
1308
    }
1309
 
1310
  if (cd->insn_table.init_entries)
1311
    {
1312
      insns = cd->insn_table.init_entries;
1313
      for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
1314
        if (CGEN_INSN_RX (insns))
1315
          regfree (CGEN_INSN_RX (insns));
1316
    }
1317
 
1318
  if (cd->macro_insn_table.init_entries)
1319
    free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
1320
 
1321
  if (cd->insn_table.init_entries)
1322
    free ((CGEN_INSN *) cd->insn_table.init_entries);
1323
 
1324
  if (cd->hw_table.entries)
1325
    free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
1326
 
1327
  if (cd->operand_table.entries)
1328
    free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
1329
 
1330
  free (cd);
1331
}
1332
 

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