OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [opcodes/] [s390-opc.c] - Blame information for rev 225

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn 
/* s390-opc.c -- S390 opcode list
2 225 jeremybenn 
   Copyright 2000, 2001, 2003, 2005, 2007, 2008, 2009
3 
   Free Software Foundation, Inc.
4 24 jeremybenn 
   Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
5 
 
6 
   This file is part of the GNU opcodes library.
7 
 
8 
   This library is free software; you can redistribute it and/or modify
9 
   it under the terms of the GNU General Public License as published by
10 
   the Free Software Foundation; either version 3, or (at your option)
11 
   any later version.
12 
 
13 
   It is distributed in the hope that it will be useful, but WITHOUT
14 
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
16 
   License for more details.
17 
 
18 
   You should have received a copy of the GNU General Public License
19 
   along with this file; see the file COPYING.  If not, write to the
20 
   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
21 
   MA 02110-1301, USA.  */
22 
 
23 
#include <stdio.h>
24 
#include "ansidecl.h"
25 
#include "opcode/s390.h"
26 
 
27 
/* This file holds the S390 opcode table.  The opcode table
28 
   includes almost all of the extended instruction mnemonics.  This
29 
   permits the disassembler to use them, and simplifies the assembler
30 
   logic, at the cost of increasing the table size.  The table is
31 
   strictly constant data, so the compiler should be able to put it in
32 
   the .text section.
33 
 
34 
   This file also holds the operand table.  All knowledge about
35 
   inserting operands into instructions and vice-versa is kept in this
36 
   file.  */
37 
 
38 
/* The operands table.
39 
   The fields are bits, shift, insert, extract, flags.  */
40 
 
41 
const struct s390_operand s390_operands[] =
42 
{
43 
#define UNUSED 0
44 
  { 0, 0, 0 },                    /* Indicates the end of the operand list */
45 
 
46 225 jeremybenn 
/* General purpose register operands.  */
47 
 
48 24 jeremybenn 
#define R_8    1                  /* GPR starting at position 8 */
49 
  { 4, 8, S390_OPERAND_GPR },
50 
#define R_12   2                  /* GPR starting at position 12 */
51 
  { 4, 12, S390_OPERAND_GPR },
52 225 jeremybenn 
#define RO_12  3                 /* optional GPR starting at position 12 */
53 
  { 4, 12, S390_OPERAND_GPR|S390_OPERAND_OPTIONAL },
54 
#define R_16   4                  /* GPR starting at position 16 */
55 24 jeremybenn 
  { 4, 16, S390_OPERAND_GPR },
56 225 jeremybenn 
#define R_20   5                  /* GPR starting at position 20 */
57 24 jeremybenn 
  { 4, 20, S390_OPERAND_GPR },
58 225 jeremybenn 
#define R_24   6                  /* GPR starting at position 24 */
59 24 jeremybenn 
  { 4, 24, S390_OPERAND_GPR },
60 225 jeremybenn 
#define R_28   7                  /* GPR starting at position 28 */
61 24 jeremybenn 
  { 4, 28, S390_OPERAND_GPR },
62 225 jeremybenn 
#define RO_28  8                  /* optional GPR starting at position 28 */
63 
  { 4, 28, (S390_OPERAND_GPR | S390_OPERAND_OPTIONAL) },
64 
#define R_32   9                  /* GPR starting at position 32 */
65 24 jeremybenn 
  { 4, 32, S390_OPERAND_GPR },
66 
 
67 225 jeremybenn 
/* Floating point register operands.  */
68 
 
69 
#define F_8    10                 /* FPR starting at position 8 */
70 24 jeremybenn 
  { 4, 8, S390_OPERAND_FPR },
71 225 jeremybenn 
#define F_12   11                 /* FPR starting at position 12 */
72 24 jeremybenn 
  { 4, 12, S390_OPERAND_FPR },
73 225 jeremybenn 
#define F_16   12                 /* FPR starting at position 16 */
74 24 jeremybenn 
  { 4, 16, S390_OPERAND_FPR },
75 225 jeremybenn 
#define F_20   13                 /* FPR starting at position 16 */
76 24 jeremybenn 
  { 4, 16, S390_OPERAND_FPR },
77 225 jeremybenn 
#define F_24   14                 /* FPR starting at position 24 */
78 24 jeremybenn 
  { 4, 24, S390_OPERAND_FPR },
79 225 jeremybenn 
#define F_28   15                 /* FPR starting at position 28 */
80 24 jeremybenn 
  { 4, 28, S390_OPERAND_FPR },
81 225 jeremybenn 
#define F_32   16                 /* FPR starting at position 32 */
82 24 jeremybenn 
  { 4, 32, S390_OPERAND_FPR },
83 
 
84 225 jeremybenn 
/* Access register operands.  */
85 
 
86 
#define A_8    17                 /* Access reg. starting at position 8 */
87 24 jeremybenn 
  { 4, 8, S390_OPERAND_AR },
88 225 jeremybenn 
#define A_12   18                 /* Access reg. starting at position 12 */
89 24 jeremybenn 
  { 4, 12, S390_OPERAND_AR },
90 225 jeremybenn 
#define A_24   19                 /* Access reg. starting at position 24 */
91 24 jeremybenn 
  { 4, 24, S390_OPERAND_AR },
92 225 jeremybenn 
#define A_28   20                 /* Access reg. starting at position 28 */
93 24 jeremybenn 
  { 4, 28, S390_OPERAND_AR },
94 
 
95 225 jeremybenn 
/* Control register operands.  */
96 
 
97 
#define C_8    21                 /* Control reg. starting at position 8 */
98 24 jeremybenn 
  { 4, 8, S390_OPERAND_CR },
99 225 jeremybenn 
#define C_12   22                 /* Control reg. starting at position 12 */
100 24 jeremybenn 
  { 4, 12, S390_OPERAND_CR },
101 
 
102 225 jeremybenn 
/* Base register operands.  */
103 
 
104 
#define B_16   23                 /* Base register starting at position 16 */
105 24 jeremybenn 
  { 4, 16, S390_OPERAND_BASE|S390_OPERAND_GPR },
106 225 jeremybenn 
#define B_32   24                 /* Base register starting at position 32 */
107 24 jeremybenn 
  { 4, 32, S390_OPERAND_BASE|S390_OPERAND_GPR },
108 
 
109 225 jeremybenn 
#define X_12   25                 /* Index register starting at position 12 */
110 24 jeremybenn 
  { 4, 12, S390_OPERAND_INDEX|S390_OPERAND_GPR },
111 
 
112 225 jeremybenn 
/* Address displacement operands.  */
113 
 
114 
#define D_20   26                 /* Displacement starting at position 20 */
115 24 jeremybenn 
  { 12, 20, S390_OPERAND_DISP },
116 225 jeremybenn 
#define DO_20  27                 /* optional Displ. starting at position 20 */
117 
  { 12, 20, S390_OPERAND_DISP|S390_OPERAND_OPTIONAL },
118 
#define D_36   28                 /* Displacement starting at position 36 */
119 24 jeremybenn 
  { 12, 36, S390_OPERAND_DISP },
120 225 jeremybenn 
#define D20_20 29                 /* 20 bit displacement starting at 20 */
121 24 jeremybenn 
  { 20, 20, S390_OPERAND_DISP|S390_OPERAND_SIGNED },
122 
 
123 225 jeremybenn 
/* Length operands.  */
124 
 
125 
#define L4_8   30                 /* 4 bit length starting at position 8 */
126 24 jeremybenn 
  { 4, 8, S390_OPERAND_LENGTH },
127 225 jeremybenn 
#define L4_12  31                 /* 4 bit length starting at position 12 */
128 24 jeremybenn 
  { 4, 12, S390_OPERAND_LENGTH },
129 225 jeremybenn 
#define L8_8   32                 /* 8 bit length starting at position 8 */
130 24 jeremybenn 
  { 8, 8, S390_OPERAND_LENGTH },
131 
 
132 225 jeremybenn 
/* Signed immediate operands.  */
133 
 
134 
#define I8_8   33                 /* 8 bit signed value starting at 8 */
135 
  { 8, 8, S390_OPERAND_SIGNED },
136 
#define I8_32  34                 /* 8 bit signed value starting at 32 */
137 
  { 8, 32, S390_OPERAND_SIGNED },
138 
#define I16_16 35                 /* 16 bit signed value starting at 16 */
139 
  { 16, 16, S390_OPERAND_SIGNED },
140 
#define I16_32 36                 /* 16 bit signed value starting at 32 */
141 
  { 16, 32, S390_OPERAND_SIGNED },
142 
#define I32_16 37                 /* 32 bit signed value starting at 16 */
143 
  { 32, 16, S390_OPERAND_SIGNED },
144 
 
145 
/* Unsigned immediate operands.  */
146 
 
147 
#define U4_8   38                 /* 4 bit unsigned value starting at 8 */
148 24 jeremybenn 
  { 4, 8, 0 },
149 225 jeremybenn 
#define U4_12  39                 /* 4 bit unsigned value starting at 12 */
150 24 jeremybenn 
  { 4, 12, 0 },
151 225 jeremybenn 
#define U4_16  40                 /* 4 bit unsigned value starting at 16 */
152 24 jeremybenn 
  { 4, 16, 0 },
153 225 jeremybenn 
#define U4_20  41                 /* 4 bit unsigned value starting at 20 */
154 24 jeremybenn 
  { 4, 20, 0 },
155 225 jeremybenn 
#define U4_32  42                 /* 4 bit unsigned value starting at 32 */
156 
  { 4, 32, 0 },
157 
#define U8_8   43                 /* 8 bit unsigned value starting at 8 */
158 24 jeremybenn 
  { 8, 8, 0 },
159 225 jeremybenn 
#define U8_16  44                 /* 8 bit unsigned value starting at 16 */
160 24 jeremybenn 
  { 8, 16, 0 },
161 225 jeremybenn 
#define U8_24  45                 /* 8 bit unsigned value starting at 24 */
162 
  { 8, 24, 0 },
163 
#define U8_32  46                 /* 8 bit unsigned value starting at 32 */
164 
  { 8, 32, 0 },
165 
#define U16_16 47                 /* 16 bit unsigned value starting at 16 */
166 24 jeremybenn 
  { 16, 16, 0 },
167 225 jeremybenn 
#define U16_32 48                 /* 16 bit unsigned value starting at 32 */
168 
  { 16, 32, 0 },
169 
#define U32_16 49                 /* 32 bit unsigned value starting at 16 */
170 
  { 32, 16, 0 },
171 
 
172 
/* PC-relative address operands.  */
173 
 
174 
#define J16_16 50                 /* PC relative jump offset at 16 */
175 24 jeremybenn 
  { 16, 16, S390_OPERAND_PCREL },
176 225 jeremybenn 
#define J32_16 51                 /* PC relative long offset at 16 */
177 24 jeremybenn 
  { 32, 16, S390_OPERAND_PCREL },
178 225 jeremybenn 
 
179 
/* Conditional mask operands.  */
180 
 
181 
#define M_16   52                 /* 4 bit optional mask starting at 16 */
182 24 jeremybenn 
  { 4, 16, S390_OPERAND_OPTIONAL },
183 
 
184 
};
185 
 
186 
 
187 
/* Macros used to form opcodes.  */
188 
 
189 
/* 8/16/48 bit opcodes.  */
190 
#define OP8(x) { x, 0x00, 0x00, 0x00, 0x00, 0x00 }
191 
#define OP16(x) { x >> 8, x & 255, 0x00, 0x00, 0x00, 0x00 }
192 
#define OP48(x) { x >> 40, (x >> 32) & 255, (x >> 24) & 255, \
193 
                  (x >> 16) & 255, (x >> 8) & 255, x & 255}
194 
 
195 
/* The new format of the INSTR_x_y and MASK_x_y defines is based
196 
   on the following rules:
197 
   1) the middle part of the definition (x in INSTR_x_y) is the official
198 
      names of the instruction format that you can find in the principals
199 
      of operation.
200 
   2) the last part of the definition (y in INSTR_x_y) gives you an idea
201 
      which operands the binary represenation of the instruction has.
202 
      The meanings of the letters in y are:
203 
      a - access register
204 
      c - control register
205 
      d - displacement, 12 bit
206 
      f - floating pointer register
207 
      i - signed integer, 4, 8, 16 or 32 bit
208 
      l - length, 4 or 8 bit
209 
      p - pc relative
210 
      r - general purpose register
211 
      u - unsigned integer, 4, 8, 16 or 32 bit
212 
      m - mode field, 4 bit
213 
 
214 
      The order of the letters reflects the layout of the format in
215 
      storage and not the order of the paramaters of the instructions.
216 
      The use of the letters is not a 100% match with the PoP but it is
217 
      quite close.
218 
 
219 
      For example the instruction "mvo" is defined in the PoP as follows:
220 
 
221 
      MVO  D1(L1,B1),D2(L2,B2)   [SS]
222 
 
223 
      --------------------------------------
224 
      | 'F1' | L1 | L2 | B1 | D1 | B2 | D2 |
225 
      --------------------------------------
226 
 
227 
 
228 
      The instruction format is: INSTR_SS_LLRDRD / MASK_SS_LLRDRD.  */
229 
 
230 
#define INSTR_E          2, { 0,0,0,0,0,0 }                    /* e.g. pr    */
231 
#define INSTR_RIE_RRP    6, { R_8,R_12,J16_16,0,0,0 }          /* e.g. brxhg */
232 225 jeremybenn 
#define INSTR_RIE_RRPU   6, { R_8,R_12,U4_32,J16_16,0,0 }      /* e.g. crj   */
233 
#define INSTR_RIE_RRP0   6, { R_8,R_12,J16_16,0,0,0 }          /* e.g. crjne */
234 
#define INSTR_RIE_RUPI   6, { R_8,I8_32,U4_12,J16_16,0,0 }     /* e.g. cij   */
235 
#define INSTR_RIE_R0PI   6, { R_8,I8_32,J16_16,0,0,0 }         /* e.g. cijne */
236 
#define INSTR_RIE_RUPU   6, { R_8,U8_32,U4_12,J16_16,0,0 }     /* e.g. clij  */
237 
#define INSTR_RIE_R0PU   6, { R_8,U8_32,J16_16,0,0,0 }         /* e.g. clijne */
238 
#define INSTR_RIE_R0IU   6, { R_8,I16_16,U4_32,0,0,0 }         /* e.g. cit   */
239 
#define INSTR_RIE_R0I0   6, { R_8,I16_16,0,0,0,0 }             /* e.g. citne */
240 
#define INSTR_RIE_R0UU   6, { R_8,U16_16,U4_32,0,0,0 }         /* e.g. clfit */
241 
#define INSTR_RIE_R0U0   6, { R_8,U16_16,0,0,0,0 }             /* e.g. clfitne */
242 
#define INSTR_RIE_RRUUU  6, { R_8,R_12,U8_16,U8_24,U8_32,0 }   /* e.g. rnsbg */
243 24 jeremybenn 
#define INSTR_RIL_0P     6, { J32_16,0,0,0,0 }                 /* e.g. jg    */
244 
#define INSTR_RIL_RP     6, { R_8,J32_16,0,0,0,0 }             /* e.g. brasl */
245 
#define INSTR_RIL_UP     6, { U4_8,J32_16,0,0,0,0 }            /* e.g. brcl  */
246 
#define INSTR_RIL_RI     6, { R_8,I32_16,0,0,0,0 }             /* e.g. afi   */
247 
#define INSTR_RIL_RU     6, { R_8,U32_16,0,0,0,0 }             /* e.g. alfi  */
248 
#define INSTR_RI_0P      4, { J16_16,0,0,0,0,0 }               /* e.g. j     */
249 
#define INSTR_RI_RI      4, { R_8,I16_16,0,0,0,0 }             /* e.g. ahi   */
250 
#define INSTR_RI_RP      4, { R_8,J16_16,0,0,0,0 }             /* e.g. brct  */
251 
#define INSTR_RI_RU      4, { R_8,U16_16,0,0,0,0 }             /* e.g. tml   */
252 
#define INSTR_RI_UP      4, { U4_8,J16_16,0,0,0,0 }            /* e.g. brc   */
253 225 jeremybenn 
#define INSTR_RIS_RURDI  6, { R_8,I8_32,U4_12,D_20,B_16,0 }    /* e.g. cib   */
254 
#define INSTR_RIS_R0RDI  6, { R_8,I8_32,D_20,B_16,0,0 }        /* e.g. cibne */
255 
#define INSTR_RIS_RURDU  6, { R_8,U8_32,U4_12,D_20,B_16,0 }    /* e.g. clib  */
256 
#define INSTR_RIS_R0RDU  6, { R_8,U8_32,D_20,B_16,0,0 }        /* e.g. clibne*/
257 24 jeremybenn 
#define INSTR_RRE_00     4, { 0,0,0,0,0,0 }                    /* e.g. palb  */
258 
#define INSTR_RRE_0R     4, { R_28,0,0,0,0,0 }                 /* e.g. tb    */
259 
#define INSTR_RRE_AA     4, { A_24,A_28,0,0,0,0 }              /* e.g. cpya  */
260 
#define INSTR_RRE_AR     4, { A_24,R_28,0,0,0,0 }              /* e.g. sar   */
261 
#define INSTR_RRE_F0     4, { F_24,0,0,0,0,0 }                 /* e.g. sqer  */
262 
#define INSTR_RRE_FF     4, { F_24,F_28,0,0,0,0 }              /* e.g. debr  */
263 
#define INSTR_RRE_R0     4, { R_24,0,0,0,0,0 }                 /* e.g. ipm   */
264 
#define INSTR_RRE_RA     4, { R_24,A_28,0,0,0,0 }              /* e.g. ear   */
265 
#define INSTR_RRE_RF     4, { R_24,F_28,0,0,0,0 }              /* e.g. cefbr */
266 
#define INSTR_RRE_RR     4, { R_24,R_28,0,0,0,0 }              /* e.g. lura  */
267 
#define INSTR_RRE_FR     4, { F_24,R_28,0,0,0,0 }              /* e.g. ldgr  */
268 
/* Actually efpc and sfpc do not take an optional operand.
269 
   This is just a workaround for existing code e.g. glibc.  */
270 
#define INSTR_RRE_RR_OPT 4, { R_24,RO_28,0,0,0,0 }             /* efpc, sfpc */
271 
#define INSTR_RRF_F0FF   4, { F_16,F_24,F_28,0,0,0 }           /* e.g. madbr */
272 
#define INSTR_RRF_F0FF2  4, { F_24,F_16,F_28,0,0,0 }           /* e.g. cpsdr */
273 
#define INSTR_RRF_F0FR   4, { F_24,F_16,R_28,0,0,0 }           /* e.g. iedtr */
274 
#define INSTR_RRF_FUFF   4, { F_24,F_16,F_28,U4_20,0,0 }       /* e.g. didbr */
275 
#define INSTR_RRF_RURR   4, { R_24,R_28,R_16,U4_20,0,0 }       /* e.g. .insn */
276 225 jeremybenn 
#define INSTR_RRF_R0RR   4, { R_24,R_16,R_28,0,0,0 }           /* e.g. idte  */
277 24 jeremybenn 
#define INSTR_RRF_U0FF   4, { F_24,U4_16,F_28,0,0,0 }          /* e.g. fixr  */
278 
#define INSTR_RRF_U0RF   4, { R_24,U4_16,F_28,0,0,0 }          /* e.g. cfebr */
279 
#define INSTR_RRF_UUFF   4, { F_24,U4_16,F_28,U4_20,0,0 }      /* e.g. fidtr */
280 
#define INSTR_RRF_0UFF   4, { F_24,F_28,U4_20,0,0,0 }          /* e.g. ldetr */
281 225 jeremybenn 
#define INSTR_RRF_FFRU   4, { F_24,F_16,R_28,U4_20,0,0 }       /* e.g. rrdtr */
282 24 jeremybenn 
#define INSTR_RRF_M0RR   4, { R_24,R_28,M_16,0,0,0 }           /* e.g. sske  */
283 225 jeremybenn 
#define INSTR_RRF_U0RR   4, { R_24,R_28,U4_16,0,0,0 }          /* e.g. clrt  */
284 
#define INSTR_RRF_00RR   4, { R_24,R_28,0,0,0,0 }              /* e.g. clrtne */
285 24 jeremybenn 
#define INSTR_RR_0R      2, { R_12, 0,0,0,0,0 }                /* e.g. br    */
286 225 jeremybenn 
#define INSTR_RR_0R_OPT  2, { RO_12, 0,0,0,0,0 }               /* e.g. nopr  */
287 24 jeremybenn 
#define INSTR_RR_FF      2, { F_8,F_12,0,0,0,0 }               /* e.g. adr   */
288 
#define INSTR_RR_R0      2, { R_8, 0,0,0,0,0 }                 /* e.g. spm   */
289 
#define INSTR_RR_RR      2, { R_8,R_12,0,0,0,0 }               /* e.g. lr    */
290 
#define INSTR_RR_U0      2, { U8_8, 0,0,0,0,0 }                /* e.g. svc   */
291 
#define INSTR_RR_UR      2, { U4_8,R_12,0,0,0,0 }              /* e.g. bcr   */
292 
#define INSTR_RRR_F0FF   4, { F_24,F_28,F_16,0,0,0 }           /* e.g. ddtr  */
293 225 jeremybenn 
#define INSTR_RRS_RRRDU  6, { R_8,R_12,U4_32,D_20,B_16 }       /* e.g. crb   */
294 
#define INSTR_RRS_RRRD0  6, { R_8,R_12,D_20,B_16,0 }           /* e.g. crbne */
295 24 jeremybenn 
#define INSTR_RSE_RRRD   6, { R_8,R_12,D_20,B_16,0,0 }         /* e.g. lmh   */
296 
#define INSTR_RSE_CCRD   6, { C_8,C_12,D_20,B_16,0,0 }         /* e.g. lmh   */
297 
#define INSTR_RSE_RURD   6, { R_8,U4_12,D_20,B_16,0,0 }        /* e.g. icmh  */
298 225 jeremybenn 
#define INSTR_RSL_R0RD   6, { D_20,L4_8,B_16,0,0,0 }           /* e.g. tp    */
299 24 jeremybenn 
#define INSTR_RSI_RRP    4, { R_8,R_12,J16_16,0,0,0 }          /* e.g. brxh  */
300 
#define INSTR_RSY_RRRD   6, { R_8,R_12,D20_20,B_16,0,0 }       /* e.g. stmy  */
301 
#define INSTR_RSY_RURD   6, { R_8,U4_12,D20_20,B_16,0,0 }      /* e.g. icmh  */
302 
#define INSTR_RSY_AARD   6, { A_8,A_12,D20_20,B_16,0,0 }       /* e.g. lamy  */
303 
#define INSTR_RSY_CCRD   6, { C_8,C_12,D20_20,B_16,0,0 }       /* e.g. lamy  */
304 
#define INSTR_RS_AARD    4, { A_8,A_12,D_20,B_16,0,0 }         /* e.g. lam   */
305 
#define INSTR_RS_CCRD    4, { C_8,C_12,D_20,B_16,0,0 }         /* e.g. lctl  */
306 
#define INSTR_RS_R0RD    4, { R_8,D_20,B_16,0,0,0 }            /* e.g. sll   */
307 
#define INSTR_RS_RRRD    4, { R_8,R_12,D_20,B_16,0,0 }         /* e.g. cs    */
308 
#define INSTR_RS_RURD    4, { R_8,U4_12,D_20,B_16,0,0 }        /* e.g. icm   */
309 
#define INSTR_RXE_FRRD   6, { F_8,D_20,X_12,B_16,0,0 }         /* e.g. axbr  */
310 
#define INSTR_RXE_RRRD   6, { R_8,D_20,X_12,B_16,0,0 }         /* e.g. lg    */
311 
#define INSTR_RXF_FRRDF  6, { F_32,F_8,D_20,X_12,B_16,0 }      /* e.g. madb  */
312 
#define INSTR_RXF_RRRDR  6, { R_32,R_8,D_20,X_12,B_16,0 }      /* e.g. .insn */
313 
#define INSTR_RXY_RRRD   6, { R_8,D20_20,X_12,B_16,0,0 }       /* e.g. ly    */
314 
#define INSTR_RXY_FRRD   6, { F_8,D20_20,X_12,B_16,0,0 }       /* e.g. ley   */
315 225 jeremybenn 
#define INSTR_RXY_URRD   6, { U4_8,D20_20,X_12,B_16,0,0 }      /* e.g. pfd   */
316 24 jeremybenn 
#define INSTR_RX_0RRD    4, { D_20,X_12,B_16,0,0,0 }           /* e.g. be    */
317 225 jeremybenn 
#define INSTR_RX_0RRD_OPT 4, { DO_20,X_12,B_16,0,0,0 }         /* e.g. nop   */
318 24 jeremybenn 
#define INSTR_RX_FRRD    4, { F_8,D_20,X_12,B_16,0,0 }         /* e.g. ae    */
319 
#define INSTR_RX_RRRD    4, { R_8,D_20,X_12,B_16,0,0 }         /* e.g. l     */
320 
#define INSTR_RX_URRD    4, { U4_8,D_20,X_12,B_16,0,0 }        /* e.g. bc    */
321 
#define INSTR_SI_URD     4, { D_20,B_16,U8_8,0,0,0 }           /* e.g. cli   */
322 
#define INSTR_SIY_URD    6, { D20_20,B_16,U8_8,0,0,0 }         /* e.g. tmy   */
323 225 jeremybenn 
#define INSTR_SIY_IRD    6, { D20_20,B_16,I8_8,0,0,0 }         /* e.g. asi   */
324 
#define INSTR_SIL_RDI    6, { D_20,B_16,I16_32,0,0,0 }         /* e.g. chhsi */
325 
#define INSTR_SIL_RDU    6, { D_20,B_16,U16_32,0,0,0 }         /* e.g. clfhsi */
326 24 jeremybenn 
#define INSTR_SSE_RDRD   6, { D_20,B_16,D_36,B_32,0,0 }        /* e.g. mvsdk */
327 
#define INSTR_SS_L0RDRD  6, { D_20,L8_8,B_16,D_36,B_32,0     } /* e.g. mvc   */
328 
#define INSTR_SS_L2RDRD  6, { D_20,B_16,D_36,L8_8,B_32,0     } /* e.g. pka   */
329 
#define INSTR_SS_LIRDRD  6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp   */
330 
#define INSTR_SS_LLRDRD  6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack  */
331 
#define INSTR_SS_RRRDRD  6, { D_20,R_8,B_16,D_36,B_32,R_12 }   /* e.g. mvck  */
332 
#define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 }   /* e.g. plo   */
333 
#define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 }   /* e.g. lmd   */
334 225 jeremybenn 
#define INSTR_SSF_RRDRD  6, { D_20,B_16,D_36,B_32,R_8,0 }      /* e.g. mvcos */
335 24 jeremybenn 
#define INSTR_S_00       4, { 0,0,0,0,0,0 }                    /* e.g. hsch  */
336 
#define INSTR_S_RD       4, { D_20,B_16,0,0,0,0 }              /* e.g. lpsw  */
337 
 
338 
#define MASK_E           { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
339 
#define MASK_RIE_RRP     { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
340 225 jeremybenn 
#define MASK_RIE_RRPU    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
341 
#define MASK_RIE_RRP0    { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff }
342 
#define MASK_RIE_RUPI    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
343 
#define MASK_RIE_R0PI    { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff }
344 
#define MASK_RIE_RUPU    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
345 
#define MASK_RIE_R0PU    { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff }
346 
#define MASK_RIE_R0IU    { 0xff, 0x0f, 0x00, 0x00, 0x0f, 0xff }
347 
#define MASK_RIE_R0I0    { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff }
348 
#define MASK_RIE_R0UU    { 0xff, 0x0f, 0x00, 0x00, 0x0f, 0xff }
349 
#define MASK_RIE_R0U0    { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff }
350 
#define MASK_RIE_RRUUU   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
351 24 jeremybenn 
#define MASK_RIL_0P      { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
352 
#define MASK_RIL_RP      { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
353 
#define MASK_RIL_UP      { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
354 
#define MASK_RIL_RI      { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
355 
#define MASK_RIL_RU      { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
356 
#define MASK_RI_0P       { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
357 
#define MASK_RI_RI       { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
358 
#define MASK_RI_RP       { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
359 
#define MASK_RI_RU       { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
360 
#define MASK_RI_UP       { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
361 225 jeremybenn 
#define MASK_RIS_RURDI   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
362 
#define MASK_RIS_R0RDI   { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff }
363 
#define MASK_RIS_RURDU   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
364 
#define MASK_RIS_R0RDU   { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff }
365 24 jeremybenn 
#define MASK_RRE_00      { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
366 
#define MASK_RRE_0R      { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 }
367 
#define MASK_RRE_AA      { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
368 
#define MASK_RRE_AR      { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
369 
#define MASK_RRE_F0      { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
370 
#define MASK_RRE_FF      { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
371 
#define MASK_RRE_R0      { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
372 
#define MASK_RRE_RA      { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
373 
#define MASK_RRE_RF      { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
374 
#define MASK_RRE_RR      { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
375 
#define MASK_RRE_FR      { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
376 
#define MASK_RRE_RR_OPT  { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
377 
#define MASK_RRF_F0FF    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
378 
#define MASK_RRF_F0FF2   { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
379 
#define MASK_RRF_F0FR    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
380 
#define MASK_RRF_FUFF    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
381 
#define MASK_RRF_RURR    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
382 
#define MASK_RRF_R0RR    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
383 
#define MASK_RRF_U0FF    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
384 
#define MASK_RRF_U0RF    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
385 
#define MASK_RRF_UUFF    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
386 
#define MASK_RRF_0UFF    { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 }
387 225 jeremybenn 
#define MASK_RRF_FFRU    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
388 24 jeremybenn 
#define MASK_RRF_M0RR    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
389 225 jeremybenn 
#define MASK_RRF_U0RR    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
390 
#define MASK_RRF_00RR    { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
391 24 jeremybenn 
#define MASK_RR_0R       { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
392 225 jeremybenn 
#define MASK_RR_0R_OPT   { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
393 24 jeremybenn 
#define MASK_RR_FF       { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
394 
#define MASK_RR_R0       { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
395 
#define MASK_RR_RR       { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
396 
#define MASK_RR_U0       { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
397 
#define MASK_RR_UR       { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
398 
#define MASK_RRR_F0FF    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
399 225 jeremybenn 
#define MASK_RRS_RRRDU   { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff }
400 
#define MASK_RRS_RRRD0   { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
401 24 jeremybenn 
#define MASK_RSE_RRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
402 
#define MASK_RSE_CCRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
403 
#define MASK_RSE_RURD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
404 
#define MASK_RSL_R0RD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
405 
#define MASK_RSI_RRP     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
406 
#define MASK_RS_AARD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
407 
#define MASK_RS_CCRD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
408 
#define MASK_RS_R0RD     { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
409 
#define MASK_RS_RRRD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
410 
#define MASK_RS_RURD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
411 
#define MASK_RSY_RRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
412 
#define MASK_RSY_RURD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
413 
#define MASK_RSY_AARD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
414 
#define MASK_RSY_CCRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
415 
#define MASK_RXE_FRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
416 
#define MASK_RXE_RRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
417 
#define MASK_RXF_FRRDF   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
418 
#define MASK_RXF_RRRDR   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
419 
#define MASK_RXY_RRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
420 
#define MASK_RXY_FRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
421 225 jeremybenn 
#define MASK_RXY_URRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
422 24 jeremybenn 
#define MASK_RX_0RRD     { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
423 225 jeremybenn 
#define MASK_RX_0RRD_OPT { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
424 24 jeremybenn 
#define MASK_RX_FRRD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
425 
#define MASK_RX_RRRD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
426 
#define MASK_RX_URRD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
427 
#define MASK_SI_URD      { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
428 
#define MASK_SIY_URD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
429 225 jeremybenn 
#define MASK_SIY_IRD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
430 
#define MASK_SIL_RDI     { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
431 
#define MASK_SIL_RDU     { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
432 24 jeremybenn 
#define MASK_SSE_RDRD    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
433 
#define MASK_SS_L0RDRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
434 
#define MASK_SS_L2RDRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
435 
#define MASK_SS_LIRDRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
436 
#define MASK_SS_LLRDRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
437 
#define MASK_SS_RRRDRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
438 
#define MASK_SS_RRRDRD2  { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
439 
#define MASK_SS_RRRDRD3  { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
440 225 jeremybenn 
#define MASK_SSF_RRDRD   { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
441 24 jeremybenn 
#define MASK_S_00        { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
442 
#define MASK_S_RD        { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
443 
 
444 225 jeremybenn 
 
445 24 jeremybenn 
/* The opcode formats table (blueprints for .insn pseudo mnemonic).  */
446 
 
447 
const struct s390_opcode s390_opformats[] =
448 
  {
449 
  { "e",        OP8(0x00LL),    MASK_E,         INSTR_E,        3, 0 },
450 
  { "ri",       OP8(0x00LL),    MASK_RI_RI,     INSTR_RI_RI,    3, 0 },
451 
  { "rie",      OP8(0x00LL),    MASK_RIE_RRP,   INSTR_RIE_RRP,  3, 0 },
452 
  { "ril",      OP8(0x00LL),    MASK_RIL_RP,    INSTR_RIL_RP,   3, 0 },
453 
  { "rilu",     OP8(0x00LL),    MASK_RIL_RU,    INSTR_RIL_RU,   3, 0 },
454 225 jeremybenn 
  { "ris",      OP8(0x00LL),    MASK_RIS_RURDI, INSTR_RIS_RURDI,3, 6 },
455 24 jeremybenn 
  { "rr",       OP8(0x00LL),    MASK_RR_RR,     INSTR_RR_RR,    3, 0 },
456 
  { "rre",      OP8(0x00LL),    MASK_RRE_RR,    INSTR_RRE_RR,   3, 0 },
457 
  { "rrf",      OP8(0x00LL),    MASK_RRF_RURR,  INSTR_RRF_RURR, 3, 0 },
458 225 jeremybenn 
  { "rrs",      OP8(0x00LL),    MASK_RRS_RRRDU, INSTR_RRS_RRRDU,3, 6 },
459 24 jeremybenn 
  { "rs",       OP8(0x00LL),    MASK_RS_RRRD,   INSTR_RS_RRRD,  3, 0 },
460 
  { "rse",      OP8(0x00LL),    MASK_RSE_RRRD,  INSTR_RSE_RRRD, 3, 0 },
461 
  { "rsi",      OP8(0x00LL),    MASK_RSI_RRP,   INSTR_RSI_RRP,  3, 0 },
462 
  { "rsy",      OP8(0x00LL),    MASK_RSY_RRRD,  INSTR_RSY_RRRD, 3, 3 },
463 
  { "rx",       OP8(0x00LL),    MASK_RX_RRRD,   INSTR_RX_RRRD,  3, 0 },
464 
  { "rxe",      OP8(0x00LL),    MASK_RXE_RRRD,  INSTR_RXE_RRRD, 3, 0 },
465 
  { "rxf",      OP8(0x00LL),    MASK_RXF_RRRDR, INSTR_RXF_RRRDR,3, 0 },
466 
  { "rxy",      OP8(0x00LL),    MASK_RXY_RRRD,  INSTR_RXY_RRRD, 3, 3 },
467 
  { "s",        OP8(0x00LL),    MASK_S_RD,      INSTR_S_RD,     3, 0 },
468 
  { "si",       OP8(0x00LL),    MASK_SI_URD,    INSTR_SI_URD,   3, 0 },
469 
  { "siy",      OP8(0x00LL),    MASK_SIY_URD,   INSTR_SIY_URD,  3, 3 },
470 225 jeremybenn 
  { "sil",      OP8(0x00LL),    MASK_SIL_RDI,   INSTR_SIL_RDI,  3, 6 },
471 24 jeremybenn 
  { "ss",       OP8(0x00LL),    MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3, 0 },
472 
  { "sse",      OP8(0x00LL),    MASK_SSE_RDRD,  INSTR_SSE_RDRD, 3, 0 },
473 
  { "ssf",      OP8(0x00LL),    MASK_SSF_RRDRD, INSTR_SSF_RRDRD,3, 0 },
474 
};
475 
 
476 
const int s390_num_opformats =
477 
  sizeof (s390_opformats) / sizeof (s390_opformats[0]);
478 
 
479 
#include "s390-opc.tab"

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.