OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [common/] [sim-endian.c] - Blame information for rev 280

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
/* The common simulator framework for GDB, the GNU Debugger.
2
 
3
   Copyright 2002, 2007, 2008 Free Software Foundation, Inc.
4
 
5
   Contributed by Andrew Cagney and Red Hat.
6
 
7
   This file is part of GDB.
8
 
9
   This program is free software; you can redistribute it and/or modify
10
   it under the terms of the GNU General Public License as published by
11
   the Free Software Foundation; either version 3 of the License, or
12
   (at your option) any later version.
13
 
14
   This program is distributed in the hope that it will be useful,
15
   but WITHOUT ANY WARRANTY; without even the implied warranty of
16
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17
   GNU General Public License for more details.
18
 
19
   You should have received a copy of the GNU General Public License
20
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
21
 
22
 
23
#ifndef _SIM_ENDIAN_C_
24
#define _SIM_ENDIAN_C_
25
 
26
#include "sim-basics.h"
27
#include "sim-assert.h"
28
#include "sim-io.h"
29
 
30
 
31
#if !defined(_SWAP_1)
32
#define _SWAP_1(SET,RAW) SET (RAW)
33
#endif
34
 
35
#if !defined(_SWAP_2) && (WITH_HOST_BYTE_ORDER == LITTLE_ENDIAN) && defined(htons)
36
#define _SWAP_2(SET,RAW) SET htons (RAW)
37
#endif
38
 
39
#ifndef _SWAP_2
40
#define _SWAP_2(SET,RAW) SET (((RAW) >> 8) | ((RAW) << 8))
41
#endif
42
 
43
#if !defined(_SWAP_4) && (WITH_HOST_BYTE_ORDER == LITTLE_ENDIAN) && defined(htonl)
44
#define _SWAP_4(SET,RAW) SET htonl (RAW)
45
#endif
46
 
47
#ifndef _SWAP_4
48
#define _SWAP_4(SET,RAW) SET (((RAW) << 24) | (((RAW) & 0xff00) << 8) | (((RAW) & 0xff0000) >> 8) | ((RAW) >> 24))
49
#endif
50
 
51
#ifndef _SWAP_8
52
#define _SWAP_8(SET,RAW) \
53
  union { unsigned_8 dword; unsigned_4 words[2]; } in, out; \
54
  in.dword = RAW; \
55
  _SWAP_4 (out.words[0] =, in.words[1]); \
56
  _SWAP_4 (out.words[1] =, in.words[0]); \
57
  SET out.dword;
58
#endif
59
 
60
#ifndef _SWAP_16
61
#define _SWAP_16(SET,RAW) \
62
  union { unsigned_16 word; unsigned_4 words[4]; } in, out; \
63
  in.word = (RAW); \
64
  _SWAP_4 (out.words[0] =, in.words[3]); \
65
  _SWAP_4 (out.words[1] =, in.words[2]); \
66
  _SWAP_4 (out.words[2] =, in.words[1]); \
67
  _SWAP_4 (out.words[3] =, in.words[0]); \
68
  SET out.word;
69
#endif
70
 
71
 
72
#define N 1
73
#include "sim-n-endian.h"
74
#undef N
75
 
76
#define N 2
77
#include "sim-n-endian.h"
78
#undef N
79
 
80
#define N 4
81
#include "sim-n-endian.h"
82
#undef N
83
 
84
#define N 8
85
#include "sim-n-endian.h"
86
#undef N
87
 
88
#define N 16
89
#include "sim-n-endian.h"
90
#undef N
91
 
92
 
93
INLINE_SIM_ENDIAN\
94
(unsigned_8)
95
sim_endian_split_16 (unsigned_16 word, int w)
96
{
97
  if (CURRENT_HOST_BYTE_ORDER == LITTLE_ENDIAN)
98
    {
99
      return word.a[1 - w];
100
    }
101
  else
102
    {
103
      return word.a[w];
104
    }
105
}
106
 
107
 
108
INLINE_SIM_ENDIAN\
109
(unsigned_16)
110
sim_endian_join_16 (unsigned_8 h, unsigned_8 l)
111
 
112
{
113
  unsigned_16 word;
114
  if (CURRENT_HOST_BYTE_ORDER == LITTLE_ENDIAN)
115
    {
116
      word.a[0] = l;
117
      word.a[1] = h;
118
    }
119
  else
120
    {
121
      word.a[0] = h;
122
      word.a[1] = l;
123
    }
124
  return word;
125
}
126
 
127
 
128
 
129
#endif /* _SIM_ENDIAN_C_ */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.