OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [common/] [sim-hrw.c] - Blame information for rev 450

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
/* Generic memory read/write for hardware simulator models.
2
   Copyright (C) 1997, 2007, 2008 Free Software Foundation, Inc.
3
   Contributed by Cygnus Support.
4
 
5
This file is part of GDB, the GNU debugger.
6
 
7
This program is free software; you can redistribute it and/or modify
8
it under the terms of the GNU General Public License as published by
9
the Free Software Foundation; either version 3 of the License, or
10
(at your option) any later version.
11
 
12
This program is distributed in the hope that it will be useful,
13
but WITHOUT ANY WARRANTY; without even the implied warranty of
14
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
GNU General Public License for more details.
16
 
17
You should have received a copy of the GNU General Public License
18
along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
19
 
20
#include "sim-main.h"
21
#include "sim-assert.h"
22
 
23
/* Generic implementation of sim_read that works with simulators
24
   modeling real hardware */
25
 
26
int
27
sim_read (SIM_DESC sd, SIM_ADDR mem, unsigned char *buf, int length)
28
{
29
  SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
30
  return sim_core_read_buffer (sd, NULL, read_map,
31
                               buf, mem, length);
32
}
33
 
34
int
35
sim_write (SIM_DESC sd, SIM_ADDR mem, unsigned char *buf, int length)
36
{
37
  SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
38
  return sim_core_write_buffer (sd, NULL, write_map,
39
                                buf, mem, length);
40
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.