OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [cris/] [crisv10f.c] - Blame information for rev 471

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
/* CRIS v10 simulator support code
2
   Copyright (C) 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
3
   Contributed by Axis Communications.
4
 
5
This file is part of the GNU simulators.
6
 
7
This program is free software; you can redistribute it and/or modify
8
it under the terms of the GNU General Public License as published by
9
the Free Software Foundation; either version 3 of the License, or
10
(at your option) any later version.
11
 
12
This program is distributed in the hope that it will be useful,
13
but WITHOUT ANY WARRANTY; without even the implied warranty of
14
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
GNU General Public License for more details.
16
 
17
You should have received a copy of the GNU General Public License
18
along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
19
 
20
/* The infrastructure is based on that of i960.c.  */
21
 
22
#define WANT_CPU_CRISV10F
23
 
24
#define BASENUM 10
25
#include "cris-tmpl.c"
26
 
27
#if WITH_PROFILE_MODEL_P
28
 
29
/* Model function for u-multiply unit.  */
30
 
31
int
32
MY (XCONCAT3 (f_model_crisv,BASENUM,
33
              _u_multiply)) (SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
34
                             const IDESC *idesc ATTRIBUTE_UNUSED,
35
                             int unit_num ATTRIBUTE_UNUSED,
36
                             int referenced ATTRIBUTE_UNUSED)
37
{
38
  return 1;
39
}
40
 
41
#endif /* WITH_PROFILE_MODEL_P */
42
 
43
/* Do the interrupt sequence if possible, and return 1.  If interrupts
44
   are disabled or some other lockout is active, return 0 and do
45
   nothing.
46
 
47
   Beware, the v10 implementation is incomplete and doesn't properly
48
   lock out interrupts e.g. after special-register access and doesn't
49
   handle user-mode.  */
50
 
51
int
52
MY (deliver_interrupt) (SIM_CPU *current_cpu,
53
                        enum cris_interrupt_type type,
54
                        unsigned int vec)
55
{
56
  unsigned char entryaddr_le[4];
57
  int was_user;
58
  SIM_DESC sd = CPU_STATE (current_cpu);
59
  unsigned32 entryaddr;
60
 
61
  /* We haven't implemented other interrupt-types yet.  */
62
  if (type != CRIS_INT_INT)
63
    abort ();
64
 
65
  /* We're supposed to be called outside of prefixes and branch
66
     delay-slots etc, but why not check.  */
67
  if (GET_H_INSN_PREFIXED_P ())
68
    abort ();
69
 
70
  if (!GET_H_IBIT ())
71
    return 0;
72
 
73
  /* User mode isn't supported for interrupts.  (And we shouldn't see
74
     this as 1 anyway.  The user-mode bit isn't visible from user
75
     mode.  It doesn't make it into the U bit until the next
76
     interrupt/exception.)  */
77
  if (GET_H_UBIT ())
78
    abort ();
79
 
80
  SET_H_PBIT (1);
81
 
82
  if (sim_core_read_buffer (sd,
83
                            current_cpu,
84
                            read_map, entryaddr_le,
85
                            GET_H_SR (H_SR_PRE_V32_IBR) + vec * 4, 4) == 0)
86
    {
87
      /* Nothing to do actually; either abort or send a signal.  */
88
      sim_core_signal (sd, current_cpu, CIA_GET (current_cpu), 0, 4,
89
                       GET_H_SR (H_SR_PRE_V32_IBR) + vec * 4,
90
                       read_transfer, sim_core_unmapped_signal);
91
      return 0;
92
    }
93
 
94
  entryaddr = bfd_getl32 (entryaddr_le);
95
 
96
  SET_H_SR (H_SR_PRE_V32_IRP, GET_H_PC ());
97
  SET_H_PC (entryaddr);
98
 
99
  return 1;
100
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.