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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [frv/] [sim-main.h] - Blame information for rev 301

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1 24 jeremybenn
/* frv simulator support code
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   Copyright (C) 1998, 2000, 2001, 2007, 2008 Free Software Foundation, Inc.
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   Contributed by Red Hat.
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This file is part of the GNU simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
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/* Main header for the frv.  */
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#define USING_SIM_BASE_H /* FIXME: quick hack */
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struct _sim_cpu; /* FIXME: should be in sim-basics.h */
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typedef struct _sim_cpu SIM_CPU;
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/* Set the mask of unsupported traces.  */
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#define WITH_TRACE \
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  (~(TRACE_alu | TRACE_decode | TRACE_memory | TRACE_model | TRACE_fpu \
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     | TRACE_branch | TRACE_debug))
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/* sim-basics.h includes config.h but cgen-types.h must be included before
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   sim-basics.h and cgen-types.h needs config.h.  */
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#include "config.h"
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#include "symcat.h"
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#include "sim-basics.h"
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#include "cgen-types.h"
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#include "frv-desc.h"
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#include "frv-opc.h"
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#include "arch.h"
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/* These must be defined before sim-base.h.  */
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typedef USI sim_cia;
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#define CIA_GET(cpu)     CPU_PC_GET (cpu)
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#define CIA_SET(cpu,val) CPU_PC_SET ((cpu), (val))
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void frv_sim_engine_halt_hook (SIM_DESC, SIM_CPU *, sim_cia);
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#define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) \
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  frv_sim_engine_halt_hook ((SD), (LAST_CPU), (CIA))
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#define SIM_ENGINE_RESTART_HOOK(SD, LAST_CPU, CIA) 0
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#include "sim-base.h"
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#include "cgen-sim.h"
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#include "frv-sim.h"
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#include "cache.h"
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#include "registers.h"
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#include "profile.h"
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/* The _sim_cpu struct.  */
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struct _sim_cpu {
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  /* sim/common cpu base.  */
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  sim_cpu_base base;
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  /* Static parts of cgen.  */
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  CGEN_CPU cgen_cpu;
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  /* CPU specific parts go here.
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     Note that in files that don't need to access these pieces WANT_CPU_FOO
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     won't be defined and thus these parts won't appear.  This is ok in the
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     sense that things work.  It is a source of bugs though.
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     One has to of course be careful to not take the size of this
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     struct and no structure members accessed in non-cpu specific files can
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     go after here.  Oh for a better language.  */
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#if defined (WANT_CPU_FRVBF)
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  FRVBF_CPU_DATA cpu_data;
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  /* Control information for registers */
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  FRV_REGISTER_CONTROL register_control;
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#define CPU_REGISTER_CONTROL(cpu) (& (cpu)->register_control)
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  FRV_VLIW vliw;
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#define CPU_VLIW(cpu) (& (cpu)->vliw)
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  FRV_CACHE insn_cache;
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#define CPU_INSN_CACHE(cpu) (& (cpu)->insn_cache)
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  FRV_CACHE data_cache;
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#define CPU_DATA_CACHE(cpu) (& (cpu)->data_cache)
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  FRV_PROFILE_STATE profile_state;
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#define CPU_PROFILE_STATE(cpu) (& (cpu)->profile_state)
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  int debug_state;
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#define CPU_DEBUG_STATE(cpu) ((cpu)->debug_state)
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  SI load_address;
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#define CPU_LOAD_ADDRESS(cpu) ((cpu)->load_address)
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  SI load_length;
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#define CPU_LOAD_LENGTH(cpu) ((cpu)->load_length)
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  SI load_flag;
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#define CPU_LOAD_SIGNED(cpu) ((cpu)->load_flag)
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#define CPU_LOAD_LOCK(cpu) ((cpu)->load_flag)
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  SI store_flag;
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#define CPU_RSTR_INVALIDATE(cpu) ((cpu)->store_flag)
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  unsigned long elf_flags;
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#define CPU_ELF_FLAGS(cpu) ((cpu)->elf_flags)
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#endif /* defined (WANT_CPU_FRVBF) */
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};
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/* The sim_state struct.  */
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struct sim_state {
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  sim_cpu *cpu;
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#define STATE_CPU(sd, n) (/*&*/ (sd)->cpu)
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  CGEN_STATE cgen_state;
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  sim_state_base base;
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};
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/* Misc.  */
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/* Catch address exceptions.  */
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extern SIM_CORE_SIGNAL_FN frv_core_signal;
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#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
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frv_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
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                  (TRANSFER), (ERROR))
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/* Default memory size.  */
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#define FRV_DEFAULT_MEM_SIZE 0x800000 /* 8M */

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