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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [h8300/] [sim-main.h] - Blame information for rev 301

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1 24 jeremybenn
/* Main header for the Hitachi h8/300 architecture.  */
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#include "bfd.h"
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#ifndef SIM_MAIN_H
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#define SIM_MAIN_H
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#define DEBUG
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/* These define the size of main memory for the simulator.
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   Note the size of main memory for the H8/300H is only 256k.  Keeping it
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   small makes the simulator run much faster and consume less memory.
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   The linker knows about the limited size of the simulator's main memory
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   on the H8/300H (via the h8300h.sc linker script).  So if you change
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   H8300H_MSIZE, be sure to fix the linker script too.
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   Also note that there's a separate "eightbit" area aside from main
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   memory.  For simplicity, the simulator assumes any data memory reference
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   outside of main memory refers to the eightbit area (in theory, this
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   can only happen when simulating H8/300H programs).  We make no attempt
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   to catch overlapping addresses, wrapped addresses, etc etc.  */
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#define H8300_MSIZE (1 << 16)
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/* avolkov:
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   Next 2 macros are ugly for any workstation, but while they're work.
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   Memory size MUST be configurable.  */
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#define H8300H_MSIZE (1 << 24) 
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#define H8300S_MSIZE (1 << 24) 
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#define CSIZE 1024
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enum h8_regnum {
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  R0_REGNUM = 0,
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  R1_REGNUM = 1,
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  R2_REGNUM = 2,
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  R3_REGNUM = 3,
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  R4_REGNUM = 4,
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  R5_REGNUM = 5,
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  R6_REGNUM = 6,
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  R7_REGNUM = 7,
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  SP_REGNUM = R7_REGNUM,        /* Contains address of top of stack */
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  FP_REGNUM = R6_REGNUM,        /* Contains address of executing
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                                   stack frame */
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  CCR_REGNUM = 8,               /* Contains processor status */
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  PC_REGNUM  = 9,               /* Contains program counter */
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  CYCLE_REGNUM = 10,
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  EXR_REGNUM  = 11,
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  INST_REGNUM = 12,
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  TICK_REGNUM = 13,
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  MACH_REGNUM = 14,
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  MACL_REGNUM = 15,
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  SBR_REGNUM =  16,
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  VBR_REGNUM =  17,
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  ZERO_REGNUM = 18
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};
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enum h8_typecodes {
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  OP_NULL,
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  OP_REG,               /* Register direct.  */
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  OP_LOWREG,            /* Special reg syntax for "bra".  */
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  OP_DISP,              /* Register indirect w/displacement.  */
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  /* Note: h8300, h8300h, and h8300s permit only pre-decr and post-incr.  */
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  OP_PREDEC,            /* Register indirect w/pre-decrement.  */
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  OP_POSTDEC,           /* Register indirect w/post-decrement.  */
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  OP_PREINC,            /* Register indirect w/pre-increment.  */
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  OP_POSTINC,           /* Register indirect w/post-increment.  */
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  OP_PCREL,             /* PC Relative.  */
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  OP_MEM,               /* Absolute memory address.  */
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  OP_CCR,               /* Condition Code Register.  */
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  OP_IMM,               /* Immediate value.  */
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  /*OP_ABS*/            /* Un-used (duplicates op_mem?).  */
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  OP_EXR,               /* EXtended control Register.  */
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  OP_SBR,               /* Vector Base Register.  */
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  OP_VBR,               /* Short-address Base Register.  */
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  OP_MACH,              /* Multiply Accumulator - high.  */
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  OP_MACL,              /* Multiply Accumulator - low.   */
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  /* FIXME: memory indirect?  */
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  OP_INDEXB,            /* Byte index mode */
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  OP_INDEXW,            /* Word index mode */
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  OP_INDEXL             /* Long index mode */
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};
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#include "sim-basics.h"
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/* Define sim_cia.  */
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typedef unsigned32 sim_cia;
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#include "sim-base.h"
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/* Structure used to describe addressing */
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typedef struct
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{
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  int type;
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  int reg;
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  int literal;
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} ea_type;
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/* Struct for instruction decoder.  */
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typedef struct
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{
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  ea_type src;
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  ea_type dst;
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  ea_type op3;
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  int opcode;
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  int next_pc;
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  int oldpc;
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  int cycles;
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#ifdef DEBUG
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  struct h8_opcode *op;
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#endif
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} decoded_inst;
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struct _sim_cpu {
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  unsigned int regs[20];        /* 8 GR's plus ZERO, SBR, and VBR.  */
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  unsigned int pc;
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  int macS;                     /* MAC Saturating mode */
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  int macV;                     /* MAC Overflow */
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  int macN;                     /* MAC Negative */
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  int macZ;                     /* MAC Zero     */
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  int delayed_branch;
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  char **command_line;          /* Pointer to command line arguments.  */
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  unsigned char *memory;
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  unsigned char *eightbit;
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  int mask;
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  sim_cpu_base base;
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};
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/* The sim_state struct.  */
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struct sim_state {
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  struct _sim_cpu *cpu;
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  unsigned int sim_cache_size;
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  decoded_inst *sim_cache;
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  unsigned short *cache_idx;
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  unsigned long memory_size;
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  int cache_top;
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  int compiles;
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#ifdef ADEBUG
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  int stats[O_LAST];
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#endif
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  sim_state_base base;
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};
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/* The current state of the processor; registers, memory, etc.  */
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#define CIA_GET(CPU)            (cpu_get_pc (CPU))
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#define CIA_SET(CPU, VAL)       (cpu_set_pc ((CPU), (VAL)))
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#define STATE_CPU(SD, N)        ((SD)->cpu)     /* Single Processor.  */
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#define cpu_set_pc(CPU, VAL)    (((CPU)->pc)  = (VAL))
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#define cpu_get_pc(CPU)         (((CPU)->pc))
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/* Magic numbers used to distinguish an exit from a breakpoint.  */
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#define LIBC_EXIT_MAGIC1 0xdead 
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#define LIBC_EXIT_MAGIC2 0xbeef 
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/* Local version of macros for decoding exit status.
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   (included here rather than try to find target version of wait.h)
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*/
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#define SIM_WIFEXITED(V)        (((V) & 0xff) == 0)
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#define SIM_WIFSTOPPED(V)       (!SIM_WIFEXITED (V))
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#define SIM_WEXITSTATUS(V)      (((V) >> 8) & 0xff)
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#define SIM_WSTOPSIG(V)         ((V) & 0x7f)
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#endif /* SIM_MAIN_H */

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