OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [iq2000/] [iq2000-sim.h] - Blame information for rev 321

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
/* collection of junk waiting time to sort out
2
   Copyright (C) 1998, 1999, 2007, 2008 Free Software Foundation, Inc.
3
   Contributed by Cygnus Solutions.
4
 
5
This file is part of the GNU Simulators.
6
 
7
This program is free software; you can redistribute it and/or modify
8
it under the terms of the GNU General Public License as published by
9
the Free Software Foundation; either version 3 of the License, or
10
(at your option) any later version.
11
 
12
This program is distributed in the hope that it will be useful,
13
but WITHOUT ANY WARRANTY; without even the implied warranty of
14
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
GNU General Public License for more details.
16
 
17
You should have received a copy of the GNU General Public License
18
along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
19
 
20
#ifndef IQ2000_SIM_H
21
#define IQ2000_SIM_H
22
 
23
#define GETTWI GETTSI
24
#define SETTWI SETTSI
25
 
26
 
27
/* Hardware/device support.
28
/* sim_core_attach device argument.  */
29
extern device iq2000_devices;
30
 
31
/* FIXME: Temporary, until device support ready.  */
32
struct _device { int foo; };
33
 
34
#endif /* IQ2000_SIM_H */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.