OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [m32c/] [main.c] - Blame information for rev 247

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
/* main.c --- main function for stand-alone M32C simulator.
2
 
3
Copyright (C) 2005, 2007, 2008 Free Software Foundation, Inc.
4
Contributed by Red Hat, Inc.
5
 
6
This file is part of the GNU simulators.
7
 
8
This program is free software; you can redistribute it and/or modify
9
it under the terms of the GNU General Public License as published by
10
the Free Software Foundation; either version 3 of the License, or
11
(at your option) any later version.
12
 
13
This program is distributed in the hope that it will be useful,
14
but WITHOUT ANY WARRANTY; without even the implied warranty of
15
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
GNU General Public License for more details.
17
 
18
You should have received a copy of the GNU General Public License
19
along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
20
 
21
 
22
#include <stdio.h>
23
#include <string.h>
24
#include <stdlib.h>
25
#include <unistd.h>
26
#include <assert.h>
27
#include <setjmp.h>
28
#include <signal.h>
29
 
30
#include "bfd.h"
31
 
32
#include "cpu.h"
33
#include "mem.h"
34
#include "misc.h"
35
#include "load.h"
36
#include "trace.h"
37
 
38
static int disassemble = 0;
39
static unsigned int cycles = 0;
40
 
41
static void
42
done (int exit_code)
43
{
44
  if (verbose)
45
    {
46
      stack_heap_stats ();
47
      mem_usage_stats ();
48
      printf ("insns: %14s\n", comma (cycles));
49
    }
50
  exit (exit_code);
51
}
52
 
53
int
54
main (int argc, char **argv)
55
{
56
  int o;
57
  int save_trace;
58
  bfd *prog;
59
 
60
  while ((o = getopt (argc, argv, "tvdm:")) != -1)
61
    switch (o)
62
      {
63
      case 't':
64
        trace++;
65
        break;
66
      case 'v':
67
        verbose++;
68
        break;
69
      case 'd':
70
        disassemble++;
71
        break;
72
      case 'm':
73
        if (strcmp (optarg, "r8c") == 0 || strcmp (optarg, "m16c") == 0)
74
          default_machine = bfd_mach_m16c;
75
        else if (strcmp (optarg, "m32cm") == 0
76
                 || strcmp (optarg, "m32c") == 0)
77
          default_machine = bfd_mach_m32c;
78
        else
79
          {
80
            fprintf (stderr, "Invalid machine: %s\n", optarg);
81
            exit (1);
82
          }
83
        break;
84
      case '?':
85
        fprintf (stderr,
86
                 "usage: run [-v] [-t] [-d] [-m r8c|m16c|m32cm|m32c]"
87
                 " program\n");
88
        exit (1);
89
      }
90
 
91
  prog = bfd_openr (argv[optind], 0);
92
  if (!prog)
93
    {
94
      fprintf (stderr, "Can't read %s\n", argv[optind]);
95
      exit (1);
96
    }
97
 
98
  if (!bfd_check_format (prog, bfd_object))
99
    {
100
      fprintf (stderr, "%s not a m32c program\n", argv[optind]);
101
      exit (1);
102
    }
103
 
104
  save_trace = trace;
105
  trace = 0;
106
  m32c_load (prog);
107
  trace = save_trace;
108
 
109
  if (disassemble)
110
    sim_disasm_init (prog);
111
 
112
  while (1)
113
    {
114
      int rc;
115
 
116
      if (trace)
117
        printf ("\n");
118
 
119
      if (disassemble)
120
        sim_disasm_one ();
121
 
122
      enable_counting = verbose;
123
      cycles++;
124
      rc = decode_opcode ();
125
      enable_counting = 0;
126
 
127
      if (M32C_HIT_BREAK (rc))
128
        done (1);
129
      else if (M32C_EXITED (rc))
130
        done (M32C_EXIT_STATUS (rc));
131
      else
132
        assert (M32C_STEPPED (rc));
133
 
134
      trace_register_changes ();
135
    }
136
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.