OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [m32r/] [arch.h] - Blame information for rev 438

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
/* Simulator header for m32r.
2
 
3
THIS FILE IS MACHINE GENERATED WITH CGEN.
4
 
5
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
6
 
7
This file is part of the GNU simulators.
8
 
9
This program is free software; you can redistribute it and/or modify
10
it under the terms of the GNU General Public License as published by
11
the Free Software Foundation; either version 3 of the License, or
12
(at your option) any later version.
13
 
14
This program is distributed in the hope that it will be useful,
15
but WITHOUT ANY WARRANTY; without even the implied warranty of
16
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17
GNU General Public License for more details.
18
 
19
You should have received a copy of the GNU General Public License
20
along with this program.  If not, see <http://www.gnu.org/licenses/>.
21
 
22
*/
23
 
24
#ifndef M32R_ARCH_H
25
#define M32R_ARCH_H
26
 
27
#define TARGET_BIG_ENDIAN 1
28
 
29
/* Enum declaration for model types.  */
30
typedef enum model_type {
31
  MODEL_M32R_D, MODEL_TEST, MODEL_M32RX, MODEL_M32R2
32
 , MODEL_MAX
33
} MODEL_TYPE;
34
 
35
#define MAX_MODELS ((int) MODEL_MAX)
36
 
37
/* Enum declaration for unit types.  */
38
typedef enum unit_type {
39
  UNIT_NONE, UNIT_M32R_D_U_STORE, UNIT_M32R_D_U_LOAD, UNIT_M32R_D_U_CTI
40
 , UNIT_M32R_D_U_MAC, UNIT_M32R_D_U_CMP, UNIT_M32R_D_U_EXEC, UNIT_TEST_U_EXEC
41
 , UNIT_M32RX_U_STORE, UNIT_M32RX_U_LOAD, UNIT_M32RX_U_CTI, UNIT_M32RX_U_MAC
42
 , UNIT_M32RX_U_CMP, UNIT_M32RX_U_EXEC, UNIT_M32R2_U_STORE, UNIT_M32R2_U_LOAD
43
 , UNIT_M32R2_U_CTI, UNIT_M32R2_U_MAC, UNIT_M32R2_U_CMP, UNIT_M32R2_U_EXEC
44
 , UNIT_MAX
45
} UNIT_TYPE;
46
 
47
#define MAX_UNITS (2)
48
 
49
#endif /* M32R_ARCH_H */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.