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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [m32r/] [model.c] - Blame information for rev 300

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1 24 jeremybenn 
/* Simulator model support for m32rbf.
2 
 
3 
THIS FILE IS MACHINE GENERATED WITH CGEN.
4 
 
5 
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
6 
 
7 
This file is part of the GNU simulators.
8 
 
9 
This program is free software; you can redistribute it and/or modify
10 
it under the terms of the GNU General Public License as published by
11 
the Free Software Foundation; either version 3 of the License, or
12 
(at your option) any later version.
13 
 
14 
This program is distributed in the hope that it will be useful,
15 
but WITHOUT ANY WARRANTY; without even the implied warranty of
16 
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 
GNU General Public License for more details.
18 
 
19 
You should have received a copy of the GNU General Public License
20 
along with this program.  If not, see <http://www.gnu.org/licenses/>.
21 
 
22 
*/
23 
 
24 
#define WANT_CPU m32rbf
25 
#define WANT_CPU_M32RBF
26 
 
27 
#include "sim-main.h"
28 
 
29 
/* The profiling data is recorded here, but is accessed via the profiling
30 
   mechanism.  After all, this is information for profiling.  */
31 
 
32 
#if WITH_PROFILE_MODEL_P
33 
 
34 
/* Model handlers for each insn.  */
35 
 
36 
static int
37 
model_m32r_d_add (SIM_CPU *current_cpu, void *sem_arg)
38 
{
39 
#define FLD(f) abuf->fields.sfmt_add.f
40 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
41 
  const IDESC * UNUSED idesc = abuf->idesc;
42 
  int cycles = 0;
43 
  {
44 
    int referenced = 0;
45 
    int UNUSED insn_referenced = abuf->written;
46 
    INT in_sr = -1;
47 
    INT in_dr = -1;
48 
    INT out_dr = -1;
49 
    in_sr = FLD (in_sr);
50 
    in_dr = FLD (in_dr);
51 
    out_dr = FLD (out_dr);
52 
    referenced |= 1 << 0;
53 
    referenced |= 1 << 1;
54 
    referenced |= 1 << 2;
55 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
56 
  }
57 
  return cycles;
58 
#undef FLD
59 
}
60 
 
61 
static int
62 
model_m32r_d_add3 (SIM_CPU *current_cpu, void *sem_arg)
63 
{
64 
#define FLD(f) abuf->fields.sfmt_add3.f
65 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
66 
  const IDESC * UNUSED idesc = abuf->idesc;
67 
  int cycles = 0;
68 
  {
69 
    int referenced = 0;
70 
    int UNUSED insn_referenced = abuf->written;
71 
    INT in_sr = -1;
72 
    INT in_dr = -1;
73 
    INT out_dr = -1;
74 
    in_sr = FLD (in_sr);
75 
    out_dr = FLD (out_dr);
76 
    referenced |= 1 << 0;
77 
    referenced |= 1 << 2;
78 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
79 
  }
80 
  return cycles;
81 
#undef FLD
82 
}
83 
 
84 
static int
85 
model_m32r_d_and (SIM_CPU *current_cpu, void *sem_arg)
86 
{
87 
#define FLD(f) abuf->fields.sfmt_add.f
88 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
89 
  const IDESC * UNUSED idesc = abuf->idesc;
90 
  int cycles = 0;
91 
  {
92 
    int referenced = 0;
93 
    int UNUSED insn_referenced = abuf->written;
94 
    INT in_sr = -1;
95 
    INT in_dr = -1;
96 
    INT out_dr = -1;
97 
    in_sr = FLD (in_sr);
98 
    in_dr = FLD (in_dr);
99 
    out_dr = FLD (out_dr);
100 
    referenced |= 1 << 0;
101 
    referenced |= 1 << 1;
102 
    referenced |= 1 << 2;
103 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
104 
  }
105 
  return cycles;
106 
#undef FLD
107 
}
108 
 
109 
static int
110 
model_m32r_d_and3 (SIM_CPU *current_cpu, void *sem_arg)
111 
{
112 
#define FLD(f) abuf->fields.sfmt_and3.f
113 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
114 
  const IDESC * UNUSED idesc = abuf->idesc;
115 
  int cycles = 0;
116 
  {
117 
    int referenced = 0;
118 
    int UNUSED insn_referenced = abuf->written;
119 
    INT in_sr = -1;
120 
    INT in_dr = -1;
121 
    INT out_dr = -1;
122 
    in_sr = FLD (in_sr);
123 
    out_dr = FLD (out_dr);
124 
    referenced |= 1 << 0;
125 
    referenced |= 1 << 2;
126 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
127 
  }
128 
  return cycles;
129 
#undef FLD
130 
}
131 
 
132 
static int
133 
model_m32r_d_or (SIM_CPU *current_cpu, void *sem_arg)
134 
{
135 
#define FLD(f) abuf->fields.sfmt_add.f
136 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
137 
  const IDESC * UNUSED idesc = abuf->idesc;
138 
  int cycles = 0;
139 
  {
140 
    int referenced = 0;
141 
    int UNUSED insn_referenced = abuf->written;
142 
    INT in_sr = -1;
143 
    INT in_dr = -1;
144 
    INT out_dr = -1;
145 
    in_sr = FLD (in_sr);
146 
    in_dr = FLD (in_dr);
147 
    out_dr = FLD (out_dr);
148 
    referenced |= 1 << 0;
149 
    referenced |= 1 << 1;
150 
    referenced |= 1 << 2;
151 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
152 
  }
153 
  return cycles;
154 
#undef FLD
155 
}
156 
 
157 
static int
158 
model_m32r_d_or3 (SIM_CPU *current_cpu, void *sem_arg)
159 
{
160 
#define FLD(f) abuf->fields.sfmt_and3.f
161 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
162 
  const IDESC * UNUSED idesc = abuf->idesc;
163 
  int cycles = 0;
164 
  {
165 
    int referenced = 0;
166 
    int UNUSED insn_referenced = abuf->written;
167 
    INT in_sr = -1;
168 
    INT in_dr = -1;
169 
    INT out_dr = -1;
170 
    in_sr = FLD (in_sr);
171 
    out_dr = FLD (out_dr);
172 
    referenced |= 1 << 0;
173 
    referenced |= 1 << 2;
174 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
175 
  }
176 
  return cycles;
177 
#undef FLD
178 
}
179 
 
180 
static int
181 
model_m32r_d_xor (SIM_CPU *current_cpu, void *sem_arg)
182 
{
183 
#define FLD(f) abuf->fields.sfmt_add.f
184 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
185 
  const IDESC * UNUSED idesc = abuf->idesc;
186 
  int cycles = 0;
187 
  {
188 
    int referenced = 0;
189 
    int UNUSED insn_referenced = abuf->written;
190 
    INT in_sr = -1;
191 
    INT in_dr = -1;
192 
    INT out_dr = -1;
193 
    in_sr = FLD (in_sr);
194 
    in_dr = FLD (in_dr);
195 
    out_dr = FLD (out_dr);
196 
    referenced |= 1 << 0;
197 
    referenced |= 1 << 1;
198 
    referenced |= 1 << 2;
199 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
200 
  }
201 
  return cycles;
202 
#undef FLD
203 
}
204 
 
205 
static int
206 
model_m32r_d_xor3 (SIM_CPU *current_cpu, void *sem_arg)
207 
{
208 
#define FLD(f) abuf->fields.sfmt_and3.f
209 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
210 
  const IDESC * UNUSED idesc = abuf->idesc;
211 
  int cycles = 0;
212 
  {
213 
    int referenced = 0;
214 
    int UNUSED insn_referenced = abuf->written;
215 
    INT in_sr = -1;
216 
    INT in_dr = -1;
217 
    INT out_dr = -1;
218 
    in_sr = FLD (in_sr);
219 
    out_dr = FLD (out_dr);
220 
    referenced |= 1 << 0;
221 
    referenced |= 1 << 2;
222 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
223 
  }
224 
  return cycles;
225 
#undef FLD
226 
}
227 
 
228 
static int
229 
model_m32r_d_addi (SIM_CPU *current_cpu, void *sem_arg)
230 
{
231 
#define FLD(f) abuf->fields.sfmt_addi.f
232 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
233 
  const IDESC * UNUSED idesc = abuf->idesc;
234 
  int cycles = 0;
235 
  {
236 
    int referenced = 0;
237 
    int UNUSED insn_referenced = abuf->written;
238 
    INT in_sr = -1;
239 
    INT in_dr = -1;
240 
    INT out_dr = -1;
241 
    in_dr = FLD (in_dr);
242 
    out_dr = FLD (out_dr);
243 
    referenced |= 1 << 1;
244 
    referenced |= 1 << 2;
245 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
246 
  }
247 
  return cycles;
248 
#undef FLD
249 
}
250 
 
251 
static int
252 
model_m32r_d_addv (SIM_CPU *current_cpu, void *sem_arg)
253 
{
254 
#define FLD(f) abuf->fields.sfmt_add.f
255 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
256 
  const IDESC * UNUSED idesc = abuf->idesc;
257 
  int cycles = 0;
258 
  {
259 
    int referenced = 0;
260 
    int UNUSED insn_referenced = abuf->written;
261 
    INT in_sr = -1;
262 
    INT in_dr = -1;
263 
    INT out_dr = -1;
264 
    in_sr = FLD (in_sr);
265 
    in_dr = FLD (in_dr);
266 
    out_dr = FLD (out_dr);
267 
    referenced |= 1 << 0;
268 
    referenced |= 1 << 1;
269 
    referenced |= 1 << 2;
270 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
271 
  }
272 
  return cycles;
273 
#undef FLD
274 
}
275 
 
276 
static int
277 
model_m32r_d_addv3 (SIM_CPU *current_cpu, void *sem_arg)
278 
{
279 
#define FLD(f) abuf->fields.sfmt_add3.f
280 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
281 
  const IDESC * UNUSED idesc = abuf->idesc;
282 
  int cycles = 0;
283 
  {
284 
    int referenced = 0;
285 
    int UNUSED insn_referenced = abuf->written;
286 
    INT in_sr = -1;
287 
    INT in_dr = -1;
288 
    INT out_dr = -1;
289 
    in_sr = FLD (in_sr);
290 
    out_dr = FLD (out_dr);
291 
    referenced |= 1 << 0;
292 
    referenced |= 1 << 2;
293 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
294 
  }
295 
  return cycles;
296 
#undef FLD
297 
}
298 
 
299 
static int
300 
model_m32r_d_addx (SIM_CPU *current_cpu, void *sem_arg)
301 
{
302 
#define FLD(f) abuf->fields.sfmt_add.f
303 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
304 
  const IDESC * UNUSED idesc = abuf->idesc;
305 
  int cycles = 0;
306 
  {
307 
    int referenced = 0;
308 
    int UNUSED insn_referenced = abuf->written;
309 
    INT in_sr = -1;
310 
    INT in_dr = -1;
311 
    INT out_dr = -1;
312 
    in_sr = FLD (in_sr);
313 
    in_dr = FLD (in_dr);
314 
    out_dr = FLD (out_dr);
315 
    referenced |= 1 << 0;
316 
    referenced |= 1 << 1;
317 
    referenced |= 1 << 2;
318 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
319 
  }
320 
  return cycles;
321 
#undef FLD
322 
}
323 
 
324 
static int
325 
model_m32r_d_bc8 (SIM_CPU *current_cpu, void *sem_arg)
326 
{
327 
#define FLD(f) abuf->fields.sfmt_bl8.f
328 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
329 
  const IDESC * UNUSED idesc = abuf->idesc;
330 
  int cycles = 0;
331 
  {
332 
    int referenced = 0;
333 
    int UNUSED insn_referenced = abuf->written;
334 
    INT in_sr = -1;
335 
    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
336 
    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
337 
  }
338 
  return cycles;
339 
#undef FLD
340 
}
341 
 
342 
static int
343 
model_m32r_d_bc24 (SIM_CPU *current_cpu, void *sem_arg)
344 
{
345 
#define FLD(f) abuf->fields.sfmt_bl24.f
346 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
347 
  const IDESC * UNUSED idesc = abuf->idesc;
348 
  int cycles = 0;
349 
  {
350 
    int referenced = 0;
351 
    int UNUSED insn_referenced = abuf->written;
352 
    INT in_sr = -1;
353 
    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
354 
    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
355 
  }
356 
  return cycles;
357 
#undef FLD
358 
}
359 
 
360 
static int
361 
model_m32r_d_beq (SIM_CPU *current_cpu, void *sem_arg)
362 
{
363 
#define FLD(f) abuf->fields.sfmt_beq.f
364 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
365 
  const IDESC * UNUSED idesc = abuf->idesc;
366 
  int cycles = 0;
367 
  {
368 
    int referenced = 0;
369 
    int UNUSED insn_referenced = abuf->written;
370 
    INT in_sr = -1;
371 
    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
372 
    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
373 
  }
374 
  {
375 
    int referenced = 0;
376 
    int UNUSED insn_referenced = abuf->written;
377 
    INT in_src1 = -1;
378 
    INT in_src2 = -1;
379 
    in_src1 = FLD (in_src1);
380 
    in_src2 = FLD (in_src2);
381 
    referenced |= 1 << 0;
382 
    referenced |= 1 << 1;
383 
    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
384 
  }
385 
  return cycles;
386 
#undef FLD
387 
}
388 
 
389 
static int
390 
model_m32r_d_beqz (SIM_CPU *current_cpu, void *sem_arg)
391 
{
392 
#define FLD(f) abuf->fields.sfmt_beq.f
393 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
394 
  const IDESC * UNUSED idesc = abuf->idesc;
395 
  int cycles = 0;
396 
  {
397 
    int referenced = 0;
398 
    int UNUSED insn_referenced = abuf->written;
399 
    INT in_sr = -1;
400 
    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
401 
    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
402 
  }
403 
  {
404 
    int referenced = 0;
405 
    int UNUSED insn_referenced = abuf->written;
406 
    INT in_src1 = -1;
407 
    INT in_src2 = -1;
408 
    in_src2 = FLD (in_src2);
409 
    referenced |= 1 << 1;
410 
    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
411 
  }
412 
  return cycles;
413 
#undef FLD
414 
}
415 
 
416 
static int
417 
model_m32r_d_bgez (SIM_CPU *current_cpu, void *sem_arg)
418 
{
419 
#define FLD(f) abuf->fields.sfmt_beq.f
420 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
421 
  const IDESC * UNUSED idesc = abuf->idesc;
422 
  int cycles = 0;
423 
  {
424 
    int referenced = 0;
425 
    int UNUSED insn_referenced = abuf->written;
426 
    INT in_sr = -1;
427 
    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
428 
    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
429 
  }
430 
  {
431 
    int referenced = 0;
432 
    int UNUSED insn_referenced = abuf->written;
433 
    INT in_src1 = -1;
434 
    INT in_src2 = -1;
435 
    in_src2 = FLD (in_src2);
436 
    referenced |= 1 << 1;
437 
    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
438 
  }
439 
  return cycles;
440 
#undef FLD
441 
}
442 
 
443 
static int
444 
model_m32r_d_bgtz (SIM_CPU *current_cpu, void *sem_arg)
445 
{
446 
#define FLD(f) abuf->fields.sfmt_beq.f
447 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
448 
  const IDESC * UNUSED idesc = abuf->idesc;
449 
  int cycles = 0;
450 
  {
451 
    int referenced = 0;
452 
    int UNUSED insn_referenced = abuf->written;
453 
    INT in_sr = -1;
454 
    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
455 
    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
456 
  }
457 
  {
458 
    int referenced = 0;
459 
    int UNUSED insn_referenced = abuf->written;
460 
    INT in_src1 = -1;
461 
    INT in_src2 = -1;
462 
    in_src2 = FLD (in_src2);
463 
    referenced |= 1 << 1;
464 
    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
465 
  }
466 
  return cycles;
467 
#undef FLD
468 
}
469 
 
470 
static int
471 
model_m32r_d_blez (SIM_CPU *current_cpu, void *sem_arg)
472 
{
473 
#define FLD(f) abuf->fields.sfmt_beq.f
474 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
475 
  const IDESC * UNUSED idesc = abuf->idesc;
476 
  int cycles = 0;
477 
  {
478 
    int referenced = 0;
479 
    int UNUSED insn_referenced = abuf->written;
480 
    INT in_sr = -1;
481 
    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
482 
    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
483 
  }
484 
  {
485 
    int referenced = 0;
486 
    int UNUSED insn_referenced = abuf->written;
487 
    INT in_src1 = -1;
488 
    INT in_src2 = -1;
489 
    in_src2 = FLD (in_src2);
490 
    referenced |= 1 << 1;
491 
    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
492 
  }
493 
  return cycles;
494 
#undef FLD
495 
}
496 
 
497 
static int
498 
model_m32r_d_bltz (SIM_CPU *current_cpu, void *sem_arg)
499 
{
500 
#define FLD(f) abuf->fields.sfmt_beq.f
501 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
502 
  const IDESC * UNUSED idesc = abuf->idesc;
503 
  int cycles = 0;
504 
  {
505 
    int referenced = 0;
506 
    int UNUSED insn_referenced = abuf->written;
507 
    INT in_sr = -1;
508 
    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
509 
    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
510 
  }
511 
  {
512 
    int referenced = 0;
513 
    int UNUSED insn_referenced = abuf->written;
514 
    INT in_src1 = -1;
515 
    INT in_src2 = -1;
516 
    in_src2 = FLD (in_src2);
517 
    referenced |= 1 << 1;
518 
    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
519 
  }
520 
  return cycles;
521 
#undef FLD
522 
}
523 
 
524 
static int
525 
model_m32r_d_bnez (SIM_CPU *current_cpu, void *sem_arg)
526 
{
527 
#define FLD(f) abuf->fields.sfmt_beq.f
528 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
529 
  const IDESC * UNUSED idesc = abuf->idesc;
530 
  int cycles = 0;
531 
  {
532 
    int referenced = 0;
533 
    int UNUSED insn_referenced = abuf->written;
534 
    INT in_sr = -1;
535 
    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
536 
    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
537 
  }
538 
  {
539 
    int referenced = 0;
540 
    int UNUSED insn_referenced = abuf->written;
541 
    INT in_src1 = -1;
542 
    INT in_src2 = -1;
543 
    in_src2 = FLD (in_src2);
544 
    referenced |= 1 << 1;
545 
    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
546 
  }
547 
  return cycles;
548 
#undef FLD
549 
}
550 
 
551 
static int
552 
model_m32r_d_bl8 (SIM_CPU *current_cpu, void *sem_arg)
553 
{
554 
#define FLD(f) abuf->fields.sfmt_bl8.f
555 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
556 
  const IDESC * UNUSED idesc = abuf->idesc;
557 
  int cycles = 0;
558 
  {
559 
    int referenced = 0;
560 
    int UNUSED insn_referenced = abuf->written;
561 
    INT in_sr = -1;
562 
    referenced |= 1 << 1;
563 
    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
564 
  }
565 
  return cycles;
566 
#undef FLD
567 
}
568 
 
569 
static int
570 
model_m32r_d_bl24 (SIM_CPU *current_cpu, void *sem_arg)
571 
{
572 
#define FLD(f) abuf->fields.sfmt_bl24.f
573 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
574 
  const IDESC * UNUSED idesc = abuf->idesc;
575 
  int cycles = 0;
576 
  {
577 
    int referenced = 0;
578 
    int UNUSED insn_referenced = abuf->written;
579 
    INT in_sr = -1;
580 
    referenced |= 1 << 1;
581 
    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
582 
  }
583 
  return cycles;
584 
#undef FLD
585 
}
586 
 
587 
static int
588 
model_m32r_d_bnc8 (SIM_CPU *current_cpu, void *sem_arg)
589 
{
590 
#define FLD(f) abuf->fields.sfmt_bl8.f
591 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
592 
  const IDESC * UNUSED idesc = abuf->idesc;
593 
  int cycles = 0;
594 
  {
595 
    int referenced = 0;
596 
    int UNUSED insn_referenced = abuf->written;
597 
    INT in_sr = -1;
598 
    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
599 
    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
600 
  }
601 
  return cycles;
602 
#undef FLD
603 
}
604 
 
605 
static int
606 
model_m32r_d_bnc24 (SIM_CPU *current_cpu, void *sem_arg)
607 
{
608 
#define FLD(f) abuf->fields.sfmt_bl24.f
609 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
610 
  const IDESC * UNUSED idesc = abuf->idesc;
611 
  int cycles = 0;
612 
  {
613 
    int referenced = 0;
614 
    int UNUSED insn_referenced = abuf->written;
615 
    INT in_sr = -1;
616 
    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
617 
    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
618 
  }
619 
  return cycles;
620 
#undef FLD
621 
}
622 
 
623 
static int
624 
model_m32r_d_bne (SIM_CPU *current_cpu, void *sem_arg)
625 
{
626 
#define FLD(f) abuf->fields.sfmt_beq.f
627 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
628 
  const IDESC * UNUSED idesc = abuf->idesc;
629 
  int cycles = 0;
630 
  {
631 
    int referenced = 0;
632 
    int UNUSED insn_referenced = abuf->written;
633 
    INT in_sr = -1;
634 
    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
635 
    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
636 
  }
637 
  {
638 
    int referenced = 0;
639 
    int UNUSED insn_referenced = abuf->written;
640 
    INT in_src1 = -1;
641 
    INT in_src2 = -1;
642 
    in_src1 = FLD (in_src1);
643 
    in_src2 = FLD (in_src2);
644 
    referenced |= 1 << 0;
645 
    referenced |= 1 << 1;
646 
    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
647 
  }
648 
  return cycles;
649 
#undef FLD
650 
}
651 
 
652 
static int
653 
model_m32r_d_bra8 (SIM_CPU *current_cpu, void *sem_arg)
654 
{
655 
#define FLD(f) abuf->fields.sfmt_bl8.f
656 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
657 
  const IDESC * UNUSED idesc = abuf->idesc;
658 
  int cycles = 0;
659 
  {
660 
    int referenced = 0;
661 
    int UNUSED insn_referenced = abuf->written;
662 
    INT in_sr = -1;
663 
    referenced |= 1 << 1;
664 
    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
665 
  }
666 
  return cycles;
667 
#undef FLD
668 
}
669 
 
670 
static int
671 
model_m32r_d_bra24 (SIM_CPU *current_cpu, void *sem_arg)
672 
{
673 
#define FLD(f) abuf->fields.sfmt_bl24.f
674 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
675 
  const IDESC * UNUSED idesc = abuf->idesc;
676 
  int cycles = 0;
677 
  {
678 
    int referenced = 0;
679 
    int UNUSED insn_referenced = abuf->written;
680 
    INT in_sr = -1;
681 
    referenced |= 1 << 1;
682 
    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
683 
  }
684 
  return cycles;
685 
#undef FLD
686 
}
687 
 
688 
static int
689 
model_m32r_d_cmp (SIM_CPU *current_cpu, void *sem_arg)
690 
{
691 
#define FLD(f) abuf->fields.sfmt_st_plus.f
692 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
693 
  const IDESC * UNUSED idesc = abuf->idesc;
694 
  int cycles = 0;
695 
  {
696 
    int referenced = 0;
697 
    int UNUSED insn_referenced = abuf->written;
698 
    INT in_src1 = -1;
699 
    INT in_src2 = -1;
700 
    in_src1 = FLD (in_src1);
701 
    in_src2 = FLD (in_src2);
702 
    referenced |= 1 << 0;
703 
    referenced |= 1 << 1;
704 
    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
705 
  }
706 
  return cycles;
707 
#undef FLD
708 
}
709 
 
710 
static int
711 
model_m32r_d_cmpi (SIM_CPU *current_cpu, void *sem_arg)
712 
{
713 
#define FLD(f) abuf->fields.sfmt_st_d.f
714 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
715 
  const IDESC * UNUSED idesc = abuf->idesc;
716 
  int cycles = 0;
717 
  {
718 
    int referenced = 0;
719 
    int UNUSED insn_referenced = abuf->written;
720 
    INT in_src1 = -1;
721 
    INT in_src2 = -1;
722 
    in_src2 = FLD (in_src2);
723 
    referenced |= 1 << 1;
724 
    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
725 
  }
726 
  return cycles;
727 
#undef FLD
728 
}
729 
 
730 
static int
731 
model_m32r_d_cmpu (SIM_CPU *current_cpu, void *sem_arg)
732 
{
733 
#define FLD(f) abuf->fields.sfmt_st_plus.f
734 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
735 
  const IDESC * UNUSED idesc = abuf->idesc;
736 
  int cycles = 0;
737 
  {
738 
    int referenced = 0;
739 
    int UNUSED insn_referenced = abuf->written;
740 
    INT in_src1 = -1;
741 
    INT in_src2 = -1;
742 
    in_src1 = FLD (in_src1);
743 
    in_src2 = FLD (in_src2);
744 
    referenced |= 1 << 0;
745 
    referenced |= 1 << 1;
746 
    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
747 
  }
748 
  return cycles;
749 
#undef FLD
750 
}
751 
 
752 
static int
753 
model_m32r_d_cmpui (SIM_CPU *current_cpu, void *sem_arg)
754 
{
755 
#define FLD(f) abuf->fields.sfmt_st_d.f
756 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
757 
  const IDESC * UNUSED idesc = abuf->idesc;
758 
  int cycles = 0;
759 
  {
760 
    int referenced = 0;
761 
    int UNUSED insn_referenced = abuf->written;
762 
    INT in_src1 = -1;
763 
    INT in_src2 = -1;
764 
    in_src2 = FLD (in_src2);
765 
    referenced |= 1 << 1;
766 
    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
767 
  }
768 
  return cycles;
769 
#undef FLD
770 
}
771 
 
772 
static int
773 
model_m32r_d_div (SIM_CPU *current_cpu, void *sem_arg)
774 
{
775 
#define FLD(f) abuf->fields.sfmt_add.f
776 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
777 
  const IDESC * UNUSED idesc = abuf->idesc;
778 
  int cycles = 0;
779 
  {
780 
    int referenced = 0;
781 
    int UNUSED insn_referenced = abuf->written;
782 
    INT in_sr = -1;
783 
    INT in_dr = -1;
784 
    INT out_dr = -1;
785 
    in_sr = FLD (in_sr);
786 
    in_dr = FLD (in_dr);
787 
    out_dr = FLD (out_dr);
788 
    referenced |= 1 << 0;
789 
    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
790 
    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
791 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
792 
  }
793 
  return cycles;
794 
#undef FLD
795 
}
796 
 
797 
static int
798 
model_m32r_d_divu (SIM_CPU *current_cpu, void *sem_arg)
799 
{
800 
#define FLD(f) abuf->fields.sfmt_add.f
801 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
802 
  const IDESC * UNUSED idesc = abuf->idesc;
803 
  int cycles = 0;
804 
  {
805 
    int referenced = 0;
806 
    int UNUSED insn_referenced = abuf->written;
807 
    INT in_sr = -1;
808 
    INT in_dr = -1;
809 
    INT out_dr = -1;
810 
    in_sr = FLD (in_sr);
811 
    in_dr = FLD (in_dr);
812 
    out_dr = FLD (out_dr);
813 
    referenced |= 1 << 0;
814 
    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
815 
    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
816 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
817 
  }
818 
  return cycles;
819 
#undef FLD
820 
}
821 
 
822 
static int
823 
model_m32r_d_rem (SIM_CPU *current_cpu, void *sem_arg)
824 
{
825 
#define FLD(f) abuf->fields.sfmt_add.f
826 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
827 
  const IDESC * UNUSED idesc = abuf->idesc;
828 
  int cycles = 0;
829 
  {
830 
    int referenced = 0;
831 
    int UNUSED insn_referenced = abuf->written;
832 
    INT in_sr = -1;
833 
    INT in_dr = -1;
834 
    INT out_dr = -1;
835 
    in_sr = FLD (in_sr);
836 
    in_dr = FLD (in_dr);
837 
    out_dr = FLD (out_dr);
838 
    referenced |= 1 << 0;
839 
    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
840 
    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
841 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
842 
  }
843 
  return cycles;
844 
#undef FLD
845 
}
846 
 
847 
static int
848 
model_m32r_d_remu (SIM_CPU *current_cpu, void *sem_arg)
849 
{
850 
#define FLD(f) abuf->fields.sfmt_add.f
851 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
852 
  const IDESC * UNUSED idesc = abuf->idesc;
853 
  int cycles = 0;
854 
  {
855 
    int referenced = 0;
856 
    int UNUSED insn_referenced = abuf->written;
857 
    INT in_sr = -1;
858 
    INT in_dr = -1;
859 
    INT out_dr = -1;
860 
    in_sr = FLD (in_sr);
861 
    in_dr = FLD (in_dr);
862 
    out_dr = FLD (out_dr);
863 
    referenced |= 1 << 0;
864 
    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
865 
    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
866 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
867 
  }
868 
  return cycles;
869 
#undef FLD
870 
}
871 
 
872 
static int
873 
model_m32r_d_jl (SIM_CPU *current_cpu, void *sem_arg)
874 
{
875 
#define FLD(f) abuf->fields.sfmt_jl.f
876 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
877 
  const IDESC * UNUSED idesc = abuf->idesc;
878 
  int cycles = 0;
879 
  {
880 
    int referenced = 0;
881 
    int UNUSED insn_referenced = abuf->written;
882 
    INT in_sr = -1;
883 
    in_sr = FLD (in_sr);
884 
    referenced |= 1 << 0;
885 
    referenced |= 1 << 1;
886 
    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
887 
  }
888 
  return cycles;
889 
#undef FLD
890 
}
891 
 
892 
static int
893 
model_m32r_d_jmp (SIM_CPU *current_cpu, void *sem_arg)
894 
{
895 
#define FLD(f) abuf->fields.sfmt_jl.f
896 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
897 
  const IDESC * UNUSED idesc = abuf->idesc;
898 
  int cycles = 0;
899 
  {
900 
    int referenced = 0;
901 
    int UNUSED insn_referenced = abuf->written;
902 
    INT in_sr = -1;
903 
    in_sr = FLD (in_sr);
904 
    referenced |= 1 << 0;
905 
    referenced |= 1 << 1;
906 
    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
907 
  }
908 
  return cycles;
909 
#undef FLD
910 
}
911 
 
912 
static int
913 
model_m32r_d_ld (SIM_CPU *current_cpu, void *sem_arg)
914 
{
915 
#define FLD(f) abuf->fields.sfmt_ld_plus.f
916 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
917 
  const IDESC * UNUSED idesc = abuf->idesc;
918 
  int cycles = 0;
919 
  {
920 
    int referenced = 0;
921 
    int UNUSED insn_referenced = abuf->written;
922 
    INT in_sr = 0;
923 
    INT out_dr = 0;
924 
    in_sr = FLD (in_sr);
925 
    out_dr = FLD (out_dr);
926 
    referenced |= 1 << 0;
927 
    referenced |= 1 << 1;
928 
    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
929 
  }
930 
  return cycles;
931 
#undef FLD
932 
}
933 
 
934 
static int
935 
model_m32r_d_ld_d (SIM_CPU *current_cpu, void *sem_arg)
936 
{
937 
#define FLD(f) abuf->fields.sfmt_add3.f
938 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
939 
  const IDESC * UNUSED idesc = abuf->idesc;
940 
  int cycles = 0;
941 
  {
942 
    int referenced = 0;
943 
    int UNUSED insn_referenced = abuf->written;
944 
    INT in_sr = 0;
945 
    INT out_dr = 0;
946 
    in_sr = FLD (in_sr);
947 
    out_dr = FLD (out_dr);
948 
    referenced |= 1 << 0;
949 
    referenced |= 1 << 1;
950 
    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
951 
  }
952 
  return cycles;
953 
#undef FLD
954 
}
955 
 
956 
static int
957 
model_m32r_d_ldb (SIM_CPU *current_cpu, void *sem_arg)
958 
{
959 
#define FLD(f) abuf->fields.sfmt_ld_plus.f
960 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
961 
  const IDESC * UNUSED idesc = abuf->idesc;
962 
  int cycles = 0;
963 
  {
964 
    int referenced = 0;
965 
    int UNUSED insn_referenced = abuf->written;
966 
    INT in_sr = 0;
967 
    INT out_dr = 0;
968 
    in_sr = FLD (in_sr);
969 
    out_dr = FLD (out_dr);
970 
    referenced |= 1 << 0;
971 
    referenced |= 1 << 1;
972 
    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
973 
  }
974 
  return cycles;
975 
#undef FLD
976 
}
977 
 
978 
static int
979 
model_m32r_d_ldb_d (SIM_CPU *current_cpu, void *sem_arg)
980 
{
981 
#define FLD(f) abuf->fields.sfmt_add3.f
982 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
983 
  const IDESC * UNUSED idesc = abuf->idesc;
984 
  int cycles = 0;
985 
  {
986 
    int referenced = 0;
987 
    int UNUSED insn_referenced = abuf->written;
988 
    INT in_sr = 0;
989 
    INT out_dr = 0;
990 
    in_sr = FLD (in_sr);
991 
    out_dr = FLD (out_dr);
992 
    referenced |= 1 << 0;
993 
    referenced |= 1 << 1;
994 
    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
995 
  }
996 
  return cycles;
997 
#undef FLD
998 
}
999 
 
1000 
static int
1001 
model_m32r_d_ldh (SIM_CPU *current_cpu, void *sem_arg)
1002 
{
1003 
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1004 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1005 
  const IDESC * UNUSED idesc = abuf->idesc;
1006 
  int cycles = 0;
1007 
  {
1008 
    int referenced = 0;
1009 
    int UNUSED insn_referenced = abuf->written;
1010 
    INT in_sr = 0;
1011 
    INT out_dr = 0;
1012 
    in_sr = FLD (in_sr);
1013 
    out_dr = FLD (out_dr);
1014 
    referenced |= 1 << 0;
1015 
    referenced |= 1 << 1;
1016 
    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1017 
  }
1018 
  return cycles;
1019 
#undef FLD
1020 
}
1021 
 
1022 
static int
1023 
model_m32r_d_ldh_d (SIM_CPU *current_cpu, void *sem_arg)
1024 
{
1025 
#define FLD(f) abuf->fields.sfmt_add3.f
1026 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1027 
  const IDESC * UNUSED idesc = abuf->idesc;
1028 
  int cycles = 0;
1029 
  {
1030 
    int referenced = 0;
1031 
    int UNUSED insn_referenced = abuf->written;
1032 
    INT in_sr = 0;
1033 
    INT out_dr = 0;
1034 
    in_sr = FLD (in_sr);
1035 
    out_dr = FLD (out_dr);
1036 
    referenced |= 1 << 0;
1037 
    referenced |= 1 << 1;
1038 
    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1039 
  }
1040 
  return cycles;
1041 
#undef FLD
1042 
}
1043 
 
1044 
static int
1045 
model_m32r_d_ldub (SIM_CPU *current_cpu, void *sem_arg)
1046 
{
1047 
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1048 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1049 
  const IDESC * UNUSED idesc = abuf->idesc;
1050 
  int cycles = 0;
1051 
  {
1052 
    int referenced = 0;
1053 
    int UNUSED insn_referenced = abuf->written;
1054 
    INT in_sr = 0;
1055 
    INT out_dr = 0;
1056 
    in_sr = FLD (in_sr);
1057 
    out_dr = FLD (out_dr);
1058 
    referenced |= 1 << 0;
1059 
    referenced |= 1 << 1;
1060 
    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1061 
  }
1062 
  return cycles;
1063 
#undef FLD
1064 
}
1065 
 
1066 
static int
1067 
model_m32r_d_ldub_d (SIM_CPU *current_cpu, void *sem_arg)
1068 
{
1069 
#define FLD(f) abuf->fields.sfmt_add3.f
1070 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1071 
  const IDESC * UNUSED idesc = abuf->idesc;
1072 
  int cycles = 0;
1073 
  {
1074 
    int referenced = 0;
1075 
    int UNUSED insn_referenced = abuf->written;
1076 
    INT in_sr = 0;
1077 
    INT out_dr = 0;
1078 
    in_sr = FLD (in_sr);
1079 
    out_dr = FLD (out_dr);
1080 
    referenced |= 1 << 0;
1081 
    referenced |= 1 << 1;
1082 
    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1083 
  }
1084 
  return cycles;
1085 
#undef FLD
1086 
}
1087 
 
1088 
static int
1089 
model_m32r_d_lduh (SIM_CPU *current_cpu, void *sem_arg)
1090 
{
1091 
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1092 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1093 
  const IDESC * UNUSED idesc = abuf->idesc;
1094 
  int cycles = 0;
1095 
  {
1096 
    int referenced = 0;
1097 
    int UNUSED insn_referenced = abuf->written;
1098 
    INT in_sr = 0;
1099 
    INT out_dr = 0;
1100 
    in_sr = FLD (in_sr);
1101 
    out_dr = FLD (out_dr);
1102 
    referenced |= 1 << 0;
1103 
    referenced |= 1 << 1;
1104 
    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1105 
  }
1106 
  return cycles;
1107 
#undef FLD
1108 
}
1109 
 
1110 
static int
1111 
model_m32r_d_lduh_d (SIM_CPU *current_cpu, void *sem_arg)
1112 
{
1113 
#define FLD(f) abuf->fields.sfmt_add3.f
1114 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1115 
  const IDESC * UNUSED idesc = abuf->idesc;
1116 
  int cycles = 0;
1117 
  {
1118 
    int referenced = 0;
1119 
    int UNUSED insn_referenced = abuf->written;
1120 
    INT in_sr = 0;
1121 
    INT out_dr = 0;
1122 
    in_sr = FLD (in_sr);
1123 
    out_dr = FLD (out_dr);
1124 
    referenced |= 1 << 0;
1125 
    referenced |= 1 << 1;
1126 
    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1127 
  }
1128 
  return cycles;
1129 
#undef FLD
1130 
}
1131 
 
1132 
static int
1133 
model_m32r_d_ld_plus (SIM_CPU *current_cpu, void *sem_arg)
1134 
{
1135 
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1136 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1137 
  const IDESC * UNUSED idesc = abuf->idesc;
1138 
  int cycles = 0;
1139 
  {
1140 
    int referenced = 0;
1141 
    int UNUSED insn_referenced = abuf->written;
1142 
    INT in_sr = 0;
1143 
    INT out_dr = 0;
1144 
    in_sr = FLD (in_sr);
1145 
    out_dr = FLD (out_dr);
1146 
    referenced |= 1 << 0;
1147 
    referenced |= 1 << 1;
1148 
    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1149 
  }
1150 
  {
1151 
    int referenced = 0;
1152 
    int UNUSED insn_referenced = abuf->written;
1153 
    INT in_sr = -1;
1154 
    INT in_dr = -1;
1155 
    INT out_dr = -1;
1156 
    in_dr = FLD (in_sr);
1157 
    out_dr = FLD (out_sr);
1158 
    referenced |= 1 << 0;
1159 
    referenced |= 1 << 2;
1160 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
1161 
  }
1162 
  return cycles;
1163 
#undef FLD
1164 
}
1165 
 
1166 
static int
1167 
model_m32r_d_ld24 (SIM_CPU *current_cpu, void *sem_arg)
1168 
{
1169 
#define FLD(f) abuf->fields.sfmt_ld24.f
1170 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1171 
  const IDESC * UNUSED idesc = abuf->idesc;
1172 
  int cycles = 0;
1173 
  {
1174 
    int referenced = 0;
1175 
    int UNUSED insn_referenced = abuf->written;
1176 
    INT in_sr = -1;
1177 
    INT in_dr = -1;
1178 
    INT out_dr = -1;
1179 
    out_dr = FLD (out_dr);
1180 
    referenced |= 1 << 2;
1181 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1182 
  }
1183 
  return cycles;
1184 
#undef FLD
1185 
}
1186 
 
1187 
static int
1188 
model_m32r_d_ldi8 (SIM_CPU *current_cpu, void *sem_arg)
1189 
{
1190 
#define FLD(f) abuf->fields.sfmt_addi.f
1191 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1192 
  const IDESC * UNUSED idesc = abuf->idesc;
1193 
  int cycles = 0;
1194 
  {
1195 
    int referenced = 0;
1196 
    int UNUSED insn_referenced = abuf->written;
1197 
    INT in_sr = -1;
1198 
    INT in_dr = -1;
1199 
    INT out_dr = -1;
1200 
    out_dr = FLD (out_dr);
1201 
    referenced |= 1 << 2;
1202 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1203 
  }
1204 
  return cycles;
1205 
#undef FLD
1206 
}
1207 
 
1208 
static int
1209 
model_m32r_d_ldi16 (SIM_CPU *current_cpu, void *sem_arg)
1210 
{
1211 
#define FLD(f) abuf->fields.sfmt_add3.f
1212 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1213 
  const IDESC * UNUSED idesc = abuf->idesc;
1214 
  int cycles = 0;
1215 
  {
1216 
    int referenced = 0;
1217 
    int UNUSED insn_referenced = abuf->written;
1218 
    INT in_sr = -1;
1219 
    INT in_dr = -1;
1220 
    INT out_dr = -1;
1221 
    out_dr = FLD (out_dr);
1222 
    referenced |= 1 << 2;
1223 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1224 
  }
1225 
  return cycles;
1226 
#undef FLD
1227 
}
1228 
 
1229 
static int
1230 
model_m32r_d_lock (SIM_CPU *current_cpu, void *sem_arg)
1231 
{
1232 
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1233 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1234 
  const IDESC * UNUSED idesc = abuf->idesc;
1235 
  int cycles = 0;
1236 
  {
1237 
    int referenced = 0;
1238 
    int UNUSED insn_referenced = abuf->written;
1239 
    INT in_sr = 0;
1240 
    INT out_dr = 0;
1241 
    in_sr = FLD (in_sr);
1242 
    out_dr = FLD (out_dr);
1243 
    referenced |= 1 << 0;
1244 
    referenced |= 1 << 1;
1245 
    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1246 
  }
1247 
  return cycles;
1248 
#undef FLD
1249 
}
1250 
 
1251 
static int
1252 
model_m32r_d_machi (SIM_CPU *current_cpu, void *sem_arg)
1253 
{
1254 
#define FLD(f) abuf->fields.sfmt_st_plus.f
1255 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1256 
  const IDESC * UNUSED idesc = abuf->idesc;
1257 
  int cycles = 0;
1258 
  {
1259 
    int referenced = 0;
1260 
    int UNUSED insn_referenced = abuf->written;
1261 
    INT in_src1 = -1;
1262 
    INT in_src2 = -1;
1263 
    in_src1 = FLD (in_src1);
1264 
    in_src2 = FLD (in_src2);
1265 
    referenced |= 1 << 0;
1266 
    referenced |= 1 << 1;
1267 
    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1268 
  }
1269 
  return cycles;
1270 
#undef FLD
1271 
}
1272 
 
1273 
static int
1274 
model_m32r_d_maclo (SIM_CPU *current_cpu, void *sem_arg)
1275 
{
1276 
#define FLD(f) abuf->fields.sfmt_st_plus.f
1277 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1278 
  const IDESC * UNUSED idesc = abuf->idesc;
1279 
  int cycles = 0;
1280 
  {
1281 
    int referenced = 0;
1282 
    int UNUSED insn_referenced = abuf->written;
1283 
    INT in_src1 = -1;
1284 
    INT in_src2 = -1;
1285 
    in_src1 = FLD (in_src1);
1286 
    in_src2 = FLD (in_src2);
1287 
    referenced |= 1 << 0;
1288 
    referenced |= 1 << 1;
1289 
    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1290 
  }
1291 
  return cycles;
1292 
#undef FLD
1293 
}
1294 
 
1295 
static int
1296 
model_m32r_d_macwhi (SIM_CPU *current_cpu, void *sem_arg)
1297 
{
1298 
#define FLD(f) abuf->fields.sfmt_st_plus.f
1299 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1300 
  const IDESC * UNUSED idesc = abuf->idesc;
1301 
  int cycles = 0;
1302 
  {
1303 
    int referenced = 0;
1304 
    int UNUSED insn_referenced = abuf->written;
1305 
    INT in_src1 = -1;
1306 
    INT in_src2 = -1;
1307 
    in_src1 = FLD (in_src1);
1308 
    in_src2 = FLD (in_src2);
1309 
    referenced |= 1 << 0;
1310 
    referenced |= 1 << 1;
1311 
    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1312 
  }
1313 
  return cycles;
1314 
#undef FLD
1315 
}
1316 
 
1317 
static int
1318 
model_m32r_d_macwlo (SIM_CPU *current_cpu, void *sem_arg)
1319 
{
1320 
#define FLD(f) abuf->fields.sfmt_st_plus.f
1321 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1322 
  const IDESC * UNUSED idesc = abuf->idesc;
1323 
  int cycles = 0;
1324 
  {
1325 
    int referenced = 0;
1326 
    int UNUSED insn_referenced = abuf->written;
1327 
    INT in_src1 = -1;
1328 
    INT in_src2 = -1;
1329 
    in_src1 = FLD (in_src1);
1330 
    in_src2 = FLD (in_src2);
1331 
    referenced |= 1 << 0;
1332 
    referenced |= 1 << 1;
1333 
    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1334 
  }
1335 
  return cycles;
1336 
#undef FLD
1337 
}
1338 
 
1339 
static int
1340 
model_m32r_d_mul (SIM_CPU *current_cpu, void *sem_arg)
1341 
{
1342 
#define FLD(f) abuf->fields.sfmt_add.f
1343 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1344 
  const IDESC * UNUSED idesc = abuf->idesc;
1345 
  int cycles = 0;
1346 
  {
1347 
    int referenced = 0;
1348 
    int UNUSED insn_referenced = abuf->written;
1349 
    INT in_sr = -1;
1350 
    INT in_dr = -1;
1351 
    INT out_dr = -1;
1352 
    in_sr = FLD (in_sr);
1353 
    in_dr = FLD (in_dr);
1354 
    out_dr = FLD (out_dr);
1355 
    referenced |= 1 << 0;
1356 
    referenced |= 1 << 1;
1357 
    referenced |= 1 << 2;
1358 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1359 
  }
1360 
  return cycles;
1361 
#undef FLD
1362 
}
1363 
 
1364 
static int
1365 
model_m32r_d_mulhi (SIM_CPU *current_cpu, void *sem_arg)
1366 
{
1367 
#define FLD(f) abuf->fields.sfmt_st_plus.f
1368 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1369 
  const IDESC * UNUSED idesc = abuf->idesc;
1370 
  int cycles = 0;
1371 
  {
1372 
    int referenced = 0;
1373 
    int UNUSED insn_referenced = abuf->written;
1374 
    INT in_src1 = -1;
1375 
    INT in_src2 = -1;
1376 
    in_src1 = FLD (in_src1);
1377 
    in_src2 = FLD (in_src2);
1378 
    referenced |= 1 << 0;
1379 
    referenced |= 1 << 1;
1380 
    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1381 
  }
1382 
  return cycles;
1383 
#undef FLD
1384 
}
1385 
 
1386 
static int
1387 
model_m32r_d_mullo (SIM_CPU *current_cpu, void *sem_arg)
1388 
{
1389 
#define FLD(f) abuf->fields.sfmt_st_plus.f
1390 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1391 
  const IDESC * UNUSED idesc = abuf->idesc;
1392 
  int cycles = 0;
1393 
  {
1394 
    int referenced = 0;
1395 
    int UNUSED insn_referenced = abuf->written;
1396 
    INT in_src1 = -1;
1397 
    INT in_src2 = -1;
1398 
    in_src1 = FLD (in_src1);
1399 
    in_src2 = FLD (in_src2);
1400 
    referenced |= 1 << 0;
1401 
    referenced |= 1 << 1;
1402 
    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1403 
  }
1404 
  return cycles;
1405 
#undef FLD
1406 
}
1407 
 
1408 
static int
1409 
model_m32r_d_mulwhi (SIM_CPU *current_cpu, void *sem_arg)
1410 
{
1411 
#define FLD(f) abuf->fields.sfmt_st_plus.f
1412 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1413 
  const IDESC * UNUSED idesc = abuf->idesc;
1414 
  int cycles = 0;
1415 
  {
1416 
    int referenced = 0;
1417 
    int UNUSED insn_referenced = abuf->written;
1418 
    INT in_src1 = -1;
1419 
    INT in_src2 = -1;
1420 
    in_src1 = FLD (in_src1);
1421 
    in_src2 = FLD (in_src2);
1422 
    referenced |= 1 << 0;
1423 
    referenced |= 1 << 1;
1424 
    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1425 
  }
1426 
  return cycles;
1427 
#undef FLD
1428 
}
1429 
 
1430 
static int
1431 
model_m32r_d_mulwlo (SIM_CPU *current_cpu, void *sem_arg)
1432 
{
1433 
#define FLD(f) abuf->fields.sfmt_st_plus.f
1434 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1435 
  const IDESC * UNUSED idesc = abuf->idesc;
1436 
  int cycles = 0;
1437 
  {
1438 
    int referenced = 0;
1439 
    int UNUSED insn_referenced = abuf->written;
1440 
    INT in_src1 = -1;
1441 
    INT in_src2 = -1;
1442 
    in_src1 = FLD (in_src1);
1443 
    in_src2 = FLD (in_src2);
1444 
    referenced |= 1 << 0;
1445 
    referenced |= 1 << 1;
1446 
    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1447 
  }
1448 
  return cycles;
1449 
#undef FLD
1450 
}
1451 
 
1452 
static int
1453 
model_m32r_d_mv (SIM_CPU *current_cpu, void *sem_arg)
1454 
{
1455 
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1456 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1457 
  const IDESC * UNUSED idesc = abuf->idesc;
1458 
  int cycles = 0;
1459 
  {
1460 
    int referenced = 0;
1461 
    int UNUSED insn_referenced = abuf->written;
1462 
    INT in_sr = -1;
1463 
    INT in_dr = -1;
1464 
    INT out_dr = -1;
1465 
    in_sr = FLD (in_sr);
1466 
    out_dr = FLD (out_dr);
1467 
    referenced |= 1 << 0;
1468 
    referenced |= 1 << 2;
1469 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1470 
  }
1471 
  return cycles;
1472 
#undef FLD
1473 
}
1474 
 
1475 
static int
1476 
model_m32r_d_mvfachi (SIM_CPU *current_cpu, void *sem_arg)
1477 
{
1478 
#define FLD(f) abuf->fields.sfmt_seth.f
1479 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1480 
  const IDESC * UNUSED idesc = abuf->idesc;
1481 
  int cycles = 0;
1482 
  {
1483 
    int referenced = 0;
1484 
    int UNUSED insn_referenced = abuf->written;
1485 
    INT in_sr = -1;
1486 
    INT in_dr = -1;
1487 
    INT out_dr = -1;
1488 
    out_dr = FLD (out_dr);
1489 
    referenced |= 1 << 2;
1490 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1491 
  }
1492 
  return cycles;
1493 
#undef FLD
1494 
}
1495 
 
1496 
static int
1497 
model_m32r_d_mvfaclo (SIM_CPU *current_cpu, void *sem_arg)
1498 
{
1499 
#define FLD(f) abuf->fields.sfmt_seth.f
1500 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1501 
  const IDESC * UNUSED idesc = abuf->idesc;
1502 
  int cycles = 0;
1503 
  {
1504 
    int referenced = 0;
1505 
    int UNUSED insn_referenced = abuf->written;
1506 
    INT in_sr = -1;
1507 
    INT in_dr = -1;
1508 
    INT out_dr = -1;
1509 
    out_dr = FLD (out_dr);
1510 
    referenced |= 1 << 2;
1511 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1512 
  }
1513 
  return cycles;
1514 
#undef FLD
1515 
}
1516 
 
1517 
static int
1518 
model_m32r_d_mvfacmi (SIM_CPU *current_cpu, void *sem_arg)
1519 
{
1520 
#define FLD(f) abuf->fields.sfmt_seth.f
1521 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1522 
  const IDESC * UNUSED idesc = abuf->idesc;
1523 
  int cycles = 0;
1524 
  {
1525 
    int referenced = 0;
1526 
    int UNUSED insn_referenced = abuf->written;
1527 
    INT in_sr = -1;
1528 
    INT in_dr = -1;
1529 
    INT out_dr = -1;
1530 
    out_dr = FLD (out_dr);
1531 
    referenced |= 1 << 2;
1532 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1533 
  }
1534 
  return cycles;
1535 
#undef FLD
1536 
}
1537 
 
1538 
static int
1539 
model_m32r_d_mvfc (SIM_CPU *current_cpu, void *sem_arg)
1540 
{
1541 
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1542 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1543 
  const IDESC * UNUSED idesc = abuf->idesc;
1544 
  int cycles = 0;
1545 
  {
1546 
    int referenced = 0;
1547 
    int UNUSED insn_referenced = abuf->written;
1548 
    INT in_sr = -1;
1549 
    INT in_dr = -1;
1550 
    INT out_dr = -1;
1551 
    out_dr = FLD (out_dr);
1552 
    referenced |= 1 << 2;
1553 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1554 
  }
1555 
  return cycles;
1556 
#undef FLD
1557 
}
1558 
 
1559 
static int
1560 
model_m32r_d_mvtachi (SIM_CPU *current_cpu, void *sem_arg)
1561 
{
1562 
#define FLD(f) abuf->fields.sfmt_st_plus.f
1563 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1564 
  const IDESC * UNUSED idesc = abuf->idesc;
1565 
  int cycles = 0;
1566 
  {
1567 
    int referenced = 0;
1568 
    int UNUSED insn_referenced = abuf->written;
1569 
    INT in_sr = -1;
1570 
    INT in_dr = -1;
1571 
    INT out_dr = -1;
1572 
    in_sr = FLD (in_src1);
1573 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1574 
  }
1575 
  return cycles;
1576 
#undef FLD
1577 
}
1578 
 
1579 
static int
1580 
model_m32r_d_mvtaclo (SIM_CPU *current_cpu, void *sem_arg)
1581 
{
1582 
#define FLD(f) abuf->fields.sfmt_st_plus.f
1583 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1584 
  const IDESC * UNUSED idesc = abuf->idesc;
1585 
  int cycles = 0;
1586 
  {
1587 
    int referenced = 0;
1588 
    int UNUSED insn_referenced = abuf->written;
1589 
    INT in_sr = -1;
1590 
    INT in_dr = -1;
1591 
    INT out_dr = -1;
1592 
    in_sr = FLD (in_src1);
1593 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1594 
  }
1595 
  return cycles;
1596 
#undef FLD
1597 
}
1598 
 
1599 
static int
1600 
model_m32r_d_mvtc (SIM_CPU *current_cpu, void *sem_arg)
1601 
{
1602 
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1603 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1604 
  const IDESC * UNUSED idesc = abuf->idesc;
1605 
  int cycles = 0;
1606 
  {
1607 
    int referenced = 0;
1608 
    int UNUSED insn_referenced = abuf->written;
1609 
    INT in_sr = -1;
1610 
    INT in_dr = -1;
1611 
    INT out_dr = -1;
1612 
    in_sr = FLD (in_sr);
1613 
    referenced |= 1 << 0;
1614 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1615 
  }
1616 
  return cycles;
1617 
#undef FLD
1618 
}
1619 
 
1620 
static int
1621 
model_m32r_d_neg (SIM_CPU *current_cpu, void *sem_arg)
1622 
{
1623 
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1624 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1625 
  const IDESC * UNUSED idesc = abuf->idesc;
1626 
  int cycles = 0;
1627 
  {
1628 
    int referenced = 0;
1629 
    int UNUSED insn_referenced = abuf->written;
1630 
    INT in_sr = -1;
1631 
    INT in_dr = -1;
1632 
    INT out_dr = -1;
1633 
    in_sr = FLD (in_sr);
1634 
    out_dr = FLD (out_dr);
1635 
    referenced |= 1 << 0;
1636 
    referenced |= 1 << 2;
1637 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1638 
  }
1639 
  return cycles;
1640 
#undef FLD
1641 
}
1642 
 
1643 
static int
1644 
model_m32r_d_nop (SIM_CPU *current_cpu, void *sem_arg)
1645 
{
1646 
#define FLD(f) abuf->fields.fmt_empty.f
1647 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1648 
  const IDESC * UNUSED idesc = abuf->idesc;
1649 
  int cycles = 0;
1650 
  {
1651 
    int referenced = 0;
1652 
    int UNUSED insn_referenced = abuf->written;
1653 
    INT in_sr = -1;
1654 
    INT in_dr = -1;
1655 
    INT out_dr = -1;
1656 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1657 
  }
1658 
  return cycles;
1659 
#undef FLD
1660 
}
1661 
 
1662 
static int
1663 
model_m32r_d_not (SIM_CPU *current_cpu, void *sem_arg)
1664 
{
1665 
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1666 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1667 
  const IDESC * UNUSED idesc = abuf->idesc;
1668 
  int cycles = 0;
1669 
  {
1670 
    int referenced = 0;
1671 
    int UNUSED insn_referenced = abuf->written;
1672 
    INT in_sr = -1;
1673 
    INT in_dr = -1;
1674 
    INT out_dr = -1;
1675 
    in_sr = FLD (in_sr);
1676 
    out_dr = FLD (out_dr);
1677 
    referenced |= 1 << 0;
1678 
    referenced |= 1 << 2;
1679 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1680 
  }
1681 
  return cycles;
1682 
#undef FLD
1683 
}
1684 
 
1685 
static int
1686 
model_m32r_d_rac (SIM_CPU *current_cpu, void *sem_arg)
1687 
{
1688 
#define FLD(f) abuf->fields.fmt_empty.f
1689 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1690 
  const IDESC * UNUSED idesc = abuf->idesc;
1691 
  int cycles = 0;
1692 
  {
1693 
    int referenced = 0;
1694 
    int UNUSED insn_referenced = abuf->written;
1695 
    INT in_src1 = -1;
1696 
    INT in_src2 = -1;
1697 
    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1698 
  }
1699 
  return cycles;
1700 
#undef FLD
1701 
}
1702 
 
1703 
static int
1704 
model_m32r_d_rach (SIM_CPU *current_cpu, void *sem_arg)
1705 
{
1706 
#define FLD(f) abuf->fields.fmt_empty.f
1707 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1708 
  const IDESC * UNUSED idesc = abuf->idesc;
1709 
  int cycles = 0;
1710 
  {
1711 
    int referenced = 0;
1712 
    int UNUSED insn_referenced = abuf->written;
1713 
    INT in_src1 = -1;
1714 
    INT in_src2 = -1;
1715 
    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1716 
  }
1717 
  return cycles;
1718 
#undef FLD
1719 
}
1720 
 
1721 
static int
1722 
model_m32r_d_rte (SIM_CPU *current_cpu, void *sem_arg)
1723 
{
1724 
#define FLD(f) abuf->fields.fmt_empty.f
1725 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1726 
  const IDESC * UNUSED idesc = abuf->idesc;
1727 
  int cycles = 0;
1728 
  {
1729 
    int referenced = 0;
1730 
    int UNUSED insn_referenced = abuf->written;
1731 
    INT in_sr = -1;
1732 
    INT in_dr = -1;
1733 
    INT out_dr = -1;
1734 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1735 
  }
1736 
  return cycles;
1737 
#undef FLD
1738 
}
1739 
 
1740 
static int
1741 
model_m32r_d_seth (SIM_CPU *current_cpu, void *sem_arg)
1742 
{
1743 
#define FLD(f) abuf->fields.sfmt_seth.f
1744 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1745 
  const IDESC * UNUSED idesc = abuf->idesc;
1746 
  int cycles = 0;
1747 
  {
1748 
    int referenced = 0;
1749 
    int UNUSED insn_referenced = abuf->written;
1750 
    INT in_sr = -1;
1751 
    INT in_dr = -1;
1752 
    INT out_dr = -1;
1753 
    out_dr = FLD (out_dr);
1754 
    referenced |= 1 << 2;
1755 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1756 
  }
1757 
  return cycles;
1758 
#undef FLD
1759 
}
1760 
 
1761 
static int
1762 
model_m32r_d_sll (SIM_CPU *current_cpu, void *sem_arg)
1763 
{
1764 
#define FLD(f) abuf->fields.sfmt_add.f
1765 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1766 
  const IDESC * UNUSED idesc = abuf->idesc;
1767 
  int cycles = 0;
1768 
  {
1769 
    int referenced = 0;
1770 
    int UNUSED insn_referenced = abuf->written;
1771 
    INT in_sr = -1;
1772 
    INT in_dr = -1;
1773 
    INT out_dr = -1;
1774 
    in_sr = FLD (in_sr);
1775 
    in_dr = FLD (in_dr);
1776 
    out_dr = FLD (out_dr);
1777 
    referenced |= 1 << 0;
1778 
    referenced |= 1 << 1;
1779 
    referenced |= 1 << 2;
1780 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1781 
  }
1782 
  return cycles;
1783 
#undef FLD
1784 
}
1785 
 
1786 
static int
1787 
model_m32r_d_sll3 (SIM_CPU *current_cpu, void *sem_arg)
1788 
{
1789 
#define FLD(f) abuf->fields.sfmt_add3.f
1790 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1791 
  const IDESC * UNUSED idesc = abuf->idesc;
1792 
  int cycles = 0;
1793 
  {
1794 
    int referenced = 0;
1795 
    int UNUSED insn_referenced = abuf->written;
1796 
    INT in_sr = -1;
1797 
    INT in_dr = -1;
1798 
    INT out_dr = -1;
1799 
    in_sr = FLD (in_sr);
1800 
    out_dr = FLD (out_dr);
1801 
    referenced |= 1 << 0;
1802 
    referenced |= 1 << 2;
1803 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1804 
  }
1805 
  return cycles;
1806 
#undef FLD
1807 
}
1808 
 
1809 
static int
1810 
model_m32r_d_slli (SIM_CPU *current_cpu, void *sem_arg)
1811 
{
1812 
#define FLD(f) abuf->fields.sfmt_slli.f
1813 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1814 
  const IDESC * UNUSED idesc = abuf->idesc;
1815 
  int cycles = 0;
1816 
  {
1817 
    int referenced = 0;
1818 
    int UNUSED insn_referenced = abuf->written;
1819 
    INT in_sr = -1;
1820 
    INT in_dr = -1;
1821 
    INT out_dr = -1;
1822 
    in_dr = FLD (in_dr);
1823 
    out_dr = FLD (out_dr);
1824 
    referenced |= 1 << 1;
1825 
    referenced |= 1 << 2;
1826 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1827 
  }
1828 
  return cycles;
1829 
#undef FLD
1830 
}
1831 
 
1832 
static int
1833 
model_m32r_d_sra (SIM_CPU *current_cpu, void *sem_arg)
1834 
{
1835 
#define FLD(f) abuf->fields.sfmt_add.f
1836 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1837 
  const IDESC * UNUSED idesc = abuf->idesc;
1838 
  int cycles = 0;
1839 
  {
1840 
    int referenced = 0;
1841 
    int UNUSED insn_referenced = abuf->written;
1842 
    INT in_sr = -1;
1843 
    INT in_dr = -1;
1844 
    INT out_dr = -1;
1845 
    in_sr = FLD (in_sr);
1846 
    in_dr = FLD (in_dr);
1847 
    out_dr = FLD (out_dr);
1848 
    referenced |= 1 << 0;
1849 
    referenced |= 1 << 1;
1850 
    referenced |= 1 << 2;
1851 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1852 
  }
1853 
  return cycles;
1854 
#undef FLD
1855 
}
1856 
 
1857 
static int
1858 
model_m32r_d_sra3 (SIM_CPU *current_cpu, void *sem_arg)
1859 
{
1860 
#define FLD(f) abuf->fields.sfmt_add3.f
1861 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1862 
  const IDESC * UNUSED idesc = abuf->idesc;
1863 
  int cycles = 0;
1864 
  {
1865 
    int referenced = 0;
1866 
    int UNUSED insn_referenced = abuf->written;
1867 
    INT in_sr = -1;
1868 
    INT in_dr = -1;
1869 
    INT out_dr = -1;
1870 
    in_sr = FLD (in_sr);
1871 
    out_dr = FLD (out_dr);
1872 
    referenced |= 1 << 0;
1873 
    referenced |= 1 << 2;
1874 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1875 
  }
1876 
  return cycles;
1877 
#undef FLD
1878 
}
1879 
 
1880 
static int
1881 
model_m32r_d_srai (SIM_CPU *current_cpu, void *sem_arg)
1882 
{
1883 
#define FLD(f) abuf->fields.sfmt_slli.f
1884 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1885 
  const IDESC * UNUSED idesc = abuf->idesc;
1886 
  int cycles = 0;
1887 
  {
1888 
    int referenced = 0;
1889 
    int UNUSED insn_referenced = abuf->written;
1890 
    INT in_sr = -1;
1891 
    INT in_dr = -1;
1892 
    INT out_dr = -1;
1893 
    in_dr = FLD (in_dr);
1894 
    out_dr = FLD (out_dr);
1895 
    referenced |= 1 << 1;
1896 
    referenced |= 1 << 2;
1897 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1898 
  }
1899 
  return cycles;
1900 
#undef FLD
1901 
}
1902 
 
1903 
static int
1904 
model_m32r_d_srl (SIM_CPU *current_cpu, void *sem_arg)
1905 
{
1906 
#define FLD(f) abuf->fields.sfmt_add.f
1907 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1908 
  const IDESC * UNUSED idesc = abuf->idesc;
1909 
  int cycles = 0;
1910 
  {
1911 
    int referenced = 0;
1912 
    int UNUSED insn_referenced = abuf->written;
1913 
    INT in_sr = -1;
1914 
    INT in_dr = -1;
1915 
    INT out_dr = -1;
1916 
    in_sr = FLD (in_sr);
1917 
    in_dr = FLD (in_dr);
1918 
    out_dr = FLD (out_dr);
1919 
    referenced |= 1 << 0;
1920 
    referenced |= 1 << 1;
1921 
    referenced |= 1 << 2;
1922 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1923 
  }
1924 
  return cycles;
1925 
#undef FLD
1926 
}
1927 
 
1928 
static int
1929 
model_m32r_d_srl3 (SIM_CPU *current_cpu, void *sem_arg)
1930 
{
1931 
#define FLD(f) abuf->fields.sfmt_add3.f
1932 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1933 
  const IDESC * UNUSED idesc = abuf->idesc;
1934 
  int cycles = 0;
1935 
  {
1936 
    int referenced = 0;
1937 
    int UNUSED insn_referenced = abuf->written;
1938 
    INT in_sr = -1;
1939 
    INT in_dr = -1;
1940 
    INT out_dr = -1;
1941 
    in_sr = FLD (in_sr);
1942 
    out_dr = FLD (out_dr);
1943 
    referenced |= 1 << 0;
1944 
    referenced |= 1 << 2;
1945 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1946 
  }
1947 
  return cycles;
1948 
#undef FLD
1949 
}
1950 
 
1951 
static int
1952 
model_m32r_d_srli (SIM_CPU *current_cpu, void *sem_arg)
1953 
{
1954 
#define FLD(f) abuf->fields.sfmt_slli.f
1955 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1956 
  const IDESC * UNUSED idesc = abuf->idesc;
1957 
  int cycles = 0;
1958 
  {
1959 
    int referenced = 0;
1960 
    int UNUSED insn_referenced = abuf->written;
1961 
    INT in_sr = -1;
1962 
    INT in_dr = -1;
1963 
    INT out_dr = -1;
1964 
    in_dr = FLD (in_dr);
1965 
    out_dr = FLD (out_dr);
1966 
    referenced |= 1 << 1;
1967 
    referenced |= 1 << 2;
1968 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1969 
  }
1970 
  return cycles;
1971 
#undef FLD
1972 
}
1973 
 
1974 
static int
1975 
model_m32r_d_st (SIM_CPU *current_cpu, void *sem_arg)
1976 
{
1977 
#define FLD(f) abuf->fields.sfmt_st_plus.f
1978 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1979 
  const IDESC * UNUSED idesc = abuf->idesc;
1980 
  int cycles = 0;
1981 
  {
1982 
    int referenced = 0;
1983 
    int UNUSED insn_referenced = abuf->written;
1984 
    INT in_src1 = 0;
1985 
    INT in_src2 = 0;
1986 
    in_src1 = FLD (in_src1);
1987 
    in_src2 = FLD (in_src2);
1988 
    referenced |= 1 << 0;
1989 
    referenced |= 1 << 1;
1990 
    cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1991 
  }
1992 
  return cycles;
1993 
#undef FLD
1994 
}
1995 
 
1996 
static int
1997 
model_m32r_d_st_d (SIM_CPU *current_cpu, void *sem_arg)
1998 
{
1999 
#define FLD(f) abuf->fields.sfmt_st_d.f
2000 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2001 
  const IDESC * UNUSED idesc = abuf->idesc;
2002 
  int cycles = 0;
2003 
  {
2004 
    int referenced = 0;
2005 
    int UNUSED insn_referenced = abuf->written;
2006 
    INT in_src1 = 0;
2007 
    INT in_src2 = 0;
2008 
    in_src1 = FLD (in_src1);
2009 
    in_src2 = FLD (in_src2);
2010 
    referenced |= 1 << 0;
2011 
    referenced |= 1 << 1;
2012 
    cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2013 
  }
2014 
  return cycles;
2015 
#undef FLD
2016 
}
2017 
 
2018 
static int
2019 
model_m32r_d_stb (SIM_CPU *current_cpu, void *sem_arg)
2020 
{
2021 
#define FLD(f) abuf->fields.sfmt_st_plus.f
2022 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2023 
  const IDESC * UNUSED idesc = abuf->idesc;
2024 
  int cycles = 0;
2025 
  {
2026 
    int referenced = 0;
2027 
    int UNUSED insn_referenced = abuf->written;
2028 
    INT in_src1 = 0;
2029 
    INT in_src2 = 0;
2030 
    in_src1 = FLD (in_src1);
2031 
    in_src2 = FLD (in_src2);
2032 
    referenced |= 1 << 0;
2033 
    referenced |= 1 << 1;
2034 
    cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2035 
  }
2036 
  return cycles;
2037 
#undef FLD
2038 
}
2039 
 
2040 
static int
2041 
model_m32r_d_stb_d (SIM_CPU *current_cpu, void *sem_arg)
2042 
{
2043 
#define FLD(f) abuf->fields.sfmt_st_d.f
2044 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2045 
  const IDESC * UNUSED idesc = abuf->idesc;
2046 
  int cycles = 0;
2047 
  {
2048 
    int referenced = 0;
2049 
    int UNUSED insn_referenced = abuf->written;
2050 
    INT in_src1 = 0;
2051 
    INT in_src2 = 0;
2052 
    in_src1 = FLD (in_src1);
2053 
    in_src2 = FLD (in_src2);
2054 
    referenced |= 1 << 0;
2055 
    referenced |= 1 << 1;
2056 
    cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2057 
  }
2058 
  return cycles;
2059 
#undef FLD
2060 
}
2061 
 
2062 
static int
2063 
model_m32r_d_sth (SIM_CPU *current_cpu, void *sem_arg)
2064 
{
2065 
#define FLD(f) abuf->fields.sfmt_st_plus.f
2066 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2067 
  const IDESC * UNUSED idesc = abuf->idesc;
2068 
  int cycles = 0;
2069 
  {
2070 
    int referenced = 0;
2071 
    int UNUSED insn_referenced = abuf->written;
2072 
    INT in_src1 = 0;
2073 
    INT in_src2 = 0;
2074 
    in_src1 = FLD (in_src1);
2075 
    in_src2 = FLD (in_src2);
2076 
    referenced |= 1 << 0;
2077 
    referenced |= 1 << 1;
2078 
    cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2079 
  }
2080 
  return cycles;
2081 
#undef FLD
2082 
}
2083 
 
2084 
static int
2085 
model_m32r_d_sth_d (SIM_CPU *current_cpu, void *sem_arg)
2086 
{
2087 
#define FLD(f) abuf->fields.sfmt_st_d.f
2088 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2089 
  const IDESC * UNUSED idesc = abuf->idesc;
2090 
  int cycles = 0;
2091 
  {
2092 
    int referenced = 0;
2093 
    int UNUSED insn_referenced = abuf->written;
2094 
    INT in_src1 = 0;
2095 
    INT in_src2 = 0;
2096 
    in_src1 = FLD (in_src1);
2097 
    in_src2 = FLD (in_src2);
2098 
    referenced |= 1 << 0;
2099 
    referenced |= 1 << 1;
2100 
    cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2101 
  }
2102 
  return cycles;
2103 
#undef FLD
2104 
}
2105 
 
2106 
static int
2107 
model_m32r_d_st_plus (SIM_CPU *current_cpu, void *sem_arg)
2108 
{
2109 
#define FLD(f) abuf->fields.sfmt_st_plus.f
2110 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2111 
  const IDESC * UNUSED idesc = abuf->idesc;
2112 
  int cycles = 0;
2113 
  {
2114 
    int referenced = 0;
2115 
    int UNUSED insn_referenced = abuf->written;
2116 
    INT in_src1 = 0;
2117 
    INT in_src2 = 0;
2118 
    in_src1 = FLD (in_src1);
2119 
    in_src2 = FLD (in_src2);
2120 
    referenced |= 1 << 0;
2121 
    referenced |= 1 << 1;
2122 
    cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2123 
  }
2124 
  {
2125 
    int referenced = 0;
2126 
    int UNUSED insn_referenced = abuf->written;
2127 
    INT in_sr = -1;
2128 
    INT in_dr = -1;
2129 
    INT out_dr = -1;
2130 
    in_dr = FLD (in_src2);
2131 
    out_dr = FLD (out_src2);
2132 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
2133 
  }
2134 
  return cycles;
2135 
#undef FLD
2136 
}
2137 
 
2138 
static int
2139 
model_m32r_d_st_minus (SIM_CPU *current_cpu, void *sem_arg)
2140 
{
2141 
#define FLD(f) abuf->fields.sfmt_st_plus.f
2142 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2143 
  const IDESC * UNUSED idesc = abuf->idesc;
2144 
  int cycles = 0;
2145 
  {
2146 
    int referenced = 0;
2147 
    int UNUSED insn_referenced = abuf->written;
2148 
    INT in_src1 = 0;
2149 
    INT in_src2 = 0;
2150 
    in_src1 = FLD (in_src1);
2151 
    in_src2 = FLD (in_src2);
2152 
    referenced |= 1 << 0;
2153 
    referenced |= 1 << 1;
2154 
    cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2155 
  }
2156 
  {
2157 
    int referenced = 0;
2158 
    int UNUSED insn_referenced = abuf->written;
2159 
    INT in_sr = -1;
2160 
    INT in_dr = -1;
2161 
    INT out_dr = -1;
2162 
    in_dr = FLD (in_src2);
2163 
    out_dr = FLD (out_src2);
2164 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
2165 
  }
2166 
  return cycles;
2167 
#undef FLD
2168 
}
2169 
 
2170 
static int
2171 
model_m32r_d_sub (SIM_CPU *current_cpu, void *sem_arg)
2172 
{
2173 
#define FLD(f) abuf->fields.sfmt_add.f
2174 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2175 
  const IDESC * UNUSED idesc = abuf->idesc;
2176 
  int cycles = 0;
2177 
  {
2178 
    int referenced = 0;
2179 
    int UNUSED insn_referenced = abuf->written;
2180 
    INT in_sr = -1;
2181 
    INT in_dr = -1;
2182 
    INT out_dr = -1;
2183 
    in_sr = FLD (in_sr);
2184 
    in_dr = FLD (in_dr);
2185 
    out_dr = FLD (out_dr);
2186 
    referenced |= 1 << 0;
2187 
    referenced |= 1 << 1;
2188 
    referenced |= 1 << 2;
2189 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2190 
  }
2191 
  return cycles;
2192 
#undef FLD
2193 
}
2194 
 
2195 
static int
2196 
model_m32r_d_subv (SIM_CPU *current_cpu, void *sem_arg)
2197 
{
2198 
#define FLD(f) abuf->fields.sfmt_add.f
2199 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2200 
  const IDESC * UNUSED idesc = abuf->idesc;
2201 
  int cycles = 0;
2202 
  {
2203 
    int referenced = 0;
2204 
    int UNUSED insn_referenced = abuf->written;
2205 
    INT in_sr = -1;
2206 
    INT in_dr = -1;
2207 
    INT out_dr = -1;
2208 
    in_sr = FLD (in_sr);
2209 
    in_dr = FLD (in_dr);
2210 
    out_dr = FLD (out_dr);
2211 
    referenced |= 1 << 0;
2212 
    referenced |= 1 << 1;
2213 
    referenced |= 1 << 2;
2214 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2215 
  }
2216 
  return cycles;
2217 
#undef FLD
2218 
}
2219 
 
2220 
static int
2221 
model_m32r_d_subx (SIM_CPU *current_cpu, void *sem_arg)
2222 
{
2223 
#define FLD(f) abuf->fields.sfmt_add.f
2224 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2225 
  const IDESC * UNUSED idesc = abuf->idesc;
2226 
  int cycles = 0;
2227 
  {
2228 
    int referenced = 0;
2229 
    int UNUSED insn_referenced = abuf->written;
2230 
    INT in_sr = -1;
2231 
    INT in_dr = -1;
2232 
    INT out_dr = -1;
2233 
    in_sr = FLD (in_sr);
2234 
    in_dr = FLD (in_dr);
2235 
    out_dr = FLD (out_dr);
2236 
    referenced |= 1 << 0;
2237 
    referenced |= 1 << 1;
2238 
    referenced |= 1 << 2;
2239 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2240 
  }
2241 
  return cycles;
2242 
#undef FLD
2243 
}
2244 
 
2245 
static int
2246 
model_m32r_d_trap (SIM_CPU *current_cpu, void *sem_arg)
2247 
{
2248 
#define FLD(f) abuf->fields.sfmt_trap.f
2249 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2250 
  const IDESC * UNUSED idesc = abuf->idesc;
2251 
  int cycles = 0;
2252 
  {
2253 
    int referenced = 0;
2254 
    int UNUSED insn_referenced = abuf->written;
2255 
    INT in_sr = -1;
2256 
    INT in_dr = -1;
2257 
    INT out_dr = -1;
2258 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2259 
  }
2260 
  return cycles;
2261 
#undef FLD
2262 
}
2263 
 
2264 
static int
2265 
model_m32r_d_unlock (SIM_CPU *current_cpu, void *sem_arg)
2266 
{
2267 
#define FLD(f) abuf->fields.sfmt_st_plus.f
2268 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2269 
  const IDESC * UNUSED idesc = abuf->idesc;
2270 
  int cycles = 0;
2271 
  {
2272 
    int referenced = 0;
2273 
    int UNUSED insn_referenced = abuf->written;
2274 
    INT in_sr = 0;
2275 
    INT out_dr = 0;
2276 
    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
2277 
  }
2278 
  return cycles;
2279 
#undef FLD
2280 
}
2281 
 
2282 
static int
2283 
model_m32r_d_clrpsw (SIM_CPU *current_cpu, void *sem_arg)
2284 
{
2285 
#define FLD(f) abuf->fields.sfmt_clrpsw.f
2286 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2287 
  const IDESC * UNUSED idesc = abuf->idesc;
2288 
  int cycles = 0;
2289 
  {
2290 
    int referenced = 0;
2291 
    int UNUSED insn_referenced = abuf->written;
2292 
    INT in_sr = -1;
2293 
    INT in_dr = -1;
2294 
    INT out_dr = -1;
2295 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2296 
  }
2297 
  return cycles;
2298 
#undef FLD
2299 
}
2300 
 
2301 
static int
2302 
model_m32r_d_setpsw (SIM_CPU *current_cpu, void *sem_arg)
2303 
{
2304 
#define FLD(f) abuf->fields.sfmt_clrpsw.f
2305 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2306 
  const IDESC * UNUSED idesc = abuf->idesc;
2307 
  int cycles = 0;
2308 
  {
2309 
    int referenced = 0;
2310 
    int UNUSED insn_referenced = abuf->written;
2311 
    INT in_sr = -1;
2312 
    INT in_dr = -1;
2313 
    INT out_dr = -1;
2314 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2315 
  }
2316 
  return cycles;
2317 
#undef FLD
2318 
}
2319 
 
2320 
static int
2321 
model_m32r_d_bset (SIM_CPU *current_cpu, void *sem_arg)
2322 
{
2323 
#define FLD(f) abuf->fields.sfmt_bset.f
2324 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2325 
  const IDESC * UNUSED idesc = abuf->idesc;
2326 
  int cycles = 0;
2327 
  {
2328 
    int referenced = 0;
2329 
    int UNUSED insn_referenced = abuf->written;
2330 
    INT in_sr = -1;
2331 
    INT in_dr = -1;
2332 
    INT out_dr = -1;
2333 
    in_sr = FLD (in_sr);
2334 
    referenced |= 1 << 0;
2335 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2336 
  }
2337 
  return cycles;
2338 
#undef FLD
2339 
}
2340 
 
2341 
static int
2342 
model_m32r_d_bclr (SIM_CPU *current_cpu, void *sem_arg)
2343 
{
2344 
#define FLD(f) abuf->fields.sfmt_bset.f
2345 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2346 
  const IDESC * UNUSED idesc = abuf->idesc;
2347 
  int cycles = 0;
2348 
  {
2349 
    int referenced = 0;
2350 
    int UNUSED insn_referenced = abuf->written;
2351 
    INT in_sr = -1;
2352 
    INT in_dr = -1;
2353 
    INT out_dr = -1;
2354 
    in_sr = FLD (in_sr);
2355 
    referenced |= 1 << 0;
2356 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2357 
  }
2358 
  return cycles;
2359 
#undef FLD
2360 
}
2361 
 
2362 
static int
2363 
model_m32r_d_btst (SIM_CPU *current_cpu, void *sem_arg)
2364 
{
2365 
#define FLD(f) abuf->fields.sfmt_bset.f
2366 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2367 
  const IDESC * UNUSED idesc = abuf->idesc;
2368 
  int cycles = 0;
2369 
  {
2370 
    int referenced = 0;
2371 
    int UNUSED insn_referenced = abuf->written;
2372 
    INT in_sr = -1;
2373 
    INT in_dr = -1;
2374 
    INT out_dr = -1;
2375 
    in_sr = FLD (in_sr);
2376 
    referenced |= 1 << 0;
2377 
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2378 
  }
2379 
  return cycles;
2380 
#undef FLD
2381 
}
2382 
 
2383 
static int
2384 
model_test_add (SIM_CPU *current_cpu, void *sem_arg)
2385 
{
2386 
#define FLD(f) abuf->fields.sfmt_add.f
2387 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2388 
  const IDESC * UNUSED idesc = abuf->idesc;
2389 
  int cycles = 0;
2390 
  {
2391 
    int referenced = 0;
2392 
    int UNUSED insn_referenced = abuf->written;
2393 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2394 
  }
2395 
  return cycles;
2396 
#undef FLD
2397 
}
2398 
 
2399 
static int
2400 
model_test_add3 (SIM_CPU *current_cpu, void *sem_arg)
2401 
{
2402 
#define FLD(f) abuf->fields.sfmt_add3.f
2403 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2404 
  const IDESC * UNUSED idesc = abuf->idesc;
2405 
  int cycles = 0;
2406 
  {
2407 
    int referenced = 0;
2408 
    int UNUSED insn_referenced = abuf->written;
2409 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2410 
  }
2411 
  return cycles;
2412 
#undef FLD
2413 
}
2414 
 
2415 
static int
2416 
model_test_and (SIM_CPU *current_cpu, void *sem_arg)
2417 
{
2418 
#define FLD(f) abuf->fields.sfmt_add.f
2419 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2420 
  const IDESC * UNUSED idesc = abuf->idesc;
2421 
  int cycles = 0;
2422 
  {
2423 
    int referenced = 0;
2424 
    int UNUSED insn_referenced = abuf->written;
2425 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2426 
  }
2427 
  return cycles;
2428 
#undef FLD
2429 
}
2430 
 
2431 
static int
2432 
model_test_and3 (SIM_CPU *current_cpu, void *sem_arg)
2433 
{
2434 
#define FLD(f) abuf->fields.sfmt_and3.f
2435 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2436 
  const IDESC * UNUSED idesc = abuf->idesc;
2437 
  int cycles = 0;
2438 
  {
2439 
    int referenced = 0;
2440 
    int UNUSED insn_referenced = abuf->written;
2441 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2442 
  }
2443 
  return cycles;
2444 
#undef FLD
2445 
}
2446 
 
2447 
static int
2448 
model_test_or (SIM_CPU *current_cpu, void *sem_arg)
2449 
{
2450 
#define FLD(f) abuf->fields.sfmt_add.f
2451 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2452 
  const IDESC * UNUSED idesc = abuf->idesc;
2453 
  int cycles = 0;
2454 
  {
2455 
    int referenced = 0;
2456 
    int UNUSED insn_referenced = abuf->written;
2457 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2458 
  }
2459 
  return cycles;
2460 
#undef FLD
2461 
}
2462 
 
2463 
static int
2464 
model_test_or3 (SIM_CPU *current_cpu, void *sem_arg)
2465 
{
2466 
#define FLD(f) abuf->fields.sfmt_and3.f
2467 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2468 
  const IDESC * UNUSED idesc = abuf->idesc;
2469 
  int cycles = 0;
2470 
  {
2471 
    int referenced = 0;
2472 
    int UNUSED insn_referenced = abuf->written;
2473 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2474 
  }
2475 
  return cycles;
2476 
#undef FLD
2477 
}
2478 
 
2479 
static int
2480 
model_test_xor (SIM_CPU *current_cpu, void *sem_arg)
2481 
{
2482 
#define FLD(f) abuf->fields.sfmt_add.f
2483 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2484 
  const IDESC * UNUSED idesc = abuf->idesc;
2485 
  int cycles = 0;
2486 
  {
2487 
    int referenced = 0;
2488 
    int UNUSED insn_referenced = abuf->written;
2489 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2490 
  }
2491 
  return cycles;
2492 
#undef FLD
2493 
}
2494 
 
2495 
static int
2496 
model_test_xor3 (SIM_CPU *current_cpu, void *sem_arg)
2497 
{
2498 
#define FLD(f) abuf->fields.sfmt_and3.f
2499 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2500 
  const IDESC * UNUSED idesc = abuf->idesc;
2501 
  int cycles = 0;
2502 
  {
2503 
    int referenced = 0;
2504 
    int UNUSED insn_referenced = abuf->written;
2505 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2506 
  }
2507 
  return cycles;
2508 
#undef FLD
2509 
}
2510 
 
2511 
static int
2512 
model_test_addi (SIM_CPU *current_cpu, void *sem_arg)
2513 
{
2514 
#define FLD(f) abuf->fields.sfmt_addi.f
2515 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2516 
  const IDESC * UNUSED idesc = abuf->idesc;
2517 
  int cycles = 0;
2518 
  {
2519 
    int referenced = 0;
2520 
    int UNUSED insn_referenced = abuf->written;
2521 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2522 
  }
2523 
  return cycles;
2524 
#undef FLD
2525 
}
2526 
 
2527 
static int
2528 
model_test_addv (SIM_CPU *current_cpu, void *sem_arg)
2529 
{
2530 
#define FLD(f) abuf->fields.sfmt_add.f
2531 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2532 
  const IDESC * UNUSED idesc = abuf->idesc;
2533 
  int cycles = 0;
2534 
  {
2535 
    int referenced = 0;
2536 
    int UNUSED insn_referenced = abuf->written;
2537 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2538 
  }
2539 
  return cycles;
2540 
#undef FLD
2541 
}
2542 
 
2543 
static int
2544 
model_test_addv3 (SIM_CPU *current_cpu, void *sem_arg)
2545 
{
2546 
#define FLD(f) abuf->fields.sfmt_add3.f
2547 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2548 
  const IDESC * UNUSED idesc = abuf->idesc;
2549 
  int cycles = 0;
2550 
  {
2551 
    int referenced = 0;
2552 
    int UNUSED insn_referenced = abuf->written;
2553 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2554 
  }
2555 
  return cycles;
2556 
#undef FLD
2557 
}
2558 
 
2559 
static int
2560 
model_test_addx (SIM_CPU *current_cpu, void *sem_arg)
2561 
{
2562 
#define FLD(f) abuf->fields.sfmt_add.f
2563 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2564 
  const IDESC * UNUSED idesc = abuf->idesc;
2565 
  int cycles = 0;
2566 
  {
2567 
    int referenced = 0;
2568 
    int UNUSED insn_referenced = abuf->written;
2569 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2570 
  }
2571 
  return cycles;
2572 
#undef FLD
2573 
}
2574 
 
2575 
static int
2576 
model_test_bc8 (SIM_CPU *current_cpu, void *sem_arg)
2577 
{
2578 
#define FLD(f) abuf->fields.sfmt_bl8.f
2579 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2580 
  const IDESC * UNUSED idesc = abuf->idesc;
2581 
  int cycles = 0;
2582 
  {
2583 
    int referenced = 0;
2584 
    int UNUSED insn_referenced = abuf->written;
2585 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2586 
  }
2587 
  return cycles;
2588 
#undef FLD
2589 
}
2590 
 
2591 
static int
2592 
model_test_bc24 (SIM_CPU *current_cpu, void *sem_arg)
2593 
{
2594 
#define FLD(f) abuf->fields.sfmt_bl24.f
2595 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2596 
  const IDESC * UNUSED idesc = abuf->idesc;
2597 
  int cycles = 0;
2598 
  {
2599 
    int referenced = 0;
2600 
    int UNUSED insn_referenced = abuf->written;
2601 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2602 
  }
2603 
  return cycles;
2604 
#undef FLD
2605 
}
2606 
 
2607 
static int
2608 
model_test_beq (SIM_CPU *current_cpu, void *sem_arg)
2609 
{
2610 
#define FLD(f) abuf->fields.sfmt_beq.f
2611 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2612 
  const IDESC * UNUSED idesc = abuf->idesc;
2613 
  int cycles = 0;
2614 
  {
2615 
    int referenced = 0;
2616 
    int UNUSED insn_referenced = abuf->written;
2617 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2618 
  }
2619 
  return cycles;
2620 
#undef FLD
2621 
}
2622 
 
2623 
static int
2624 
model_test_beqz (SIM_CPU *current_cpu, void *sem_arg)
2625 
{
2626 
#define FLD(f) abuf->fields.sfmt_beq.f
2627 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2628 
  const IDESC * UNUSED idesc = abuf->idesc;
2629 
  int cycles = 0;
2630 
  {
2631 
    int referenced = 0;
2632 
    int UNUSED insn_referenced = abuf->written;
2633 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2634 
  }
2635 
  return cycles;
2636 
#undef FLD
2637 
}
2638 
 
2639 
static int
2640 
model_test_bgez (SIM_CPU *current_cpu, void *sem_arg)
2641 
{
2642 
#define FLD(f) abuf->fields.sfmt_beq.f
2643 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2644 
  const IDESC * UNUSED idesc = abuf->idesc;
2645 
  int cycles = 0;
2646 
  {
2647 
    int referenced = 0;
2648 
    int UNUSED insn_referenced = abuf->written;
2649 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2650 
  }
2651 
  return cycles;
2652 
#undef FLD
2653 
}
2654 
 
2655 
static int
2656 
model_test_bgtz (SIM_CPU *current_cpu, void *sem_arg)
2657 
{
2658 
#define FLD(f) abuf->fields.sfmt_beq.f
2659 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2660 
  const IDESC * UNUSED idesc = abuf->idesc;
2661 
  int cycles = 0;
2662 
  {
2663 
    int referenced = 0;
2664 
    int UNUSED insn_referenced = abuf->written;
2665 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2666 
  }
2667 
  return cycles;
2668 
#undef FLD
2669 
}
2670 
 
2671 
static int
2672 
model_test_blez (SIM_CPU *current_cpu, void *sem_arg)
2673 
{
2674 
#define FLD(f) abuf->fields.sfmt_beq.f
2675 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2676 
  const IDESC * UNUSED idesc = abuf->idesc;
2677 
  int cycles = 0;
2678 
  {
2679 
    int referenced = 0;
2680 
    int UNUSED insn_referenced = abuf->written;
2681 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2682 
  }
2683 
  return cycles;
2684 
#undef FLD
2685 
}
2686 
 
2687 
static int
2688 
model_test_bltz (SIM_CPU *current_cpu, void *sem_arg)
2689 
{
2690 
#define FLD(f) abuf->fields.sfmt_beq.f
2691 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2692 
  const IDESC * UNUSED idesc = abuf->idesc;
2693 
  int cycles = 0;
2694 
  {
2695 
    int referenced = 0;
2696 
    int UNUSED insn_referenced = abuf->written;
2697 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2698 
  }
2699 
  return cycles;
2700 
#undef FLD
2701 
}
2702 
 
2703 
static int
2704 
model_test_bnez (SIM_CPU *current_cpu, void *sem_arg)
2705 
{
2706 
#define FLD(f) abuf->fields.sfmt_beq.f
2707 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2708 
  const IDESC * UNUSED idesc = abuf->idesc;
2709 
  int cycles = 0;
2710 
  {
2711 
    int referenced = 0;
2712 
    int UNUSED insn_referenced = abuf->written;
2713 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2714 
  }
2715 
  return cycles;
2716 
#undef FLD
2717 
}
2718 
 
2719 
static int
2720 
model_test_bl8 (SIM_CPU *current_cpu, void *sem_arg)
2721 
{
2722 
#define FLD(f) abuf->fields.sfmt_bl8.f
2723 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2724 
  const IDESC * UNUSED idesc = abuf->idesc;
2725 
  int cycles = 0;
2726 
  {
2727 
    int referenced = 0;
2728 
    int UNUSED insn_referenced = abuf->written;
2729 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2730 
  }
2731 
  return cycles;
2732 
#undef FLD
2733 
}
2734 
 
2735 
static int
2736 
model_test_bl24 (SIM_CPU *current_cpu, void *sem_arg)
2737 
{
2738 
#define FLD(f) abuf->fields.sfmt_bl24.f
2739 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2740 
  const IDESC * UNUSED idesc = abuf->idesc;
2741 
  int cycles = 0;
2742 
  {
2743 
    int referenced = 0;
2744 
    int UNUSED insn_referenced = abuf->written;
2745 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2746 
  }
2747 
  return cycles;
2748 
#undef FLD
2749 
}
2750 
 
2751 
static int
2752 
model_test_bnc8 (SIM_CPU *current_cpu, void *sem_arg)
2753 
{
2754 
#define FLD(f) abuf->fields.sfmt_bl8.f
2755 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2756 
  const IDESC * UNUSED idesc = abuf->idesc;
2757 
  int cycles = 0;
2758 
  {
2759 
    int referenced = 0;
2760 
    int UNUSED insn_referenced = abuf->written;
2761 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2762 
  }
2763 
  return cycles;
2764 
#undef FLD
2765 
}
2766 
 
2767 
static int
2768 
model_test_bnc24 (SIM_CPU *current_cpu, void *sem_arg)
2769 
{
2770 
#define FLD(f) abuf->fields.sfmt_bl24.f
2771 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2772 
  const IDESC * UNUSED idesc = abuf->idesc;
2773 
  int cycles = 0;
2774 
  {
2775 
    int referenced = 0;
2776 
    int UNUSED insn_referenced = abuf->written;
2777 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2778 
  }
2779 
  return cycles;
2780 
#undef FLD
2781 
}
2782 
 
2783 
static int
2784 
model_test_bne (SIM_CPU *current_cpu, void *sem_arg)
2785 
{
2786 
#define FLD(f) abuf->fields.sfmt_beq.f
2787 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2788 
  const IDESC * UNUSED idesc = abuf->idesc;
2789 
  int cycles = 0;
2790 
  {
2791 
    int referenced = 0;
2792 
    int UNUSED insn_referenced = abuf->written;
2793 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2794 
  }
2795 
  return cycles;
2796 
#undef FLD
2797 
}
2798 
 
2799 
static int
2800 
model_test_bra8 (SIM_CPU *current_cpu, void *sem_arg)
2801 
{
2802 
#define FLD(f) abuf->fields.sfmt_bl8.f
2803 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2804 
  const IDESC * UNUSED idesc = abuf->idesc;
2805 
  int cycles = 0;
2806 
  {
2807 
    int referenced = 0;
2808 
    int UNUSED insn_referenced = abuf->written;
2809 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2810 
  }
2811 
  return cycles;
2812 
#undef FLD
2813 
}
2814 
 
2815 
static int
2816 
model_test_bra24 (SIM_CPU *current_cpu, void *sem_arg)
2817 
{
2818 
#define FLD(f) abuf->fields.sfmt_bl24.f
2819 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2820 
  const IDESC * UNUSED idesc = abuf->idesc;
2821 
  int cycles = 0;
2822 
  {
2823 
    int referenced = 0;
2824 
    int UNUSED insn_referenced = abuf->written;
2825 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2826 
  }
2827 
  return cycles;
2828 
#undef FLD
2829 
}
2830 
 
2831 
static int
2832 
model_test_cmp (SIM_CPU *current_cpu, void *sem_arg)
2833 
{
2834 
#define FLD(f) abuf->fields.sfmt_st_plus.f
2835 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2836 
  const IDESC * UNUSED idesc = abuf->idesc;
2837 
  int cycles = 0;
2838 
  {
2839 
    int referenced = 0;
2840 
    int UNUSED insn_referenced = abuf->written;
2841 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2842 
  }
2843 
  return cycles;
2844 
#undef FLD
2845 
}
2846 
 
2847 
static int
2848 
model_test_cmpi (SIM_CPU *current_cpu, void *sem_arg)
2849 
{
2850 
#define FLD(f) abuf->fields.sfmt_st_d.f
2851 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2852 
  const IDESC * UNUSED idesc = abuf->idesc;
2853 
  int cycles = 0;
2854 
  {
2855 
    int referenced = 0;
2856 
    int UNUSED insn_referenced = abuf->written;
2857 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2858 
  }
2859 
  return cycles;
2860 
#undef FLD
2861 
}
2862 
 
2863 
static int
2864 
model_test_cmpu (SIM_CPU *current_cpu, void *sem_arg)
2865 
{
2866 
#define FLD(f) abuf->fields.sfmt_st_plus.f
2867 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2868 
  const IDESC * UNUSED idesc = abuf->idesc;
2869 
  int cycles = 0;
2870 
  {
2871 
    int referenced = 0;
2872 
    int UNUSED insn_referenced = abuf->written;
2873 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2874 
  }
2875 
  return cycles;
2876 
#undef FLD
2877 
}
2878 
 
2879 
static int
2880 
model_test_cmpui (SIM_CPU *current_cpu, void *sem_arg)
2881 
{
2882 
#define FLD(f) abuf->fields.sfmt_st_d.f
2883 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2884 
  const IDESC * UNUSED idesc = abuf->idesc;
2885 
  int cycles = 0;
2886 
  {
2887 
    int referenced = 0;
2888 
    int UNUSED insn_referenced = abuf->written;
2889 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2890 
  }
2891 
  return cycles;
2892 
#undef FLD
2893 
}
2894 
 
2895 
static int
2896 
model_test_div (SIM_CPU *current_cpu, void *sem_arg)
2897 
{
2898 
#define FLD(f) abuf->fields.sfmt_add.f
2899 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2900 
  const IDESC * UNUSED idesc = abuf->idesc;
2901 
  int cycles = 0;
2902 
  {
2903 
    int referenced = 0;
2904 
    int UNUSED insn_referenced = abuf->written;
2905 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2906 
  }
2907 
  return cycles;
2908 
#undef FLD
2909 
}
2910 
 
2911 
static int
2912 
model_test_divu (SIM_CPU *current_cpu, void *sem_arg)
2913 
{
2914 
#define FLD(f) abuf->fields.sfmt_add.f
2915 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2916 
  const IDESC * UNUSED idesc = abuf->idesc;
2917 
  int cycles = 0;
2918 
  {
2919 
    int referenced = 0;
2920 
    int UNUSED insn_referenced = abuf->written;
2921 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2922 
  }
2923 
  return cycles;
2924 
#undef FLD
2925 
}
2926 
 
2927 
static int
2928 
model_test_rem (SIM_CPU *current_cpu, void *sem_arg)
2929 
{
2930 
#define FLD(f) abuf->fields.sfmt_add.f
2931 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2932 
  const IDESC * UNUSED idesc = abuf->idesc;
2933 
  int cycles = 0;
2934 
  {
2935 
    int referenced = 0;
2936 
    int UNUSED insn_referenced = abuf->written;
2937 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2938 
  }
2939 
  return cycles;
2940 
#undef FLD
2941 
}
2942 
 
2943 
static int
2944 
model_test_remu (SIM_CPU *current_cpu, void *sem_arg)
2945 
{
2946 
#define FLD(f) abuf->fields.sfmt_add.f
2947 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2948 
  const IDESC * UNUSED idesc = abuf->idesc;
2949 
  int cycles = 0;
2950 
  {
2951 
    int referenced = 0;
2952 
    int UNUSED insn_referenced = abuf->written;
2953 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2954 
  }
2955 
  return cycles;
2956 
#undef FLD
2957 
}
2958 
 
2959 
static int
2960 
model_test_jl (SIM_CPU *current_cpu, void *sem_arg)
2961 
{
2962 
#define FLD(f) abuf->fields.sfmt_jl.f
2963 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2964 
  const IDESC * UNUSED idesc = abuf->idesc;
2965 
  int cycles = 0;
2966 
  {
2967 
    int referenced = 0;
2968 
    int UNUSED insn_referenced = abuf->written;
2969 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2970 
  }
2971 
  return cycles;
2972 
#undef FLD
2973 
}
2974 
 
2975 
static int
2976 
model_test_jmp (SIM_CPU *current_cpu, void *sem_arg)
2977 
{
2978 
#define FLD(f) abuf->fields.sfmt_jl.f
2979 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2980 
  const IDESC * UNUSED idesc = abuf->idesc;
2981 
  int cycles = 0;
2982 
  {
2983 
    int referenced = 0;
2984 
    int UNUSED insn_referenced = abuf->written;
2985 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2986 
  }
2987 
  return cycles;
2988 
#undef FLD
2989 
}
2990 
 
2991 
static int
2992 
model_test_ld (SIM_CPU *current_cpu, void *sem_arg)
2993 
{
2994 
#define FLD(f) abuf->fields.sfmt_ld_plus.f
2995 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2996 
  const IDESC * UNUSED idesc = abuf->idesc;
2997 
  int cycles = 0;
2998 
  {
2999 
    int referenced = 0;
3000 
    int UNUSED insn_referenced = abuf->written;
3001 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3002 
  }
3003 
  return cycles;
3004 
#undef FLD
3005 
}
3006 
 
3007 
static int
3008 
model_test_ld_d (SIM_CPU *current_cpu, void *sem_arg)
3009 
{
3010 
#define FLD(f) abuf->fields.sfmt_add3.f
3011 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3012 
  const IDESC * UNUSED idesc = abuf->idesc;
3013 
  int cycles = 0;
3014 
  {
3015 
    int referenced = 0;
3016 
    int UNUSED insn_referenced = abuf->written;
3017 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3018 
  }
3019 
  return cycles;
3020 
#undef FLD
3021 
}
3022 
 
3023 
static int
3024 
model_test_ldb (SIM_CPU *current_cpu, void *sem_arg)
3025 
{
3026 
#define FLD(f) abuf->fields.sfmt_ld_plus.f
3027 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3028 
  const IDESC * UNUSED idesc = abuf->idesc;
3029 
  int cycles = 0;
3030 
  {
3031 
    int referenced = 0;
3032 
    int UNUSED insn_referenced = abuf->written;
3033 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3034 
  }
3035 
  return cycles;
3036 
#undef FLD
3037 
}
3038 
 
3039 
static int
3040 
model_test_ldb_d (SIM_CPU *current_cpu, void *sem_arg)
3041 
{
3042 
#define FLD(f) abuf->fields.sfmt_add3.f
3043 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3044 
  const IDESC * UNUSED idesc = abuf->idesc;
3045 
  int cycles = 0;
3046 
  {
3047 
    int referenced = 0;
3048 
    int UNUSED insn_referenced = abuf->written;
3049 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3050 
  }
3051 
  return cycles;
3052 
#undef FLD
3053 
}
3054 
 
3055 
static int
3056 
model_test_ldh (SIM_CPU *current_cpu, void *sem_arg)
3057 
{
3058 
#define FLD(f) abuf->fields.sfmt_ld_plus.f
3059 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3060 
  const IDESC * UNUSED idesc = abuf->idesc;
3061 
  int cycles = 0;
3062 
  {
3063 
    int referenced = 0;
3064 
    int UNUSED insn_referenced = abuf->written;
3065 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3066 
  }
3067 
  return cycles;
3068 
#undef FLD
3069 
}
3070 
 
3071 
static int
3072 
model_test_ldh_d (SIM_CPU *current_cpu, void *sem_arg)
3073 
{
3074 
#define FLD(f) abuf->fields.sfmt_add3.f
3075 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3076 
  const IDESC * UNUSED idesc = abuf->idesc;
3077 
  int cycles = 0;
3078 
  {
3079 
    int referenced = 0;
3080 
    int UNUSED insn_referenced = abuf->written;
3081 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3082 
  }
3083 
  return cycles;
3084 
#undef FLD
3085 
}
3086 
 
3087 
static int
3088 
model_test_ldub (SIM_CPU *current_cpu, void *sem_arg)
3089 
{
3090 
#define FLD(f) abuf->fields.sfmt_ld_plus.f
3091 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3092 
  const IDESC * UNUSED idesc = abuf->idesc;
3093 
  int cycles = 0;
3094 
  {
3095 
    int referenced = 0;
3096 
    int UNUSED insn_referenced = abuf->written;
3097 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3098 
  }
3099 
  return cycles;
3100 
#undef FLD
3101 
}
3102 
 
3103 
static int
3104 
model_test_ldub_d (SIM_CPU *current_cpu, void *sem_arg)
3105 
{
3106 
#define FLD(f) abuf->fields.sfmt_add3.f
3107 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3108 
  const IDESC * UNUSED idesc = abuf->idesc;
3109 
  int cycles = 0;
3110 
  {
3111 
    int referenced = 0;
3112 
    int UNUSED insn_referenced = abuf->written;
3113 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3114 
  }
3115 
  return cycles;
3116 
#undef FLD
3117 
}
3118 
 
3119 
static int
3120 
model_test_lduh (SIM_CPU *current_cpu, void *sem_arg)
3121 
{
3122 
#define FLD(f) abuf->fields.sfmt_ld_plus.f
3123 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3124 
  const IDESC * UNUSED idesc = abuf->idesc;
3125 
  int cycles = 0;
3126 
  {
3127 
    int referenced = 0;
3128 
    int UNUSED insn_referenced = abuf->written;
3129 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3130 
  }
3131 
  return cycles;
3132 
#undef FLD
3133 
}
3134 
 
3135 
static int
3136 
model_test_lduh_d (SIM_CPU *current_cpu, void *sem_arg)
3137 
{
3138 
#define FLD(f) abuf->fields.sfmt_add3.f
3139 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3140 
  const IDESC * UNUSED idesc = abuf->idesc;
3141 
  int cycles = 0;
3142 
  {
3143 
    int referenced = 0;
3144 
    int UNUSED insn_referenced = abuf->written;
3145 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3146 
  }
3147 
  return cycles;
3148 
#undef FLD
3149 
}
3150 
 
3151 
static int
3152 
model_test_ld_plus (SIM_CPU *current_cpu, void *sem_arg)
3153 
{
3154 
#define FLD(f) abuf->fields.sfmt_ld_plus.f
3155 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3156 
  const IDESC * UNUSED idesc = abuf->idesc;
3157 
  int cycles = 0;
3158 
  {
3159 
    int referenced = 0;
3160 
    int UNUSED insn_referenced = abuf->written;
3161 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3162 
  }
3163 
  return cycles;
3164 
#undef FLD
3165 
}
3166 
 
3167 
static int
3168 
model_test_ld24 (SIM_CPU *current_cpu, void *sem_arg)
3169 
{
3170 
#define FLD(f) abuf->fields.sfmt_ld24.f
3171 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3172 
  const IDESC * UNUSED idesc = abuf->idesc;
3173 
  int cycles = 0;
3174 
  {
3175 
    int referenced = 0;
3176 
    int UNUSED insn_referenced = abuf->written;
3177 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3178 
  }
3179 
  return cycles;
3180 
#undef FLD
3181 
}
3182 
 
3183 
static int
3184 
model_test_ldi8 (SIM_CPU *current_cpu, void *sem_arg)
3185 
{
3186 
#define FLD(f) abuf->fields.sfmt_addi.f
3187 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3188 
  const IDESC * UNUSED idesc = abuf->idesc;
3189 
  int cycles = 0;
3190 
  {
3191 
    int referenced = 0;
3192 
    int UNUSED insn_referenced = abuf->written;
3193 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3194 
  }
3195 
  return cycles;
3196 
#undef FLD
3197 
}
3198 
 
3199 
static int
3200 
model_test_ldi16 (SIM_CPU *current_cpu, void *sem_arg)
3201 
{
3202 
#define FLD(f) abuf->fields.sfmt_add3.f
3203 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3204 
  const IDESC * UNUSED idesc = abuf->idesc;
3205 
  int cycles = 0;
3206 
  {
3207 
    int referenced = 0;
3208 
    int UNUSED insn_referenced = abuf->written;
3209 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3210 
  }
3211 
  return cycles;
3212 
#undef FLD
3213 
}
3214 
 
3215 
static int
3216 
model_test_lock (SIM_CPU *current_cpu, void *sem_arg)
3217 
{
3218 
#define FLD(f) abuf->fields.sfmt_ld_plus.f
3219 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3220 
  const IDESC * UNUSED idesc = abuf->idesc;
3221 
  int cycles = 0;
3222 
  {
3223 
    int referenced = 0;
3224 
    int UNUSED insn_referenced = abuf->written;
3225 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3226 
  }
3227 
  return cycles;
3228 
#undef FLD
3229 
}
3230 
 
3231 
static int
3232 
model_test_machi (SIM_CPU *current_cpu, void *sem_arg)
3233 
{
3234 
#define FLD(f) abuf->fields.sfmt_st_plus.f
3235 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3236 
  const IDESC * UNUSED idesc = abuf->idesc;
3237 
  int cycles = 0;
3238 
  {
3239 
    int referenced = 0;
3240 
    int UNUSED insn_referenced = abuf->written;
3241 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3242 
  }
3243 
  return cycles;
3244 
#undef FLD
3245 
}
3246 
 
3247 
static int
3248 
model_test_maclo (SIM_CPU *current_cpu, void *sem_arg)
3249 
{
3250 
#define FLD(f) abuf->fields.sfmt_st_plus.f
3251 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3252 
  const IDESC * UNUSED idesc = abuf->idesc;
3253 
  int cycles = 0;
3254 
  {
3255 
    int referenced = 0;
3256 
    int UNUSED insn_referenced = abuf->written;
3257 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3258 
  }
3259 
  return cycles;
3260 
#undef FLD
3261 
}
3262 
 
3263 
static int
3264 
model_test_macwhi (SIM_CPU *current_cpu, void *sem_arg)
3265 
{
3266 
#define FLD(f) abuf->fields.sfmt_st_plus.f
3267 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3268 
  const IDESC * UNUSED idesc = abuf->idesc;
3269 
  int cycles = 0;
3270 
  {
3271 
    int referenced = 0;
3272 
    int UNUSED insn_referenced = abuf->written;
3273 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3274 
  }
3275 
  return cycles;
3276 
#undef FLD
3277 
}
3278 
 
3279 
static int
3280 
model_test_macwlo (SIM_CPU *current_cpu, void *sem_arg)
3281 
{
3282 
#define FLD(f) abuf->fields.sfmt_st_plus.f
3283 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3284 
  const IDESC * UNUSED idesc = abuf->idesc;
3285 
  int cycles = 0;
3286 
  {
3287 
    int referenced = 0;
3288 
    int UNUSED insn_referenced = abuf->written;
3289 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3290 
  }
3291 
  return cycles;
3292 
#undef FLD
3293 
}
3294 
 
3295 
static int
3296 
model_test_mul (SIM_CPU *current_cpu, void *sem_arg)
3297 
{
3298 
#define FLD(f) abuf->fields.sfmt_add.f
3299 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3300 
  const IDESC * UNUSED idesc = abuf->idesc;
3301 
  int cycles = 0;
3302 
  {
3303 
    int referenced = 0;
3304 
    int UNUSED insn_referenced = abuf->written;
3305 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3306 
  }
3307 
  return cycles;
3308 
#undef FLD
3309 
}
3310 
 
3311 
static int
3312 
model_test_mulhi (SIM_CPU *current_cpu, void *sem_arg)
3313 
{
3314 
#define FLD(f) abuf->fields.sfmt_st_plus.f
3315 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3316 
  const IDESC * UNUSED idesc = abuf->idesc;
3317 
  int cycles = 0;
3318 
  {
3319 
    int referenced = 0;
3320 
    int UNUSED insn_referenced = abuf->written;
3321 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3322 
  }
3323 
  return cycles;
3324 
#undef FLD
3325 
}
3326 
 
3327 
static int
3328 
model_test_mullo (SIM_CPU *current_cpu, void *sem_arg)
3329 
{
3330 
#define FLD(f) abuf->fields.sfmt_st_plus.f
3331 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3332 
  const IDESC * UNUSED idesc = abuf->idesc;
3333 
  int cycles = 0;
3334 
  {
3335 
    int referenced = 0;
3336 
    int UNUSED insn_referenced = abuf->written;
3337 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3338 
  }
3339 
  return cycles;
3340 
#undef FLD
3341 
}
3342 
 
3343 
static int
3344 
model_test_mulwhi (SIM_CPU *current_cpu, void *sem_arg)
3345 
{
3346 
#define FLD(f) abuf->fields.sfmt_st_plus.f
3347 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3348 
  const IDESC * UNUSED idesc = abuf->idesc;
3349 
  int cycles = 0;
3350 
  {
3351 
    int referenced = 0;
3352 
    int UNUSED insn_referenced = abuf->written;
3353 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3354 
  }
3355 
  return cycles;
3356 
#undef FLD
3357 
}
3358 
 
3359 
static int
3360 
model_test_mulwlo (SIM_CPU *current_cpu, void *sem_arg)
3361 
{
3362 
#define FLD(f) abuf->fields.sfmt_st_plus.f
3363 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3364 
  const IDESC * UNUSED idesc = abuf->idesc;
3365 
  int cycles = 0;
3366 
  {
3367 
    int referenced = 0;
3368 
    int UNUSED insn_referenced = abuf->written;
3369 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3370 
  }
3371 
  return cycles;
3372 
#undef FLD
3373 
}
3374 
 
3375 
static int
3376 
model_test_mv (SIM_CPU *current_cpu, void *sem_arg)
3377 
{
3378 
#define FLD(f) abuf->fields.sfmt_ld_plus.f
3379 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3380 
  const IDESC * UNUSED idesc = abuf->idesc;
3381 
  int cycles = 0;
3382 
  {
3383 
    int referenced = 0;
3384 
    int UNUSED insn_referenced = abuf->written;
3385 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3386 
  }
3387 
  return cycles;
3388 
#undef FLD
3389 
}
3390 
 
3391 
static int
3392 
model_test_mvfachi (SIM_CPU *current_cpu, void *sem_arg)
3393 
{
3394 
#define FLD(f) abuf->fields.sfmt_seth.f
3395 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3396 
  const IDESC * UNUSED idesc = abuf->idesc;
3397 
  int cycles = 0;
3398 
  {
3399 
    int referenced = 0;
3400 
    int UNUSED insn_referenced = abuf->written;
3401 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3402 
  }
3403 
  return cycles;
3404 
#undef FLD
3405 
}
3406 
 
3407 
static int
3408 
model_test_mvfaclo (SIM_CPU *current_cpu, void *sem_arg)
3409 
{
3410 
#define FLD(f) abuf->fields.sfmt_seth.f
3411 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3412 
  const IDESC * UNUSED idesc = abuf->idesc;
3413 
  int cycles = 0;
3414 
  {
3415 
    int referenced = 0;
3416 
    int UNUSED insn_referenced = abuf->written;
3417 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3418 
  }
3419 
  return cycles;
3420 
#undef FLD
3421 
}
3422 
 
3423 
static int
3424 
model_test_mvfacmi (SIM_CPU *current_cpu, void *sem_arg)
3425 
{
3426 
#define FLD(f) abuf->fields.sfmt_seth.f
3427 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3428 
  const IDESC * UNUSED idesc = abuf->idesc;
3429 
  int cycles = 0;
3430 
  {
3431 
    int referenced = 0;
3432 
    int UNUSED insn_referenced = abuf->written;
3433 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3434 
  }
3435 
  return cycles;
3436 
#undef FLD
3437 
}
3438 
 
3439 
static int
3440 
model_test_mvfc (SIM_CPU *current_cpu, void *sem_arg)
3441 
{
3442 
#define FLD(f) abuf->fields.sfmt_ld_plus.f
3443 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3444 
  const IDESC * UNUSED idesc = abuf->idesc;
3445 
  int cycles = 0;
3446 
  {
3447 
    int referenced = 0;
3448 
    int UNUSED insn_referenced = abuf->written;
3449 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3450 
  }
3451 
  return cycles;
3452 
#undef FLD
3453 
}
3454 
 
3455 
static int
3456 
model_test_mvtachi (SIM_CPU *current_cpu, void *sem_arg)
3457 
{
3458 
#define FLD(f) abuf->fields.sfmt_st_plus.f
3459 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3460 
  const IDESC * UNUSED idesc = abuf->idesc;
3461 
  int cycles = 0;
3462 
  {
3463 
    int referenced = 0;
3464 
    int UNUSED insn_referenced = abuf->written;
3465 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3466 
  }
3467 
  return cycles;
3468 
#undef FLD
3469 
}
3470 
 
3471 
static int
3472 
model_test_mvtaclo (SIM_CPU *current_cpu, void *sem_arg)
3473 
{
3474 
#define FLD(f) abuf->fields.sfmt_st_plus.f
3475 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3476 
  const IDESC * UNUSED idesc = abuf->idesc;
3477 
  int cycles = 0;
3478 
  {
3479 
    int referenced = 0;
3480 
    int UNUSED insn_referenced = abuf->written;
3481 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3482 
  }
3483 
  return cycles;
3484 
#undef FLD
3485 
}
3486 
 
3487 
static int
3488 
model_test_mvtc (SIM_CPU *current_cpu, void *sem_arg)
3489 
{
3490 
#define FLD(f) abuf->fields.sfmt_ld_plus.f
3491 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3492 
  const IDESC * UNUSED idesc = abuf->idesc;
3493 
  int cycles = 0;
3494 
  {
3495 
    int referenced = 0;
3496 
    int UNUSED insn_referenced = abuf->written;
3497 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3498 
  }
3499 
  return cycles;
3500 
#undef FLD
3501 
}
3502 
 
3503 
static int
3504 
model_test_neg (SIM_CPU *current_cpu, void *sem_arg)
3505 
{
3506 
#define FLD(f) abuf->fields.sfmt_ld_plus.f
3507 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3508 
  const IDESC * UNUSED idesc = abuf->idesc;
3509 
  int cycles = 0;
3510 
  {
3511 
    int referenced = 0;
3512 
    int UNUSED insn_referenced = abuf->written;
3513 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3514 
  }
3515 
  return cycles;
3516 
#undef FLD
3517 
}
3518 
 
3519 
static int
3520 
model_test_nop (SIM_CPU *current_cpu, void *sem_arg)
3521 
{
3522 
#define FLD(f) abuf->fields.fmt_empty.f
3523 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3524 
  const IDESC * UNUSED idesc = abuf->idesc;
3525 
  int cycles = 0;
3526 
  {
3527 
    int referenced = 0;
3528 
    int UNUSED insn_referenced = abuf->written;
3529 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3530 
  }
3531 
  return cycles;
3532 
#undef FLD
3533 
}
3534 
 
3535 
static int
3536 
model_test_not (SIM_CPU *current_cpu, void *sem_arg)
3537 
{
3538 
#define FLD(f) abuf->fields.sfmt_ld_plus.f
3539 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3540 
  const IDESC * UNUSED idesc = abuf->idesc;
3541 
  int cycles = 0;
3542 
  {
3543 
    int referenced = 0;
3544 
    int UNUSED insn_referenced = abuf->written;
3545 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3546 
  }
3547 
  return cycles;
3548 
#undef FLD
3549 
}
3550 
 
3551 
static int
3552 
model_test_rac (SIM_CPU *current_cpu, void *sem_arg)
3553 
{
3554 
#define FLD(f) abuf->fields.fmt_empty.f
3555 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3556 
  const IDESC * UNUSED idesc = abuf->idesc;
3557 
  int cycles = 0;
3558 
  {
3559 
    int referenced = 0;
3560 
    int UNUSED insn_referenced = abuf->written;
3561 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3562 
  }
3563 
  return cycles;
3564 
#undef FLD
3565 
}
3566 
 
3567 
static int
3568 
model_test_rach (SIM_CPU *current_cpu, void *sem_arg)
3569 
{
3570 
#define FLD(f) abuf->fields.fmt_empty.f
3571 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3572 
  const IDESC * UNUSED idesc = abuf->idesc;
3573 
  int cycles = 0;
3574 
  {
3575 
    int referenced = 0;
3576 
    int UNUSED insn_referenced = abuf->written;
3577 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3578 
  }
3579 
  return cycles;
3580 
#undef FLD
3581 
}
3582 
 
3583 
static int
3584 
model_test_rte (SIM_CPU *current_cpu, void *sem_arg)
3585 
{
3586 
#define FLD(f) abuf->fields.fmt_empty.f
3587 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3588 
  const IDESC * UNUSED idesc = abuf->idesc;
3589 
  int cycles = 0;
3590 
  {
3591 
    int referenced = 0;
3592 
    int UNUSED insn_referenced = abuf->written;
3593 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3594 
  }
3595 
  return cycles;
3596 
#undef FLD
3597 
}
3598 
 
3599 
static int
3600 
model_test_seth (SIM_CPU *current_cpu, void *sem_arg)
3601 
{
3602 
#define FLD(f) abuf->fields.sfmt_seth.f
3603 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3604 
  const IDESC * UNUSED idesc = abuf->idesc;
3605 
  int cycles = 0;
3606 
  {
3607 
    int referenced = 0;
3608 
    int UNUSED insn_referenced = abuf->written;
3609 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3610 
  }
3611 
  return cycles;
3612 
#undef FLD
3613 
}
3614 
 
3615 
static int
3616 
model_test_sll (SIM_CPU *current_cpu, void *sem_arg)
3617 
{
3618 
#define FLD(f) abuf->fields.sfmt_add.f
3619 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3620 
  const IDESC * UNUSED idesc = abuf->idesc;
3621 
  int cycles = 0;
3622 
  {
3623 
    int referenced = 0;
3624 
    int UNUSED insn_referenced = abuf->written;
3625 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3626 
  }
3627 
  return cycles;
3628 
#undef FLD
3629 
}
3630 
 
3631 
static int
3632 
model_test_sll3 (SIM_CPU *current_cpu, void *sem_arg)
3633 
{
3634 
#define FLD(f) abuf->fields.sfmt_add3.f
3635 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3636 
  const IDESC * UNUSED idesc = abuf->idesc;
3637 
  int cycles = 0;
3638 
  {
3639 
    int referenced = 0;
3640 
    int UNUSED insn_referenced = abuf->written;
3641 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3642 
  }
3643 
  return cycles;
3644 
#undef FLD
3645 
}
3646 
 
3647 
static int
3648 
model_test_slli (SIM_CPU *current_cpu, void *sem_arg)
3649 
{
3650 
#define FLD(f) abuf->fields.sfmt_slli.f
3651 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3652 
  const IDESC * UNUSED idesc = abuf->idesc;
3653 
  int cycles = 0;
3654 
  {
3655 
    int referenced = 0;
3656 
    int UNUSED insn_referenced = abuf->written;
3657 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3658 
  }
3659 
  return cycles;
3660 
#undef FLD
3661 
}
3662 
 
3663 
static int
3664 
model_test_sra (SIM_CPU *current_cpu, void *sem_arg)
3665 
{
3666 
#define FLD(f) abuf->fields.sfmt_add.f
3667 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3668 
  const IDESC * UNUSED idesc = abuf->idesc;
3669 
  int cycles = 0;
3670 
  {
3671 
    int referenced = 0;
3672 
    int UNUSED insn_referenced = abuf->written;
3673 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3674 
  }
3675 
  return cycles;
3676 
#undef FLD
3677 
}
3678 
 
3679 
static int
3680 
model_test_sra3 (SIM_CPU *current_cpu, void *sem_arg)
3681 
{
3682 
#define FLD(f) abuf->fields.sfmt_add3.f
3683 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3684 
  const IDESC * UNUSED idesc = abuf->idesc;
3685 
  int cycles = 0;
3686 
  {
3687 
    int referenced = 0;
3688 
    int UNUSED insn_referenced = abuf->written;
3689 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3690 
  }
3691 
  return cycles;
3692 
#undef FLD
3693 
}
3694 
 
3695 
static int
3696 
model_test_srai (SIM_CPU *current_cpu, void *sem_arg)
3697 
{
3698 
#define FLD(f) abuf->fields.sfmt_slli.f
3699 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3700 
  const IDESC * UNUSED idesc = abuf->idesc;
3701 
  int cycles = 0;
3702 
  {
3703 
    int referenced = 0;
3704 
    int UNUSED insn_referenced = abuf->written;
3705 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3706 
  }
3707 
  return cycles;
3708 
#undef FLD
3709 
}
3710 
 
3711 
static int
3712 
model_test_srl (SIM_CPU *current_cpu, void *sem_arg)
3713 
{
3714 
#define FLD(f) abuf->fields.sfmt_add.f
3715 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3716 
  const IDESC * UNUSED idesc = abuf->idesc;
3717 
  int cycles = 0;
3718 
  {
3719 
    int referenced = 0;
3720 
    int UNUSED insn_referenced = abuf->written;
3721 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3722 
  }
3723 
  return cycles;
3724 
#undef FLD
3725 
}
3726 
 
3727 
static int
3728 
model_test_srl3 (SIM_CPU *current_cpu, void *sem_arg)
3729 
{
3730 
#define FLD(f) abuf->fields.sfmt_add3.f
3731 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3732 
  const IDESC * UNUSED idesc = abuf->idesc;
3733 
  int cycles = 0;
3734 
  {
3735 
    int referenced = 0;
3736 
    int UNUSED insn_referenced = abuf->written;
3737 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3738 
  }
3739 
  return cycles;
3740 
#undef FLD
3741 
}
3742 
 
3743 
static int
3744 
model_test_srli (SIM_CPU *current_cpu, void *sem_arg)
3745 
{
3746 
#define FLD(f) abuf->fields.sfmt_slli.f
3747 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3748 
  const IDESC * UNUSED idesc = abuf->idesc;
3749 
  int cycles = 0;
3750 
  {
3751 
    int referenced = 0;
3752 
    int UNUSED insn_referenced = abuf->written;
3753 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3754 
  }
3755 
  return cycles;
3756 
#undef FLD
3757 
}
3758 
 
3759 
static int
3760 
model_test_st (SIM_CPU *current_cpu, void *sem_arg)
3761 
{
3762 
#define FLD(f) abuf->fields.sfmt_st_plus.f
3763 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3764 
  const IDESC * UNUSED idesc = abuf->idesc;
3765 
  int cycles = 0;
3766 
  {
3767 
    int referenced = 0;
3768 
    int UNUSED insn_referenced = abuf->written;
3769 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3770 
  }
3771 
  return cycles;
3772 
#undef FLD
3773 
}
3774 
 
3775 
static int
3776 
model_test_st_d (SIM_CPU *current_cpu, void *sem_arg)
3777 
{
3778 
#define FLD(f) abuf->fields.sfmt_st_d.f
3779 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3780 
  const IDESC * UNUSED idesc = abuf->idesc;
3781 
  int cycles = 0;
3782 
  {
3783 
    int referenced = 0;
3784 
    int UNUSED insn_referenced = abuf->written;
3785 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3786 
  }
3787 
  return cycles;
3788 
#undef FLD
3789 
}
3790 
 
3791 
static int
3792 
model_test_stb (SIM_CPU *current_cpu, void *sem_arg)
3793 
{
3794 
#define FLD(f) abuf->fields.sfmt_st_plus.f
3795 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3796 
  const IDESC * UNUSED idesc = abuf->idesc;
3797 
  int cycles = 0;
3798 
  {
3799 
    int referenced = 0;
3800 
    int UNUSED insn_referenced = abuf->written;
3801 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3802 
  }
3803 
  return cycles;
3804 
#undef FLD
3805 
}
3806 
 
3807 
static int
3808 
model_test_stb_d (SIM_CPU *current_cpu, void *sem_arg)
3809 
{
3810 
#define FLD(f) abuf->fields.sfmt_st_d.f
3811 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3812 
  const IDESC * UNUSED idesc = abuf->idesc;
3813 
  int cycles = 0;
3814 
  {
3815 
    int referenced = 0;
3816 
    int UNUSED insn_referenced = abuf->written;
3817 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3818 
  }
3819 
  return cycles;
3820 
#undef FLD
3821 
}
3822 
 
3823 
static int
3824 
model_test_sth (SIM_CPU *current_cpu, void *sem_arg)
3825 
{
3826 
#define FLD(f) abuf->fields.sfmt_st_plus.f
3827 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3828 
  const IDESC * UNUSED idesc = abuf->idesc;
3829 
  int cycles = 0;
3830 
  {
3831 
    int referenced = 0;
3832 
    int UNUSED insn_referenced = abuf->written;
3833 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3834 
  }
3835 
  return cycles;
3836 
#undef FLD
3837 
}
3838 
 
3839 
static int
3840 
model_test_sth_d (SIM_CPU *current_cpu, void *sem_arg)
3841 
{
3842 
#define FLD(f) abuf->fields.sfmt_st_d.f
3843 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3844 
  const IDESC * UNUSED idesc = abuf->idesc;
3845 
  int cycles = 0;
3846 
  {
3847 
    int referenced = 0;
3848 
    int UNUSED insn_referenced = abuf->written;
3849 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3850 
  }
3851 
  return cycles;
3852 
#undef FLD
3853 
}
3854 
 
3855 
static int
3856 
model_test_st_plus (SIM_CPU *current_cpu, void *sem_arg)
3857 
{
3858 
#define FLD(f) abuf->fields.sfmt_st_plus.f
3859 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3860 
  const IDESC * UNUSED idesc = abuf->idesc;
3861 
  int cycles = 0;
3862 
  {
3863 
    int referenced = 0;
3864 
    int UNUSED insn_referenced = abuf->written;
3865 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3866 
  }
3867 
  return cycles;
3868 
#undef FLD
3869 
}
3870 
 
3871 
static int
3872 
model_test_st_minus (SIM_CPU *current_cpu, void *sem_arg)
3873 
{
3874 
#define FLD(f) abuf->fields.sfmt_st_plus.f
3875 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3876 
  const IDESC * UNUSED idesc = abuf->idesc;
3877 
  int cycles = 0;
3878 
  {
3879 
    int referenced = 0;
3880 
    int UNUSED insn_referenced = abuf->written;
3881 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3882 
  }
3883 
  return cycles;
3884 
#undef FLD
3885 
}
3886 
 
3887 
static int
3888 
model_test_sub (SIM_CPU *current_cpu, void *sem_arg)
3889 
{
3890 
#define FLD(f) abuf->fields.sfmt_add.f
3891 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3892 
  const IDESC * UNUSED idesc = abuf->idesc;
3893 
  int cycles = 0;
3894 
  {
3895 
    int referenced = 0;
3896 
    int UNUSED insn_referenced = abuf->written;
3897 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3898 
  }
3899 
  return cycles;
3900 
#undef FLD
3901 
}
3902 
 
3903 
static int
3904 
model_test_subv (SIM_CPU *current_cpu, void *sem_arg)
3905 
{
3906 
#define FLD(f) abuf->fields.sfmt_add.f
3907 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3908 
  const IDESC * UNUSED idesc = abuf->idesc;
3909 
  int cycles = 0;
3910 
  {
3911 
    int referenced = 0;
3912 
    int UNUSED insn_referenced = abuf->written;
3913 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3914 
  }
3915 
  return cycles;
3916 
#undef FLD
3917 
}
3918 
 
3919 
static int
3920 
model_test_subx (SIM_CPU *current_cpu, void *sem_arg)
3921 
{
3922 
#define FLD(f) abuf->fields.sfmt_add.f
3923 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3924 
  const IDESC * UNUSED idesc = abuf->idesc;
3925 
  int cycles = 0;
3926 
  {
3927 
    int referenced = 0;
3928 
    int UNUSED insn_referenced = abuf->written;
3929 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3930 
  }
3931 
  return cycles;
3932 
#undef FLD
3933 
}
3934 
 
3935 
static int
3936 
model_test_trap (SIM_CPU *current_cpu, void *sem_arg)
3937 
{
3938 
#define FLD(f) abuf->fields.sfmt_trap.f
3939 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3940 
  const IDESC * UNUSED idesc = abuf->idesc;
3941 
  int cycles = 0;
3942 
  {
3943 
    int referenced = 0;
3944 
    int UNUSED insn_referenced = abuf->written;
3945 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3946 
  }
3947 
  return cycles;
3948 
#undef FLD
3949 
}
3950 
 
3951 
static int
3952 
model_test_unlock (SIM_CPU *current_cpu, void *sem_arg)
3953 
{
3954 
#define FLD(f) abuf->fields.sfmt_st_plus.f
3955 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3956 
  const IDESC * UNUSED idesc = abuf->idesc;
3957 
  int cycles = 0;
3958 
  {
3959 
    int referenced = 0;
3960 
    int UNUSED insn_referenced = abuf->written;
3961 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3962 
  }
3963 
  return cycles;
3964 
#undef FLD
3965 
}
3966 
 
3967 
static int
3968 
model_test_clrpsw (SIM_CPU *current_cpu, void *sem_arg)
3969 
{
3970 
#define FLD(f) abuf->fields.sfmt_clrpsw.f
3971 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3972 
  const IDESC * UNUSED idesc = abuf->idesc;
3973 
  int cycles = 0;
3974 
  {
3975 
    int referenced = 0;
3976 
    int UNUSED insn_referenced = abuf->written;
3977 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3978 
  }
3979 
  return cycles;
3980 
#undef FLD
3981 
}
3982 
 
3983 
static int
3984 
model_test_setpsw (SIM_CPU *current_cpu, void *sem_arg)
3985 
{
3986 
#define FLD(f) abuf->fields.sfmt_clrpsw.f
3987 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3988 
  const IDESC * UNUSED idesc = abuf->idesc;
3989 
  int cycles = 0;
3990 
  {
3991 
    int referenced = 0;
3992 
    int UNUSED insn_referenced = abuf->written;
3993 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3994 
  }
3995 
  return cycles;
3996 
#undef FLD
3997 
}
3998 
 
3999 
static int
4000 
model_test_bset (SIM_CPU *current_cpu, void *sem_arg)
4001 
{
4002 
#define FLD(f) abuf->fields.sfmt_bset.f
4003 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
4004 
  const IDESC * UNUSED idesc = abuf->idesc;
4005 
  int cycles = 0;
4006 
  {
4007 
    int referenced = 0;
4008 
    int UNUSED insn_referenced = abuf->written;
4009 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
4010 
  }
4011 
  return cycles;
4012 
#undef FLD
4013 
}
4014 
 
4015 
static int
4016 
model_test_bclr (SIM_CPU *current_cpu, void *sem_arg)
4017 
{
4018 
#define FLD(f) abuf->fields.sfmt_bset.f
4019 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
4020 
  const IDESC * UNUSED idesc = abuf->idesc;
4021 
  int cycles = 0;
4022 
  {
4023 
    int referenced = 0;
4024 
    int UNUSED insn_referenced = abuf->written;
4025 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
4026 
  }
4027 
  return cycles;
4028 
#undef FLD
4029 
}
4030 
 
4031 
static int
4032 
model_test_btst (SIM_CPU *current_cpu, void *sem_arg)
4033 
{
4034 
#define FLD(f) abuf->fields.sfmt_bset.f
4035 
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
4036 
  const IDESC * UNUSED idesc = abuf->idesc;
4037 
  int cycles = 0;
4038 
  {
4039 
    int referenced = 0;
4040 
    int UNUSED insn_referenced = abuf->written;
4041 
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
4042 
  }
4043 
  return cycles;
4044 
#undef FLD
4045 
}
4046 
 
4047 
/* We assume UNIT_NONE == 0 because the tables don't always terminate
4048 
   entries with it.  */
4049 
 
4050 
/* Model timing data for `m32r/d'.  */
4051 
 
4052 
static const INSN_TIMING m32r_d_timing[] = {
4053 
  { M32RBF_INSN_X_INVALID, 0, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4054 
  { M32RBF_INSN_X_AFTER, 0, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4055 
  { M32RBF_INSN_X_BEFORE, 0, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4056 
  { M32RBF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4057 
  { M32RBF_INSN_X_CHAIN, 0, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4058 
  { M32RBF_INSN_X_BEGIN, 0, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4059 
  { M32RBF_INSN_ADD, model_m32r_d_add, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4060 
  { M32RBF_INSN_ADD3, model_m32r_d_add3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4061 
  { M32RBF_INSN_AND, model_m32r_d_and, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4062 
  { M32RBF_INSN_AND3, model_m32r_d_and3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4063 
  { M32RBF_INSN_OR, model_m32r_d_or, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4064 
  { M32RBF_INSN_OR3, model_m32r_d_or3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4065 
  { M32RBF_INSN_XOR, model_m32r_d_xor, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4066 
  { M32RBF_INSN_XOR3, model_m32r_d_xor3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4067 
  { M32RBF_INSN_ADDI, model_m32r_d_addi, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4068 
  { M32RBF_INSN_ADDV, model_m32r_d_addv, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4069 
  { M32RBF_INSN_ADDV3, model_m32r_d_addv3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4070 
  { M32RBF_INSN_ADDX, model_m32r_d_addx, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4071 
  { M32RBF_INSN_BC8, model_m32r_d_bc8, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
4072 
  { M32RBF_INSN_BC24, model_m32r_d_bc24, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
4073 
  { M32RBF_INSN_BEQ, model_m32r_d_beq, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
4074 
  { M32RBF_INSN_BEQZ, model_m32r_d_beqz, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
4075 
  { M32RBF_INSN_BGEZ, model_m32r_d_bgez, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
4076 
  { M32RBF_INSN_BGTZ, model_m32r_d_bgtz, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
4077 
  { M32RBF_INSN_BLEZ, model_m32r_d_blez, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
4078 
  { M32RBF_INSN_BLTZ, model_m32r_d_bltz, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
4079 
  { M32RBF_INSN_BNEZ, model_m32r_d_bnez, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
4080 
  { M32RBF_INSN_BL8, model_m32r_d_bl8, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
4081 
  { M32RBF_INSN_BL24, model_m32r_d_bl24, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
4082 
  { M32RBF_INSN_BNC8, model_m32r_d_bnc8, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
4083 
  { M32RBF_INSN_BNC24, model_m32r_d_bnc24, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
4084 
  { M32RBF_INSN_BNE, model_m32r_d_bne, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
4085 
  { M32RBF_INSN_BRA8, model_m32r_d_bra8, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
4086 
  { M32RBF_INSN_BRA24, model_m32r_d_bra24, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
4087 
  { M32RBF_INSN_CMP, model_m32r_d_cmp, { { (int) UNIT_M32R_D_U_CMP, 1, 1 } } },
4088 
  { M32RBF_INSN_CMPI, model_m32r_d_cmpi, { { (int) UNIT_M32R_D_U_CMP, 1, 1 } } },
4089 
  { M32RBF_INSN_CMPU, model_m32r_d_cmpu, { { (int) UNIT_M32R_D_U_CMP, 1, 1 } } },
4090 
  { M32RBF_INSN_CMPUI, model_m32r_d_cmpui, { { (int) UNIT_M32R_D_U_CMP, 1, 1 } } },
4091 
  { M32RBF_INSN_DIV, model_m32r_d_div, { { (int) UNIT_M32R_D_U_EXEC, 1, 37 } } },
4092 
  { M32RBF_INSN_DIVU, model_m32r_d_divu, { { (int) UNIT_M32R_D_U_EXEC, 1, 37 } } },
4093 
  { M32RBF_INSN_REM, model_m32r_d_rem, { { (int) UNIT_M32R_D_U_EXEC, 1, 37 } } },
4094 
  { M32RBF_INSN_REMU, model_m32r_d_remu, { { (int) UNIT_M32R_D_U_EXEC, 1, 37 } } },
4095 
  { M32RBF_INSN_JL, model_m32r_d_jl, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
4096 
  { M32RBF_INSN_JMP, model_m32r_d_jmp, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
4097 
  { M32RBF_INSN_LD, model_m32r_d_ld, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
4098 
  { M32RBF_INSN_LD_D, model_m32r_d_ld_d, { { (int) UNIT_M32R_D_U_LOAD, 1, 2 } } },
4099 
  { M32RBF_INSN_LDB, model_m32r_d_ldb, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
4100 
  { M32RBF_INSN_LDB_D, model_m32r_d_ldb_d, { { (int) UNIT_M32R_D_U_LOAD, 1, 2 } } },
4101 
  { M32RBF_INSN_LDH, model_m32r_d_ldh, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
4102 
  { M32RBF_INSN_LDH_D, model_m32r_d_ldh_d, { { (int) UNIT_M32R_D_U_LOAD, 1, 2 } } },
4103 
  { M32RBF_INSN_LDUB, model_m32r_d_ldub, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
4104 
  { M32RBF_INSN_LDUB_D, model_m32r_d_ldub_d, { { (int) UNIT_M32R_D_U_LOAD, 1, 2 } } },
4105 
  { M32RBF_INSN_LDUH, model_m32r_d_lduh, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
4106 
  { M32RBF_INSN_LDUH_D, model_m32r_d_lduh_d, { { (int) UNIT_M32R_D_U_LOAD, 1, 2 } } },
4107 
  { M32RBF_INSN_LD_PLUS, model_m32r_d_ld_plus, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 }, { (int) UNIT_M32R_D_U_EXEC, 1, 0 } } },
4108 
  { M32RBF_INSN_LD24, model_m32r_d_ld24, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4109 
  { M32RBF_INSN_LDI8, model_m32r_d_ldi8, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4110 
  { M32RBF_INSN_LDI16, model_m32r_d_ldi16, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4111 
  { M32RBF_INSN_LOCK, model_m32r_d_lock, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
4112 
  { M32RBF_INSN_MACHI, model_m32r_d_machi, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
4113 
  { M32RBF_INSN_MACLO, model_m32r_d_maclo, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
4114 
  { M32RBF_INSN_MACWHI, model_m32r_d_macwhi, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
4115 
  { M32RBF_INSN_MACWLO, model_m32r_d_macwlo, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
4116 
  { M32RBF_INSN_MUL, model_m32r_d_mul, { { (int) UNIT_M32R_D_U_EXEC, 1, 4 } } },
4117 
  { M32RBF_INSN_MULHI, model_m32r_d_mulhi, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
4118 
  { M32RBF_INSN_MULLO, model_m32r_d_mullo, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
4119 
  { M32RBF_INSN_MULWHI, model_m32r_d_mulwhi, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
4120 
  { M32RBF_INSN_MULWLO, model_m32r_d_mulwlo, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
4121 
  { M32RBF_INSN_MV, model_m32r_d_mv, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4122 
  { M32RBF_INSN_MVFACHI, model_m32r_d_mvfachi, { { (int) UNIT_M32R_D_U_EXEC, 1, 2 } } },
4123 
  { M32RBF_INSN_MVFACLO, model_m32r_d_mvfaclo, { { (int) UNIT_M32R_D_U_EXEC, 1, 2 } } },
4124 
  { M32RBF_INSN_MVFACMI, model_m32r_d_mvfacmi, { { (int) UNIT_M32R_D_U_EXEC, 1, 2 } } },
4125 
  { M32RBF_INSN_MVFC, model_m32r_d_mvfc, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4126 
  { M32RBF_INSN_MVTACHI, model_m32r_d_mvtachi, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4127 
  { M32RBF_INSN_MVTACLO, model_m32r_d_mvtaclo, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4128 
  { M32RBF_INSN_MVTC, model_m32r_d_mvtc, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4129 
  { M32RBF_INSN_NEG, model_m32r_d_neg, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4130 
  { M32RBF_INSN_NOP, model_m32r_d_nop, { { (int) UNIT_M32R_D_U_EXEC, 1, 0 } } },
4131 
  { M32RBF_INSN_NOT, model_m32r_d_not, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4132 
  { M32RBF_INSN_RAC, model_m32r_d_rac, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
4133 
  { M32RBF_INSN_RACH, model_m32r_d_rach, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
4134 
  { M32RBF_INSN_RTE, model_m32r_d_rte, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4135 
  { M32RBF_INSN_SETH, model_m32r_d_seth, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4136 
  { M32RBF_INSN_SLL, model_m32r_d_sll, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4137 
  { M32RBF_INSN_SLL3, model_m32r_d_sll3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4138 
  { M32RBF_INSN_SLLI, model_m32r_d_slli, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4139 
  { M32RBF_INSN_SRA, model_m32r_d_sra, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4140 
  { M32RBF_INSN_SRA3, model_m32r_d_sra3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4141 
  { M32RBF_INSN_SRAI, model_m32r_d_srai, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4142 
  { M32RBF_INSN_SRL, model_m32r_d_srl, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4143 
  { M32RBF_INSN_SRL3, model_m32r_d_srl3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4144 
  { M32RBF_INSN_SRLI, model_m32r_d_srli, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4145 
  { M32RBF_INSN_ST, model_m32r_d_st, { { (int) UNIT_M32R_D_U_STORE, 1, 1 } } },
4146 
  { M32RBF_INSN_ST_D, model_m32r_d_st_d, { { (int) UNIT_M32R_D_U_STORE, 1, 2 } } },
4147 
  { M32RBF_INSN_STB, model_m32r_d_stb, { { (int) UNIT_M32R_D_U_STORE, 1, 1 } } },
4148 
  { M32RBF_INSN_STB_D, model_m32r_d_stb_d, { { (int) UNIT_M32R_D_U_STORE, 1, 2 } } },
4149 
  { M32RBF_INSN_STH, model_m32r_d_sth, { { (int) UNIT_M32R_D_U_STORE, 1, 1 } } },
4150 
  { M32RBF_INSN_STH_D, model_m32r_d_sth_d, { { (int) UNIT_M32R_D_U_STORE, 1, 2 } } },
4151 
  { M32RBF_INSN_ST_PLUS, model_m32r_d_st_plus, { { (int) UNIT_M32R_D_U_STORE, 1, 1 }, { (int) UNIT_M32R_D_U_EXEC, 1, 0 } } },
4152 
  { M32RBF_INSN_ST_MINUS, model_m32r_d_st_minus, { { (int) UNIT_M32R_D_U_STORE, 1, 1 }, { (int) UNIT_M32R_D_U_EXEC, 1, 0 } } },
4153 
  { M32RBF_INSN_SUB, model_m32r_d_sub, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4154 
  { M32RBF_INSN_SUBV, model_m32r_d_subv, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4155 
  { M32RBF_INSN_SUBX, model_m32r_d_subx, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4156 
  { M32RBF_INSN_TRAP, model_m32r_d_trap, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4157 
  { M32RBF_INSN_UNLOCK, model_m32r_d_unlock, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
4158 
  { M32RBF_INSN_CLRPSW, model_m32r_d_clrpsw, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4159 
  { M32RBF_INSN_SETPSW, model_m32r_d_setpsw, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4160 
  { M32RBF_INSN_BSET, model_m32r_d_bset, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4161 
  { M32RBF_INSN_BCLR, model_m32r_d_bclr, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4162 
  { M32RBF_INSN_BTST, model_m32r_d_btst, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4163 
};
4164 
 
4165 
/* Model timing data for `test'.  */
4166 
 
4167 
static const INSN_TIMING test_timing[] = {
4168 
  { M32RBF_INSN_X_INVALID, 0, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4169 
  { M32RBF_INSN_X_AFTER, 0, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4170 
  { M32RBF_INSN_X_BEFORE, 0, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4171 
  { M32RBF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4172 
  { M32RBF_INSN_X_CHAIN, 0, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4173 
  { M32RBF_INSN_X_BEGIN, 0, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4174 
  { M32RBF_INSN_ADD, model_test_add, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4175 
  { M32RBF_INSN_ADD3, model_test_add3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4176 
  { M32RBF_INSN_AND, model_test_and, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4177 
  { M32RBF_INSN_AND3, model_test_and3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4178 
  { M32RBF_INSN_OR, model_test_or, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4179 
  { M32RBF_INSN_OR3, model_test_or3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4180 
  { M32RBF_INSN_XOR, model_test_xor, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4181 
  { M32RBF_INSN_XOR3, model_test_xor3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4182 
  { M32RBF_INSN_ADDI, model_test_addi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4183 
  { M32RBF_INSN_ADDV, model_test_addv, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4184 
  { M32RBF_INSN_ADDV3, model_test_addv3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4185 
  { M32RBF_INSN_ADDX, model_test_addx, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4186 
  { M32RBF_INSN_BC8, model_test_bc8, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4187 
  { M32RBF_INSN_BC24, model_test_bc24, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4188 
  { M32RBF_INSN_BEQ, model_test_beq, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4189 
  { M32RBF_INSN_BEQZ, model_test_beqz, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4190 
  { M32RBF_INSN_BGEZ, model_test_bgez, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4191 
  { M32RBF_INSN_BGTZ, model_test_bgtz, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4192 
  { M32RBF_INSN_BLEZ, model_test_blez, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4193 
  { M32RBF_INSN_BLTZ, model_test_bltz, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4194 
  { M32RBF_INSN_BNEZ, model_test_bnez, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4195 
  { M32RBF_INSN_BL8, model_test_bl8, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4196 
  { M32RBF_INSN_BL24, model_test_bl24, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4197 
  { M32RBF_INSN_BNC8, model_test_bnc8, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4198 
  { M32RBF_INSN_BNC24, model_test_bnc24, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4199 
  { M32RBF_INSN_BNE, model_test_bne, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4200 
  { M32RBF_INSN_BRA8, model_test_bra8, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4201 
  { M32RBF_INSN_BRA24, model_test_bra24, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4202 
  { M32RBF_INSN_CMP, model_test_cmp, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4203 
  { M32RBF_INSN_CMPI, model_test_cmpi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4204 
  { M32RBF_INSN_CMPU, model_test_cmpu, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4205 
  { M32RBF_INSN_CMPUI, model_test_cmpui, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4206 
  { M32RBF_INSN_DIV, model_test_div, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4207 
  { M32RBF_INSN_DIVU, model_test_divu, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4208 
  { M32RBF_INSN_REM, model_test_rem, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4209 
  { M32RBF_INSN_REMU, model_test_remu, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4210 
  { M32RBF_INSN_JL, model_test_jl, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4211 
  { M32RBF_INSN_JMP, model_test_jmp, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4212 
  { M32RBF_INSN_LD, model_test_ld, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4213 
  { M32RBF_INSN_LD_D, model_test_ld_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4214 
  { M32RBF_INSN_LDB, model_test_ldb, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4215 
  { M32RBF_INSN_LDB_D, model_test_ldb_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4216 
  { M32RBF_INSN_LDH, model_test_ldh, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4217 
  { M32RBF_INSN_LDH_D, model_test_ldh_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4218 
  { M32RBF_INSN_LDUB, model_test_ldub, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4219 
  { M32RBF_INSN_LDUB_D, model_test_ldub_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4220 
  { M32RBF_INSN_LDUH, model_test_lduh, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4221 
  { M32RBF_INSN_LDUH_D, model_test_lduh_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4222 
  { M32RBF_INSN_LD_PLUS, model_test_ld_plus, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4223 
  { M32RBF_INSN_LD24, model_test_ld24, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4224 
  { M32RBF_INSN_LDI8, model_test_ldi8, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4225 
  { M32RBF_INSN_LDI16, model_test_ldi16, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4226 
  { M32RBF_INSN_LOCK, model_test_lock, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4227 
  { M32RBF_INSN_MACHI, model_test_machi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4228 
  { M32RBF_INSN_MACLO, model_test_maclo, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4229 
  { M32RBF_INSN_MACWHI, model_test_macwhi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4230 
  { M32RBF_INSN_MACWLO, model_test_macwlo, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4231 
  { M32RBF_INSN_MUL, model_test_mul, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4232 
  { M32RBF_INSN_MULHI, model_test_mulhi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4233 
  { M32RBF_INSN_MULLO, model_test_mullo, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4234 
  { M32RBF_INSN_MULWHI, model_test_mulwhi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4235 
  { M32RBF_INSN_MULWLO, model_test_mulwlo, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4236 
  { M32RBF_INSN_MV, model_test_mv, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4237 
  { M32RBF_INSN_MVFACHI, model_test_mvfachi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4238 
  { M32RBF_INSN_MVFACLO, model_test_mvfaclo, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4239 
  { M32RBF_INSN_MVFACMI, model_test_mvfacmi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4240 
  { M32RBF_INSN_MVFC, model_test_mvfc, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4241 
  { M32RBF_INSN_MVTACHI, model_test_mvtachi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4242 
  { M32RBF_INSN_MVTACLO, model_test_mvtaclo, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4243 
  { M32RBF_INSN_MVTC, model_test_mvtc, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4244 
  { M32RBF_INSN_NEG, model_test_neg, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4245 
  { M32RBF_INSN_NOP, model_test_nop, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4246 
  { M32RBF_INSN_NOT, model_test_not, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4247 
  { M32RBF_INSN_RAC, model_test_rac, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4248 
  { M32RBF_INSN_RACH, model_test_rach, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4249 
  { M32RBF_INSN_RTE, model_test_rte, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4250 
  { M32RBF_INSN_SETH, model_test_seth, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4251 
  { M32RBF_INSN_SLL, model_test_sll, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4252 
  { M32RBF_INSN_SLL3, model_test_sll3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4253 
  { M32RBF_INSN_SLLI, model_test_slli, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4254 
  { M32RBF_INSN_SRA, model_test_sra, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4255 
  { M32RBF_INSN_SRA3, model_test_sra3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4256 
  { M32RBF_INSN_SRAI, model_test_srai, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4257 
  { M32RBF_INSN_SRL, model_test_srl, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4258 
  { M32RBF_INSN_SRL3, model_test_srl3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4259 
  { M32RBF_INSN_SRLI, model_test_srli, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4260 
  { M32RBF_INSN_ST, model_test_st, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4261 
  { M32RBF_INSN_ST_D, model_test_st_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4262 
  { M32RBF_INSN_STB, model_test_stb, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4263 
  { M32RBF_INSN_STB_D, model_test_stb_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4264 
  { M32RBF_INSN_STH, model_test_sth, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4265 
  { M32RBF_INSN_STH_D, model_test_sth_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4266 
  { M32RBF_INSN_ST_PLUS, model_test_st_plus, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4267 
  { M32RBF_INSN_ST_MINUS, model_test_st_minus, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4268 
  { M32RBF_INSN_SUB, model_test_sub, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4269 
  { M32RBF_INSN_SUBV, model_test_subv, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4270 
  { M32RBF_INSN_SUBX, model_test_subx, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4271 
  { M32RBF_INSN_TRAP, model_test_trap, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4272 
  { M32RBF_INSN_UNLOCK, model_test_unlock, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4273 
  { M32RBF_INSN_CLRPSW, model_test_clrpsw, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4274 
  { M32RBF_INSN_SETPSW, model_test_setpsw, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4275 
  { M32RBF_INSN_BSET, model_test_bset, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4276 
  { M32RBF_INSN_BCLR, model_test_bclr, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4277 
  { M32RBF_INSN_BTST, model_test_btst, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4278 
};
4279 
 
4280 
#endif /* WITH_PROFILE_MODEL_P */
4281 
 
4282 
static void
4283 
m32r_d_model_init (SIM_CPU *cpu)
4284 
{
4285 
  CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_M32R_D_DATA));
4286 
}
4287 
 
4288 
static void
4289 
test_model_init (SIM_CPU *cpu)
4290 
{
4291 
  CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_TEST_DATA));
4292 
}
4293 
 
4294 
#if WITH_PROFILE_MODEL_P
4295 
#define TIMING_DATA(td) td
4296 
#else
4297 
#define TIMING_DATA(td) 0
4298 
#endif
4299 
 
4300 
static const MODEL m32r_models[] =
4301 
{
4302 
  { "m32r/d", & m32r_mach, MODEL_M32R_D, TIMING_DATA (& m32r_d_timing[0]), m32r_d_model_init },
4303 
  { "test", & m32r_mach, MODEL_TEST, TIMING_DATA (& test_timing[0]), test_model_init },
4304 
  { 0 }
4305 
};
4306 
 
4307 
/* The properties of this cpu's implementation.  */
4308 
 
4309 
static const MACH_IMP_PROPERTIES m32rbf_imp_properties =
4310 
{
4311 
  sizeof (SIM_CPU),
4312 
#if WITH_SCACHE
4313 
  sizeof (SCACHE)
4314 
#else
4315 
 
4316 
#endif
4317 
};
4318 
 
4319 
 
4320 
static void
4321 
m32rbf_prepare_run (SIM_CPU *cpu)
4322 
{
4323 
  if (CPU_IDESC (cpu) == NULL)
4324 
    m32rbf_init_idesc_table (cpu);
4325 
}
4326 
 
4327 
static const CGEN_INSN *
4328 
m32rbf_get_idata (SIM_CPU *cpu, int inum)
4329 
{
4330 
  return CPU_IDESC (cpu) [inum].idata;
4331 
}
4332 
 
4333 
static void
4334 
m32r_init_cpu (SIM_CPU *cpu)
4335 
{
4336 
  CPU_REG_FETCH (cpu) = m32rbf_fetch_register;
4337 
  CPU_REG_STORE (cpu) = m32rbf_store_register;
4338 
  CPU_PC_FETCH (cpu) = m32rbf_h_pc_get;
4339 
  CPU_PC_STORE (cpu) = m32rbf_h_pc_set;
4340 
  CPU_GET_IDATA (cpu) = m32rbf_get_idata;
4341 
  CPU_MAX_INSNS (cpu) = M32RBF_INSN__MAX;
4342 
  CPU_INSN_NAME (cpu) = cgen_insn_name;
4343 
  CPU_FULL_ENGINE_FN (cpu) = m32rbf_engine_run_full;
4344 
#if WITH_FAST
4345 
  CPU_FAST_ENGINE_FN (cpu) = m32rbf_engine_run_fast;
4346 
#else
4347 
  CPU_FAST_ENGINE_FN (cpu) = m32rbf_engine_run_full;
4348 
#endif
4349 
}
4350 
 
4351 
const MACH m32r_mach =
4352 
{
4353 
  "m32r", "m32r", MACH_M32R,
4354 
  32, 32, & m32r_models[0], & m32rbf_imp_properties,
4355 
  m32r_init_cpu,
4356 
  m32rbf_prepare_run
4357 
};
4358 
 

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