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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [m32r/] [sem-switch.c] - Blame information for rev 438

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1 24 jeremybenn
/* Simulator instruction semantics for m32rbf.
2
 
3
THIS FILE IS MACHINE GENERATED WITH CGEN.
4
 
5
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
6
 
7
This file is part of the GNU simulators.
8
 
9
This program is free software; you can redistribute it and/or modify
10
it under the terms of the GNU General Public License as published by
11
the Free Software Foundation; either version 3 of the License, or
12
(at your option) any later version.
13
 
14
This program is distributed in the hope that it will be useful,
15
but WITHOUT ANY WARRANTY; without even the implied warranty of
16
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17
GNU General Public License for more details.
18
 
19
You should have received a copy of the GNU General Public License
20
along with this program.  If not, see <http://www.gnu.org/licenses/>.
21
 
22
*/
23
 
24
#ifdef DEFINE_LABELS
25
 
26
  /* The labels have the case they have because the enum of insn types
27
     is all uppercase and in the non-stdc case the insn symbol is built
28
     into the enum name.  */
29
 
30
  static struct {
31
    int index;
32
    void *label;
33
  } labels[] = {
34
    { M32RBF_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
35
    { M32RBF_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
36
    { M32RBF_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
37
    { M32RBF_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
38
    { M32RBF_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
39
    { M32RBF_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
40
    { M32RBF_INSN_ADD, && case_sem_INSN_ADD },
41
    { M32RBF_INSN_ADD3, && case_sem_INSN_ADD3 },
42
    { M32RBF_INSN_AND, && case_sem_INSN_AND },
43
    { M32RBF_INSN_AND3, && case_sem_INSN_AND3 },
44
    { M32RBF_INSN_OR, && case_sem_INSN_OR },
45
    { M32RBF_INSN_OR3, && case_sem_INSN_OR3 },
46
    { M32RBF_INSN_XOR, && case_sem_INSN_XOR },
47
    { M32RBF_INSN_XOR3, && case_sem_INSN_XOR3 },
48
    { M32RBF_INSN_ADDI, && case_sem_INSN_ADDI },
49
    { M32RBF_INSN_ADDV, && case_sem_INSN_ADDV },
50
    { M32RBF_INSN_ADDV3, && case_sem_INSN_ADDV3 },
51
    { M32RBF_INSN_ADDX, && case_sem_INSN_ADDX },
52
    { M32RBF_INSN_BC8, && case_sem_INSN_BC8 },
53
    { M32RBF_INSN_BC24, && case_sem_INSN_BC24 },
54
    { M32RBF_INSN_BEQ, && case_sem_INSN_BEQ },
55
    { M32RBF_INSN_BEQZ, && case_sem_INSN_BEQZ },
56
    { M32RBF_INSN_BGEZ, && case_sem_INSN_BGEZ },
57
    { M32RBF_INSN_BGTZ, && case_sem_INSN_BGTZ },
58
    { M32RBF_INSN_BLEZ, && case_sem_INSN_BLEZ },
59
    { M32RBF_INSN_BLTZ, && case_sem_INSN_BLTZ },
60
    { M32RBF_INSN_BNEZ, && case_sem_INSN_BNEZ },
61
    { M32RBF_INSN_BL8, && case_sem_INSN_BL8 },
62
    { M32RBF_INSN_BL24, && case_sem_INSN_BL24 },
63
    { M32RBF_INSN_BNC8, && case_sem_INSN_BNC8 },
64
    { M32RBF_INSN_BNC24, && case_sem_INSN_BNC24 },
65
    { M32RBF_INSN_BNE, && case_sem_INSN_BNE },
66
    { M32RBF_INSN_BRA8, && case_sem_INSN_BRA8 },
67
    { M32RBF_INSN_BRA24, && case_sem_INSN_BRA24 },
68
    { M32RBF_INSN_CMP, && case_sem_INSN_CMP },
69
    { M32RBF_INSN_CMPI, && case_sem_INSN_CMPI },
70
    { M32RBF_INSN_CMPU, && case_sem_INSN_CMPU },
71
    { M32RBF_INSN_CMPUI, && case_sem_INSN_CMPUI },
72
    { M32RBF_INSN_DIV, && case_sem_INSN_DIV },
73
    { M32RBF_INSN_DIVU, && case_sem_INSN_DIVU },
74
    { M32RBF_INSN_REM, && case_sem_INSN_REM },
75
    { M32RBF_INSN_REMU, && case_sem_INSN_REMU },
76
    { M32RBF_INSN_JL, && case_sem_INSN_JL },
77
    { M32RBF_INSN_JMP, && case_sem_INSN_JMP },
78
    { M32RBF_INSN_LD, && case_sem_INSN_LD },
79
    { M32RBF_INSN_LD_D, && case_sem_INSN_LD_D },
80
    { M32RBF_INSN_LDB, && case_sem_INSN_LDB },
81
    { M32RBF_INSN_LDB_D, && case_sem_INSN_LDB_D },
82
    { M32RBF_INSN_LDH, && case_sem_INSN_LDH },
83
    { M32RBF_INSN_LDH_D, && case_sem_INSN_LDH_D },
84
    { M32RBF_INSN_LDUB, && case_sem_INSN_LDUB },
85
    { M32RBF_INSN_LDUB_D, && case_sem_INSN_LDUB_D },
86
    { M32RBF_INSN_LDUH, && case_sem_INSN_LDUH },
87
    { M32RBF_INSN_LDUH_D, && case_sem_INSN_LDUH_D },
88
    { M32RBF_INSN_LD_PLUS, && case_sem_INSN_LD_PLUS },
89
    { M32RBF_INSN_LD24, && case_sem_INSN_LD24 },
90
    { M32RBF_INSN_LDI8, && case_sem_INSN_LDI8 },
91
    { M32RBF_INSN_LDI16, && case_sem_INSN_LDI16 },
92
    { M32RBF_INSN_LOCK, && case_sem_INSN_LOCK },
93
    { M32RBF_INSN_MACHI, && case_sem_INSN_MACHI },
94
    { M32RBF_INSN_MACLO, && case_sem_INSN_MACLO },
95
    { M32RBF_INSN_MACWHI, && case_sem_INSN_MACWHI },
96
    { M32RBF_INSN_MACWLO, && case_sem_INSN_MACWLO },
97
    { M32RBF_INSN_MUL, && case_sem_INSN_MUL },
98
    { M32RBF_INSN_MULHI, && case_sem_INSN_MULHI },
99
    { M32RBF_INSN_MULLO, && case_sem_INSN_MULLO },
100
    { M32RBF_INSN_MULWHI, && case_sem_INSN_MULWHI },
101
    { M32RBF_INSN_MULWLO, && case_sem_INSN_MULWLO },
102
    { M32RBF_INSN_MV, && case_sem_INSN_MV },
103
    { M32RBF_INSN_MVFACHI, && case_sem_INSN_MVFACHI },
104
    { M32RBF_INSN_MVFACLO, && case_sem_INSN_MVFACLO },
105
    { M32RBF_INSN_MVFACMI, && case_sem_INSN_MVFACMI },
106
    { M32RBF_INSN_MVFC, && case_sem_INSN_MVFC },
107
    { M32RBF_INSN_MVTACHI, && case_sem_INSN_MVTACHI },
108
    { M32RBF_INSN_MVTACLO, && case_sem_INSN_MVTACLO },
109
    { M32RBF_INSN_MVTC, && case_sem_INSN_MVTC },
110
    { M32RBF_INSN_NEG, && case_sem_INSN_NEG },
111
    { M32RBF_INSN_NOP, && case_sem_INSN_NOP },
112
    { M32RBF_INSN_NOT, && case_sem_INSN_NOT },
113
    { M32RBF_INSN_RAC, && case_sem_INSN_RAC },
114
    { M32RBF_INSN_RACH, && case_sem_INSN_RACH },
115
    { M32RBF_INSN_RTE, && case_sem_INSN_RTE },
116
    { M32RBF_INSN_SETH, && case_sem_INSN_SETH },
117
    { M32RBF_INSN_SLL, && case_sem_INSN_SLL },
118
    { M32RBF_INSN_SLL3, && case_sem_INSN_SLL3 },
119
    { M32RBF_INSN_SLLI, && case_sem_INSN_SLLI },
120
    { M32RBF_INSN_SRA, && case_sem_INSN_SRA },
121
    { M32RBF_INSN_SRA3, && case_sem_INSN_SRA3 },
122
    { M32RBF_INSN_SRAI, && case_sem_INSN_SRAI },
123
    { M32RBF_INSN_SRL, && case_sem_INSN_SRL },
124
    { M32RBF_INSN_SRL3, && case_sem_INSN_SRL3 },
125
    { M32RBF_INSN_SRLI, && case_sem_INSN_SRLI },
126
    { M32RBF_INSN_ST, && case_sem_INSN_ST },
127
    { M32RBF_INSN_ST_D, && case_sem_INSN_ST_D },
128
    { M32RBF_INSN_STB, && case_sem_INSN_STB },
129
    { M32RBF_INSN_STB_D, && case_sem_INSN_STB_D },
130
    { M32RBF_INSN_STH, && case_sem_INSN_STH },
131
    { M32RBF_INSN_STH_D, && case_sem_INSN_STH_D },
132
    { M32RBF_INSN_ST_PLUS, && case_sem_INSN_ST_PLUS },
133
    { M32RBF_INSN_ST_MINUS, && case_sem_INSN_ST_MINUS },
134
    { M32RBF_INSN_SUB, && case_sem_INSN_SUB },
135
    { M32RBF_INSN_SUBV, && case_sem_INSN_SUBV },
136
    { M32RBF_INSN_SUBX, && case_sem_INSN_SUBX },
137
    { M32RBF_INSN_TRAP, && case_sem_INSN_TRAP },
138
    { M32RBF_INSN_UNLOCK, && case_sem_INSN_UNLOCK },
139
    { M32RBF_INSN_CLRPSW, && case_sem_INSN_CLRPSW },
140
    { M32RBF_INSN_SETPSW, && case_sem_INSN_SETPSW },
141
    { M32RBF_INSN_BSET, && case_sem_INSN_BSET },
142
    { M32RBF_INSN_BCLR, && case_sem_INSN_BCLR },
143
    { M32RBF_INSN_BTST, && case_sem_INSN_BTST },
144
    { 0, 0 }
145
  };
146
  int i;
147
 
148
  for (i = 0; labels[i].label != 0; ++i)
149
    {
150
#if FAST_P
151
      CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
152
#else
153
      CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
154
#endif
155
    }
156
 
157
#undef DEFINE_LABELS
158
#endif /* DEFINE_LABELS */
159
 
160
#ifdef DEFINE_SWITCH
161
 
162
/* If hyper-fast [well not unnecessarily slow] execution is selected, turn
163
   off frills like tracing and profiling.  */
164
/* FIXME: A better way would be to have TRACE_RESULT check for something
165
   that can cause it to be optimized out.  Another way would be to emit
166
   special handlers into the instruction "stream".  */
167
 
168
#if FAST_P
169
#undef TRACE_RESULT
170
#define TRACE_RESULT(cpu, abuf, name, type, val)
171
#endif
172
 
173
#undef GET_ATTR
174
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
175
#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
176
#else
177
#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
178
#endif
179
 
180
{
181
 
182
#if WITH_SCACHE_PBB
183
 
184
/* Branch to next handler without going around main loop.  */
185
#define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
186
SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
187
 
188
#else /* ! WITH_SCACHE_PBB */
189
 
190
#define NEXT(vpc) BREAK (sem)
191
#ifdef __GNUC__
192
#if FAST_P
193
  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
194
#else
195
  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
196
#endif
197
#else
198
  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
199
#endif
200
 
201
#endif /* ! WITH_SCACHE_PBB */
202
 
203
    {
204
 
205
  CASE (sem, INSN_X_INVALID) : /* --invalid-- */
206
{
207
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
208
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
209
#define FLD(f) abuf->fields.fmt_empty.f
210
  int UNUSED written = 0;
211
  IADDR UNUSED pc = abuf->addr;
212
  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
213
 
214
  {
215
    /* Update the recorded pc in the cpu state struct.
216
       Only necessary for WITH_SCACHE case, but to avoid the
217
       conditional compilation ....  */
218
    SET_H_PC (pc);
219
    /* Virtual insns have zero size.  Overwrite vpc with address of next insn
220
       using the default-insn-bitsize spec.  When executing insns in parallel
221
       we may want to queue the fault and continue execution.  */
222
    vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
223
    vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
224
  }
225
 
226
#undef FLD
227
}
228
  NEXT (vpc);
229
 
230
  CASE (sem, INSN_X_AFTER) : /* --after-- */
231
{
232
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
233
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
234
#define FLD(f) abuf->fields.fmt_empty.f
235
  int UNUSED written = 0;
236
  IADDR UNUSED pc = abuf->addr;
237
  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
238
 
239
  {
240
#if WITH_SCACHE_PBB_M32RBF
241
    m32rbf_pbb_after (current_cpu, sem_arg);
242
#endif
243
  }
244
 
245
#undef FLD
246
}
247
  NEXT (vpc);
248
 
249
  CASE (sem, INSN_X_BEFORE) : /* --before-- */
250
{
251
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
252
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
253
#define FLD(f) abuf->fields.fmt_empty.f
254
  int UNUSED written = 0;
255
  IADDR UNUSED pc = abuf->addr;
256
  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
257
 
258
  {
259
#if WITH_SCACHE_PBB_M32RBF
260
    m32rbf_pbb_before (current_cpu, sem_arg);
261
#endif
262
  }
263
 
264
#undef FLD
265
}
266
  NEXT (vpc);
267
 
268
  CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
269
{
270
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
271
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
272
#define FLD(f) abuf->fields.fmt_empty.f
273
  int UNUSED written = 0;
274
  IADDR UNUSED pc = abuf->addr;
275
  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
276
 
277
  {
278
#if WITH_SCACHE_PBB_M32RBF
279
#ifdef DEFINE_SWITCH
280
    vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg,
281
                               pbb_br_type, pbb_br_npc);
282
    BREAK (sem);
283
#else
284
    /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */
285
    vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg,
286
                               CPU_PBB_BR_TYPE (current_cpu),
287
                               CPU_PBB_BR_NPC (current_cpu));
288
#endif
289
#endif
290
  }
291
 
292
#undef FLD
293
}
294
  NEXT (vpc);
295
 
296
  CASE (sem, INSN_X_CHAIN) : /* --chain-- */
297
{
298
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
299
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
300
#define FLD(f) abuf->fields.fmt_empty.f
301
  int UNUSED written = 0;
302
  IADDR UNUSED pc = abuf->addr;
303
  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
304
 
305
  {
306
#if WITH_SCACHE_PBB_M32RBF
307
    vpc = m32rbf_pbb_chain (current_cpu, sem_arg);
308
#ifdef DEFINE_SWITCH
309
    BREAK (sem);
310
#endif
311
#endif
312
  }
313
 
314
#undef FLD
315
}
316
  NEXT (vpc);
317
 
318
  CASE (sem, INSN_X_BEGIN) : /* --begin-- */
319
{
320
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
321
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
322
#define FLD(f) abuf->fields.fmt_empty.f
323
  int UNUSED written = 0;
324
  IADDR UNUSED pc = abuf->addr;
325
  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
326
 
327
  {
328
#if WITH_SCACHE_PBB_M32RBF
329
#if defined DEFINE_SWITCH || defined FAST_P
330
    /* In the switch case FAST_P is a constant, allowing several optimizations
331
       in any called inline functions.  */
332
    vpc = m32rbf_pbb_begin (current_cpu, FAST_P);
333
#else
334
#if 0 /* cgen engine can't handle dynamic fast/full switching yet.  */
335
    vpc = m32rbf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
336
#else
337
    vpc = m32rbf_pbb_begin (current_cpu, 0);
338
#endif
339
#endif
340
#endif
341
  }
342
 
343
#undef FLD
344
}
345
  NEXT (vpc);
346
 
347
  CASE (sem, INSN_ADD) : /* add $dr,$sr */
348
{
349
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
350
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
351
#define FLD(f) abuf->fields.sfmt_add.f
352
  int UNUSED written = 0;
353
  IADDR UNUSED pc = abuf->addr;
354
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
355
 
356
  {
357
    SI opval = ADDSI (* FLD (i_dr), * FLD (i_sr));
358
    * FLD (i_dr) = opval;
359
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
360
  }
361
 
362
#undef FLD
363
}
364
  NEXT (vpc);
365
 
366
  CASE (sem, INSN_ADD3) : /* add3 $dr,$sr,$hash$slo16 */
367
{
368
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
369
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
370
#define FLD(f) abuf->fields.sfmt_add3.f
371
  int UNUSED written = 0;
372
  IADDR UNUSED pc = abuf->addr;
373
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
374
 
375
  {
376
    SI opval = ADDSI (* FLD (i_sr), FLD (f_simm16));
377
    * FLD (i_dr) = opval;
378
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
379
  }
380
 
381
#undef FLD
382
}
383
  NEXT (vpc);
384
 
385
  CASE (sem, INSN_AND) : /* and $dr,$sr */
386
{
387
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
388
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
389
#define FLD(f) abuf->fields.sfmt_add.f
390
  int UNUSED written = 0;
391
  IADDR UNUSED pc = abuf->addr;
392
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
393
 
394
  {
395
    SI opval = ANDSI (* FLD (i_dr), * FLD (i_sr));
396
    * FLD (i_dr) = opval;
397
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
398
  }
399
 
400
#undef FLD
401
}
402
  NEXT (vpc);
403
 
404
  CASE (sem, INSN_AND3) : /* and3 $dr,$sr,$uimm16 */
405
{
406
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
407
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
408
#define FLD(f) abuf->fields.sfmt_and3.f
409
  int UNUSED written = 0;
410
  IADDR UNUSED pc = abuf->addr;
411
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
412
 
413
  {
414
    SI opval = ANDSI (* FLD (i_sr), FLD (f_uimm16));
415
    * FLD (i_dr) = opval;
416
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
417
  }
418
 
419
#undef FLD
420
}
421
  NEXT (vpc);
422
 
423
  CASE (sem, INSN_OR) : /* or $dr,$sr */
424
{
425
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
426
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
427
#define FLD(f) abuf->fields.sfmt_add.f
428
  int UNUSED written = 0;
429
  IADDR UNUSED pc = abuf->addr;
430
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
431
 
432
  {
433
    SI opval = ORSI (* FLD (i_dr), * FLD (i_sr));
434
    * FLD (i_dr) = opval;
435
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
436
  }
437
 
438
#undef FLD
439
}
440
  NEXT (vpc);
441
 
442
  CASE (sem, INSN_OR3) : /* or3 $dr,$sr,$hash$ulo16 */
443
{
444
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
445
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
446
#define FLD(f) abuf->fields.sfmt_and3.f
447
  int UNUSED written = 0;
448
  IADDR UNUSED pc = abuf->addr;
449
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
450
 
451
  {
452
    SI opval = ORSI (* FLD (i_sr), FLD (f_uimm16));
453
    * FLD (i_dr) = opval;
454
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
455
  }
456
 
457
#undef FLD
458
}
459
  NEXT (vpc);
460
 
461
  CASE (sem, INSN_XOR) : /* xor $dr,$sr */
462
{
463
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
464
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
465
#define FLD(f) abuf->fields.sfmt_add.f
466
  int UNUSED written = 0;
467
  IADDR UNUSED pc = abuf->addr;
468
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
469
 
470
  {
471
    SI opval = XORSI (* FLD (i_dr), * FLD (i_sr));
472
    * FLD (i_dr) = opval;
473
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
474
  }
475
 
476
#undef FLD
477
}
478
  NEXT (vpc);
479
 
480
  CASE (sem, INSN_XOR3) : /* xor3 $dr,$sr,$uimm16 */
481
{
482
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
483
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
484
#define FLD(f) abuf->fields.sfmt_and3.f
485
  int UNUSED written = 0;
486
  IADDR UNUSED pc = abuf->addr;
487
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
488
 
489
  {
490
    SI opval = XORSI (* FLD (i_sr), FLD (f_uimm16));
491
    * FLD (i_dr) = opval;
492
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
493
  }
494
 
495
#undef FLD
496
}
497
  NEXT (vpc);
498
 
499
  CASE (sem, INSN_ADDI) : /* addi $dr,$simm8 */
500
{
501
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
502
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
503
#define FLD(f) abuf->fields.sfmt_addi.f
504
  int UNUSED written = 0;
505
  IADDR UNUSED pc = abuf->addr;
506
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
507
 
508
  {
509
    SI opval = ADDSI (* FLD (i_dr), FLD (f_simm8));
510
    * FLD (i_dr) = opval;
511
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
512
  }
513
 
514
#undef FLD
515
}
516
  NEXT (vpc);
517
 
518
  CASE (sem, INSN_ADDV) : /* addv $dr,$sr */
519
{
520
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
521
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
522
#define FLD(f) abuf->fields.sfmt_add.f
523
  int UNUSED written = 0;
524
  IADDR UNUSED pc = abuf->addr;
525
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
526
 
527
{
528
  SI temp0;BI temp1;
529
  temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr));
530
  temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0);
531
  {
532
    SI opval = temp0;
533
    * FLD (i_dr) = opval;
534
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
535
  }
536
  {
537
    BI opval = temp1;
538
    CPU (h_cond) = opval;
539
    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
540
  }
541
}
542
 
543
#undef FLD
544
}
545
  NEXT (vpc);
546
 
547
  CASE (sem, INSN_ADDV3) : /* addv3 $dr,$sr,$simm16 */
548
{
549
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
550
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
551
#define FLD(f) abuf->fields.sfmt_add3.f
552
  int UNUSED written = 0;
553
  IADDR UNUSED pc = abuf->addr;
554
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
555
 
556
{
557
  SI temp0;BI temp1;
558
  temp0 = ADDSI (* FLD (i_sr), FLD (f_simm16));
559
  temp1 = ADDOFSI (* FLD (i_sr), FLD (f_simm16), 0);
560
  {
561
    SI opval = temp0;
562
    * FLD (i_dr) = opval;
563
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
564
  }
565
  {
566
    BI opval = temp1;
567
    CPU (h_cond) = opval;
568
    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
569
  }
570
}
571
 
572
#undef FLD
573
}
574
  NEXT (vpc);
575
 
576
  CASE (sem, INSN_ADDX) : /* addx $dr,$sr */
577
{
578
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
579
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
580
#define FLD(f) abuf->fields.sfmt_add.f
581
  int UNUSED written = 0;
582
  IADDR UNUSED pc = abuf->addr;
583
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
584
 
585
{
586
  SI temp0;BI temp1;
587
  temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
588
  temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
589
  {
590
    SI opval = temp0;
591
    * FLD (i_dr) = opval;
592
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
593
  }
594
  {
595
    BI opval = temp1;
596
    CPU (h_cond) = opval;
597
    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
598
  }
599
}
600
 
601
#undef FLD
602
}
603
  NEXT (vpc);
604
 
605
  CASE (sem, INSN_BC8) : /* bc.s $disp8 */
606
{
607
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
608
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
609
#define FLD(f) abuf->fields.sfmt_bl8.f
610
  int UNUSED written = 0;
611
  IADDR UNUSED pc = abuf->addr;
612
  SEM_BRANCH_INIT
613
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
614
 
615
if (CPU (h_cond)) {
616
  {
617
    USI opval = FLD (i_disp8);
618
    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
619
    written |= (1 << 2);
620
    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
621
  }
622
}
623
 
624
  abuf->written = written;
625
  SEM_BRANCH_FINI (vpc);
626
#undef FLD
627
}
628
  NEXT (vpc);
629
 
630
  CASE (sem, INSN_BC24) : /* bc.l $disp24 */
631
{
632
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
633
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
634
#define FLD(f) abuf->fields.sfmt_bl24.f
635
  int UNUSED written = 0;
636
  IADDR UNUSED pc = abuf->addr;
637
  SEM_BRANCH_INIT
638
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
639
 
640
if (CPU (h_cond)) {
641
  {
642
    USI opval = FLD (i_disp24);
643
    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
644
    written |= (1 << 2);
645
    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
646
  }
647
}
648
 
649
  abuf->written = written;
650
  SEM_BRANCH_FINI (vpc);
651
#undef FLD
652
}
653
  NEXT (vpc);
654
 
655
  CASE (sem, INSN_BEQ) : /* beq $src1,$src2,$disp16 */
656
{
657
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
658
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
659
#define FLD(f) abuf->fields.sfmt_beq.f
660
  int UNUSED written = 0;
661
  IADDR UNUSED pc = abuf->addr;
662
  SEM_BRANCH_INIT
663
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
664
 
665
if (EQSI (* FLD (i_src1), * FLD (i_src2))) {
666
  {
667
    USI opval = FLD (i_disp16);
668
    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
669
    written |= (1 << 3);
670
    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
671
  }
672
}
673
 
674
  abuf->written = written;
675
  SEM_BRANCH_FINI (vpc);
676
#undef FLD
677
}
678
  NEXT (vpc);
679
 
680
  CASE (sem, INSN_BEQZ) : /* beqz $src2,$disp16 */
681
{
682
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
683
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
684
#define FLD(f) abuf->fields.sfmt_beq.f
685
  int UNUSED written = 0;
686
  IADDR UNUSED pc = abuf->addr;
687
  SEM_BRANCH_INIT
688
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
689
 
690
if (EQSI (* FLD (i_src2), 0)) {
691
  {
692
    USI opval = FLD (i_disp16);
693
    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
694
    written |= (1 << 2);
695
    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
696
  }
697
}
698
 
699
  abuf->written = written;
700
  SEM_BRANCH_FINI (vpc);
701
#undef FLD
702
}
703
  NEXT (vpc);
704
 
705
  CASE (sem, INSN_BGEZ) : /* bgez $src2,$disp16 */
706
{
707
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
708
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
709
#define FLD(f) abuf->fields.sfmt_beq.f
710
  int UNUSED written = 0;
711
  IADDR UNUSED pc = abuf->addr;
712
  SEM_BRANCH_INIT
713
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
714
 
715
if (GESI (* FLD (i_src2), 0)) {
716
  {
717
    USI opval = FLD (i_disp16);
718
    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
719
    written |= (1 << 2);
720
    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
721
  }
722
}
723
 
724
  abuf->written = written;
725
  SEM_BRANCH_FINI (vpc);
726
#undef FLD
727
}
728
  NEXT (vpc);
729
 
730
  CASE (sem, INSN_BGTZ) : /* bgtz $src2,$disp16 */
731
{
732
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
733
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
734
#define FLD(f) abuf->fields.sfmt_beq.f
735
  int UNUSED written = 0;
736
  IADDR UNUSED pc = abuf->addr;
737
  SEM_BRANCH_INIT
738
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
739
 
740
if (GTSI (* FLD (i_src2), 0)) {
741
  {
742
    USI opval = FLD (i_disp16);
743
    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
744
    written |= (1 << 2);
745
    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
746
  }
747
}
748
 
749
  abuf->written = written;
750
  SEM_BRANCH_FINI (vpc);
751
#undef FLD
752
}
753
  NEXT (vpc);
754
 
755
  CASE (sem, INSN_BLEZ) : /* blez $src2,$disp16 */
756
{
757
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
758
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
759
#define FLD(f) abuf->fields.sfmt_beq.f
760
  int UNUSED written = 0;
761
  IADDR UNUSED pc = abuf->addr;
762
  SEM_BRANCH_INIT
763
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
764
 
765
if (LESI (* FLD (i_src2), 0)) {
766
  {
767
    USI opval = FLD (i_disp16);
768
    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
769
    written |= (1 << 2);
770
    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
771
  }
772
}
773
 
774
  abuf->written = written;
775
  SEM_BRANCH_FINI (vpc);
776
#undef FLD
777
}
778
  NEXT (vpc);
779
 
780
  CASE (sem, INSN_BLTZ) : /* bltz $src2,$disp16 */
781
{
782
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
783
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
784
#define FLD(f) abuf->fields.sfmt_beq.f
785
  int UNUSED written = 0;
786
  IADDR UNUSED pc = abuf->addr;
787
  SEM_BRANCH_INIT
788
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
789
 
790
if (LTSI (* FLD (i_src2), 0)) {
791
  {
792
    USI opval = FLD (i_disp16);
793
    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
794
    written |= (1 << 2);
795
    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
796
  }
797
}
798
 
799
  abuf->written = written;
800
  SEM_BRANCH_FINI (vpc);
801
#undef FLD
802
}
803
  NEXT (vpc);
804
 
805
  CASE (sem, INSN_BNEZ) : /* bnez $src2,$disp16 */
806
{
807
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
808
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
809
#define FLD(f) abuf->fields.sfmt_beq.f
810
  int UNUSED written = 0;
811
  IADDR UNUSED pc = abuf->addr;
812
  SEM_BRANCH_INIT
813
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
814
 
815
if (NESI (* FLD (i_src2), 0)) {
816
  {
817
    USI opval = FLD (i_disp16);
818
    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
819
    written |= (1 << 2);
820
    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
821
  }
822
}
823
 
824
  abuf->written = written;
825
  SEM_BRANCH_FINI (vpc);
826
#undef FLD
827
}
828
  NEXT (vpc);
829
 
830
  CASE (sem, INSN_BL8) : /* bl.s $disp8 */
831
{
832
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
833
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
834
#define FLD(f) abuf->fields.sfmt_bl8.f
835
  int UNUSED written = 0;
836
  IADDR UNUSED pc = abuf->addr;
837
  SEM_BRANCH_INIT
838
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
839
 
840
{
841
  {
842
    SI opval = ADDSI (ANDSI (pc, -4), 4);
843
    CPU (h_gr[((UINT) 14)]) = opval;
844
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
845
  }
846
  {
847
    USI opval = FLD (i_disp8);
848
    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
849
    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
850
  }
851
}
852
 
853
  SEM_BRANCH_FINI (vpc);
854
#undef FLD
855
}
856
  NEXT (vpc);
857
 
858
  CASE (sem, INSN_BL24) : /* bl.l $disp24 */
859
{
860
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
861
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
862
#define FLD(f) abuf->fields.sfmt_bl24.f
863
  int UNUSED written = 0;
864
  IADDR UNUSED pc = abuf->addr;
865
  SEM_BRANCH_INIT
866
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
867
 
868
{
869
  {
870
    SI opval = ADDSI (pc, 4);
871
    CPU (h_gr[((UINT) 14)]) = opval;
872
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
873
  }
874
  {
875
    USI opval = FLD (i_disp24);
876
    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
877
    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
878
  }
879
}
880
 
881
  SEM_BRANCH_FINI (vpc);
882
#undef FLD
883
}
884
  NEXT (vpc);
885
 
886
  CASE (sem, INSN_BNC8) : /* bnc.s $disp8 */
887
{
888
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
889
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
890
#define FLD(f) abuf->fields.sfmt_bl8.f
891
  int UNUSED written = 0;
892
  IADDR UNUSED pc = abuf->addr;
893
  SEM_BRANCH_INIT
894
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
895
 
896
if (NOTBI (CPU (h_cond))) {
897
  {
898
    USI opval = FLD (i_disp8);
899
    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
900
    written |= (1 << 2);
901
    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
902
  }
903
}
904
 
905
  abuf->written = written;
906
  SEM_BRANCH_FINI (vpc);
907
#undef FLD
908
}
909
  NEXT (vpc);
910
 
911
  CASE (sem, INSN_BNC24) : /* bnc.l $disp24 */
912
{
913
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
914
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
915
#define FLD(f) abuf->fields.sfmt_bl24.f
916
  int UNUSED written = 0;
917
  IADDR UNUSED pc = abuf->addr;
918
  SEM_BRANCH_INIT
919
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
920
 
921
if (NOTBI (CPU (h_cond))) {
922
  {
923
    USI opval = FLD (i_disp24);
924
    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
925
    written |= (1 << 2);
926
    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
927
  }
928
}
929
 
930
  abuf->written = written;
931
  SEM_BRANCH_FINI (vpc);
932
#undef FLD
933
}
934
  NEXT (vpc);
935
 
936
  CASE (sem, INSN_BNE) : /* bne $src1,$src2,$disp16 */
937
{
938
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
939
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
940
#define FLD(f) abuf->fields.sfmt_beq.f
941
  int UNUSED written = 0;
942
  IADDR UNUSED pc = abuf->addr;
943
  SEM_BRANCH_INIT
944
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
945
 
946
if (NESI (* FLD (i_src1), * FLD (i_src2))) {
947
  {
948
    USI opval = FLD (i_disp16);
949
    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
950
    written |= (1 << 3);
951
    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
952
  }
953
}
954
 
955
  abuf->written = written;
956
  SEM_BRANCH_FINI (vpc);
957
#undef FLD
958
}
959
  NEXT (vpc);
960
 
961
  CASE (sem, INSN_BRA8) : /* bra.s $disp8 */
962
{
963
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
964
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
965
#define FLD(f) abuf->fields.sfmt_bl8.f
966
  int UNUSED written = 0;
967
  IADDR UNUSED pc = abuf->addr;
968
  SEM_BRANCH_INIT
969
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
970
 
971
  {
972
    USI opval = FLD (i_disp8);
973
    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
974
    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
975
  }
976
 
977
  SEM_BRANCH_FINI (vpc);
978
#undef FLD
979
}
980
  NEXT (vpc);
981
 
982
  CASE (sem, INSN_BRA24) : /* bra.l $disp24 */
983
{
984
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
985
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
986
#define FLD(f) abuf->fields.sfmt_bl24.f
987
  int UNUSED written = 0;
988
  IADDR UNUSED pc = abuf->addr;
989
  SEM_BRANCH_INIT
990
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
991
 
992
  {
993
    USI opval = FLD (i_disp24);
994
    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
995
    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
996
  }
997
 
998
  SEM_BRANCH_FINI (vpc);
999
#undef FLD
1000
}
1001
  NEXT (vpc);
1002
 
1003
  CASE (sem, INSN_CMP) : /* cmp $src1,$src2 */
1004
{
1005
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1006
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1007
#define FLD(f) abuf->fields.sfmt_st_plus.f
1008
  int UNUSED written = 0;
1009
  IADDR UNUSED pc = abuf->addr;
1010
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1011
 
1012
  {
1013
    BI opval = LTSI (* FLD (i_src1), * FLD (i_src2));
1014
    CPU (h_cond) = opval;
1015
    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
1016
  }
1017
 
1018
#undef FLD
1019
}
1020
  NEXT (vpc);
1021
 
1022
  CASE (sem, INSN_CMPI) : /* cmpi $src2,$simm16 */
1023
{
1024
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1025
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1026
#define FLD(f) abuf->fields.sfmt_st_d.f
1027
  int UNUSED written = 0;
1028
  IADDR UNUSED pc = abuf->addr;
1029
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1030
 
1031
  {
1032
    BI opval = LTSI (* FLD (i_src2), FLD (f_simm16));
1033
    CPU (h_cond) = opval;
1034
    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
1035
  }
1036
 
1037
#undef FLD
1038
}
1039
  NEXT (vpc);
1040
 
1041
  CASE (sem, INSN_CMPU) : /* cmpu $src1,$src2 */
1042
{
1043
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1044
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1045
#define FLD(f) abuf->fields.sfmt_st_plus.f
1046
  int UNUSED written = 0;
1047
  IADDR UNUSED pc = abuf->addr;
1048
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1049
 
1050
  {
1051
    BI opval = LTUSI (* FLD (i_src1), * FLD (i_src2));
1052
    CPU (h_cond) = opval;
1053
    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
1054
  }
1055
 
1056
#undef FLD
1057
}
1058
  NEXT (vpc);
1059
 
1060
  CASE (sem, INSN_CMPUI) : /* cmpui $src2,$simm16 */
1061
{
1062
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1063
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1064
#define FLD(f) abuf->fields.sfmt_st_d.f
1065
  int UNUSED written = 0;
1066
  IADDR UNUSED pc = abuf->addr;
1067
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1068
 
1069
  {
1070
    BI opval = LTUSI (* FLD (i_src2), FLD (f_simm16));
1071
    CPU (h_cond) = opval;
1072
    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
1073
  }
1074
 
1075
#undef FLD
1076
}
1077
  NEXT (vpc);
1078
 
1079
  CASE (sem, INSN_DIV) : /* div $dr,$sr */
1080
{
1081
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1082
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1083
#define FLD(f) abuf->fields.sfmt_add.f
1084
  int UNUSED written = 0;
1085
  IADDR UNUSED pc = abuf->addr;
1086
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1087
 
1088
if (NESI (* FLD (i_sr), 0)) {
1089
  {
1090
    SI opval = DIVSI (* FLD (i_dr), * FLD (i_sr));
1091
    * FLD (i_dr) = opval;
1092
    written |= (1 << 2);
1093
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1094
  }
1095
}
1096
 
1097
  abuf->written = written;
1098
#undef FLD
1099
}
1100
  NEXT (vpc);
1101
 
1102
  CASE (sem, INSN_DIVU) : /* divu $dr,$sr */
1103
{
1104
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1105
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1106
#define FLD(f) abuf->fields.sfmt_add.f
1107
  int UNUSED written = 0;
1108
  IADDR UNUSED pc = abuf->addr;
1109
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1110
 
1111
if (NESI (* FLD (i_sr), 0)) {
1112
  {
1113
    SI opval = UDIVSI (* FLD (i_dr), * FLD (i_sr));
1114
    * FLD (i_dr) = opval;
1115
    written |= (1 << 2);
1116
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1117
  }
1118
}
1119
 
1120
  abuf->written = written;
1121
#undef FLD
1122
}
1123
  NEXT (vpc);
1124
 
1125
  CASE (sem, INSN_REM) : /* rem $dr,$sr */
1126
{
1127
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1128
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1129
#define FLD(f) abuf->fields.sfmt_add.f
1130
  int UNUSED written = 0;
1131
  IADDR UNUSED pc = abuf->addr;
1132
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1133
 
1134
if (NESI (* FLD (i_sr), 0)) {
1135
  {
1136
    SI opval = MODSI (* FLD (i_dr), * FLD (i_sr));
1137
    * FLD (i_dr) = opval;
1138
    written |= (1 << 2);
1139
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1140
  }
1141
}
1142
 
1143
  abuf->written = written;
1144
#undef FLD
1145
}
1146
  NEXT (vpc);
1147
 
1148
  CASE (sem, INSN_REMU) : /* remu $dr,$sr */
1149
{
1150
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1151
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1152
#define FLD(f) abuf->fields.sfmt_add.f
1153
  int UNUSED written = 0;
1154
  IADDR UNUSED pc = abuf->addr;
1155
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1156
 
1157
if (NESI (* FLD (i_sr), 0)) {
1158
  {
1159
    SI opval = UMODSI (* FLD (i_dr), * FLD (i_sr));
1160
    * FLD (i_dr) = opval;
1161
    written |= (1 << 2);
1162
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1163
  }
1164
}
1165
 
1166
  abuf->written = written;
1167
#undef FLD
1168
}
1169
  NEXT (vpc);
1170
 
1171
  CASE (sem, INSN_JL) : /* jl $sr */
1172
{
1173
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1174
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1175
#define FLD(f) abuf->fields.sfmt_jl.f
1176
  int UNUSED written = 0;
1177
  IADDR UNUSED pc = abuf->addr;
1178
  SEM_BRANCH_INIT
1179
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1180
 
1181
{
1182
  SI temp0;USI temp1;
1183
  temp0 = ADDSI (ANDSI (pc, -4), 4);
1184
  temp1 = ANDSI (* FLD (i_sr), -4);
1185
  {
1186
    SI opval = temp0;
1187
    CPU (h_gr[((UINT) 14)]) = opval;
1188
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1189
  }
1190
  {
1191
    USI opval = temp1;
1192
    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
1193
    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1194
  }
1195
}
1196
 
1197
  SEM_BRANCH_FINI (vpc);
1198
#undef FLD
1199
}
1200
  NEXT (vpc);
1201
 
1202
  CASE (sem, INSN_JMP) : /* jmp $sr */
1203
{
1204
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1205
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1206
#define FLD(f) abuf->fields.sfmt_jl.f
1207
  int UNUSED written = 0;
1208
  IADDR UNUSED pc = abuf->addr;
1209
  SEM_BRANCH_INIT
1210
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1211
 
1212
  {
1213
    USI opval = ANDSI (* FLD (i_sr), -4);
1214
    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
1215
    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1216
  }
1217
 
1218
  SEM_BRANCH_FINI (vpc);
1219
#undef FLD
1220
}
1221
  NEXT (vpc);
1222
 
1223
  CASE (sem, INSN_LD) : /* ld $dr,@$sr */
1224
{
1225
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1226
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1227
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1228
  int UNUSED written = 0;
1229
  IADDR UNUSED pc = abuf->addr;
1230
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1231
 
1232
  {
1233
    SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
1234
    * FLD (i_dr) = opval;
1235
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1236
  }
1237
 
1238
#undef FLD
1239
}
1240
  NEXT (vpc);
1241
 
1242
  CASE (sem, INSN_LD_D) : /* ld $dr,@($slo16,$sr) */
1243
{
1244
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1245
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1246
#define FLD(f) abuf->fields.sfmt_add3.f
1247
  int UNUSED written = 0;
1248
  IADDR UNUSED pc = abuf->addr;
1249
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1250
 
1251
  {
1252
    SI opval = GETMEMSI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)));
1253
    * FLD (i_dr) = opval;
1254
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1255
  }
1256
 
1257
#undef FLD
1258
}
1259
  NEXT (vpc);
1260
 
1261
  CASE (sem, INSN_LDB) : /* ldb $dr,@$sr */
1262
{
1263
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1264
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1265
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1266
  int UNUSED written = 0;
1267
  IADDR UNUSED pc = abuf->addr;
1268
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1269
 
1270
  {
1271
    SI opval = EXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
1272
    * FLD (i_dr) = opval;
1273
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1274
  }
1275
 
1276
#undef FLD
1277
}
1278
  NEXT (vpc);
1279
 
1280
  CASE (sem, INSN_LDB_D) : /* ldb $dr,@($slo16,$sr) */
1281
{
1282
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1283
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1284
#define FLD(f) abuf->fields.sfmt_add3.f
1285
  int UNUSED written = 0;
1286
  IADDR UNUSED pc = abuf->addr;
1287
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1288
 
1289
  {
1290
    SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
1291
    * FLD (i_dr) = opval;
1292
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1293
  }
1294
 
1295
#undef FLD
1296
}
1297
  NEXT (vpc);
1298
 
1299
  CASE (sem, INSN_LDH) : /* ldh $dr,@$sr */
1300
{
1301
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1302
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1303
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1304
  int UNUSED written = 0;
1305
  IADDR UNUSED pc = abuf->addr;
1306
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1307
 
1308
  {
1309
    SI opval = EXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
1310
    * FLD (i_dr) = opval;
1311
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1312
  }
1313
 
1314
#undef FLD
1315
}
1316
  NEXT (vpc);
1317
 
1318
  CASE (sem, INSN_LDH_D) : /* ldh $dr,@($slo16,$sr) */
1319
{
1320
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1321
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1322
#define FLD(f) abuf->fields.sfmt_add3.f
1323
  int UNUSED written = 0;
1324
  IADDR UNUSED pc = abuf->addr;
1325
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1326
 
1327
  {
1328
    SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
1329
    * FLD (i_dr) = opval;
1330
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1331
  }
1332
 
1333
#undef FLD
1334
}
1335
  NEXT (vpc);
1336
 
1337
  CASE (sem, INSN_LDUB) : /* ldub $dr,@$sr */
1338
{
1339
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1340
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1341
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1342
  int UNUSED written = 0;
1343
  IADDR UNUSED pc = abuf->addr;
1344
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1345
 
1346
  {
1347
    SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
1348
    * FLD (i_dr) = opval;
1349
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1350
  }
1351
 
1352
#undef FLD
1353
}
1354
  NEXT (vpc);
1355
 
1356
  CASE (sem, INSN_LDUB_D) : /* ldub $dr,@($slo16,$sr) */
1357
{
1358
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1359
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1360
#define FLD(f) abuf->fields.sfmt_add3.f
1361
  int UNUSED written = 0;
1362
  IADDR UNUSED pc = abuf->addr;
1363
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1364
 
1365
  {
1366
    SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
1367
    * FLD (i_dr) = opval;
1368
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1369
  }
1370
 
1371
#undef FLD
1372
}
1373
  NEXT (vpc);
1374
 
1375
  CASE (sem, INSN_LDUH) : /* lduh $dr,@$sr */
1376
{
1377
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1378
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1379
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1380
  int UNUSED written = 0;
1381
  IADDR UNUSED pc = abuf->addr;
1382
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1383
 
1384
  {
1385
    SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
1386
    * FLD (i_dr) = opval;
1387
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1388
  }
1389
 
1390
#undef FLD
1391
}
1392
  NEXT (vpc);
1393
 
1394
  CASE (sem, INSN_LDUH_D) : /* lduh $dr,@($slo16,$sr) */
1395
{
1396
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1397
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1398
#define FLD(f) abuf->fields.sfmt_add3.f
1399
  int UNUSED written = 0;
1400
  IADDR UNUSED pc = abuf->addr;
1401
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1402
 
1403
  {
1404
    SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
1405
    * FLD (i_dr) = opval;
1406
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1407
  }
1408
 
1409
#undef FLD
1410
}
1411
  NEXT (vpc);
1412
 
1413
  CASE (sem, INSN_LD_PLUS) : /* ld $dr,@$sr+ */
1414
{
1415
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1416
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1417
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1418
  int UNUSED written = 0;
1419
  IADDR UNUSED pc = abuf->addr;
1420
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1421
 
1422
{
1423
  SI temp0;SI temp1;
1424
  temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr));
1425
  temp1 = ADDSI (* FLD (i_sr), 4);
1426
  {
1427
    SI opval = temp0;
1428
    * FLD (i_dr) = opval;
1429
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1430
  }
1431
  {
1432
    SI opval = temp1;
1433
    * FLD (i_sr) = opval;
1434
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1435
  }
1436
}
1437
 
1438
#undef FLD
1439
}
1440
  NEXT (vpc);
1441
 
1442
  CASE (sem, INSN_LD24) : /* ld24 $dr,$uimm24 */
1443
{
1444
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1445
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1446
#define FLD(f) abuf->fields.sfmt_ld24.f
1447
  int UNUSED written = 0;
1448
  IADDR UNUSED pc = abuf->addr;
1449
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1450
 
1451
  {
1452
    SI opval = FLD (i_uimm24);
1453
    * FLD (i_dr) = opval;
1454
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1455
  }
1456
 
1457
#undef FLD
1458
}
1459
  NEXT (vpc);
1460
 
1461
  CASE (sem, INSN_LDI8) : /* ldi8 $dr,$simm8 */
1462
{
1463
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1464
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1465
#define FLD(f) abuf->fields.sfmt_addi.f
1466
  int UNUSED written = 0;
1467
  IADDR UNUSED pc = abuf->addr;
1468
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1469
 
1470
  {
1471
    SI opval = FLD (f_simm8);
1472
    * FLD (i_dr) = opval;
1473
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1474
  }
1475
 
1476
#undef FLD
1477
}
1478
  NEXT (vpc);
1479
 
1480
  CASE (sem, INSN_LDI16) : /* ldi16 $dr,$hash$slo16 */
1481
{
1482
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1483
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1484
#define FLD(f) abuf->fields.sfmt_add3.f
1485
  int UNUSED written = 0;
1486
  IADDR UNUSED pc = abuf->addr;
1487
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1488
 
1489
  {
1490
    SI opval = FLD (f_simm16);
1491
    * FLD (i_dr) = opval;
1492
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1493
  }
1494
 
1495
#undef FLD
1496
}
1497
  NEXT (vpc);
1498
 
1499
  CASE (sem, INSN_LOCK) : /* lock $dr,@$sr */
1500
{
1501
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1502
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1503
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1504
  int UNUSED written = 0;
1505
  IADDR UNUSED pc = abuf->addr;
1506
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1507
 
1508
{
1509
  {
1510
    BI opval = 1;
1511
    CPU (h_lock) = opval;
1512
    TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
1513
  }
1514
  {
1515
    SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
1516
    * FLD (i_dr) = opval;
1517
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1518
  }
1519
}
1520
 
1521
#undef FLD
1522
}
1523
  NEXT (vpc);
1524
 
1525
  CASE (sem, INSN_MACHI) : /* machi $src1,$src2 */
1526
{
1527
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1528
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1529
#define FLD(f) abuf->fields.sfmt_st_plus.f
1530
  int UNUSED written = 0;
1531
  IADDR UNUSED pc = abuf->addr;
1532
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1533
 
1534
  {
1535
    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
1536
    SET_H_ACCUM (opval);
1537
    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1538
  }
1539
 
1540
#undef FLD
1541
}
1542
  NEXT (vpc);
1543
 
1544
  CASE (sem, INSN_MACLO) : /* maclo $src1,$src2 */
1545
{
1546
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1547
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1548
#define FLD(f) abuf->fields.sfmt_st_plus.f
1549
  int UNUSED written = 0;
1550
  IADDR UNUSED pc = abuf->addr;
1551
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1552
 
1553
  {
1554
    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
1555
    SET_H_ACCUM (opval);
1556
    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1557
  }
1558
 
1559
#undef FLD
1560
}
1561
  NEXT (vpc);
1562
 
1563
  CASE (sem, INSN_MACWHI) : /* macwhi $src1,$src2 */
1564
{
1565
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1566
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1567
#define FLD(f) abuf->fields.sfmt_st_plus.f
1568
  int UNUSED written = 0;
1569
  IADDR UNUSED pc = abuf->addr;
1570
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1571
 
1572
  {
1573
    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
1574
    SET_H_ACCUM (opval);
1575
    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1576
  }
1577
 
1578
#undef FLD
1579
}
1580
  NEXT (vpc);
1581
 
1582
  CASE (sem, INSN_MACWLO) : /* macwlo $src1,$src2 */
1583
{
1584
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1585
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1586
#define FLD(f) abuf->fields.sfmt_st_plus.f
1587
  int UNUSED written = 0;
1588
  IADDR UNUSED pc = abuf->addr;
1589
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1590
 
1591
  {
1592
    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
1593
    SET_H_ACCUM (opval);
1594
    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1595
  }
1596
 
1597
#undef FLD
1598
}
1599
  NEXT (vpc);
1600
 
1601
  CASE (sem, INSN_MUL) : /* mul $dr,$sr */
1602
{
1603
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1604
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1605
#define FLD(f) abuf->fields.sfmt_add.f
1606
  int UNUSED written = 0;
1607
  IADDR UNUSED pc = abuf->addr;
1608
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1609
 
1610
  {
1611
    SI opval = MULSI (* FLD (i_dr), * FLD (i_sr));
1612
    * FLD (i_dr) = opval;
1613
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1614
  }
1615
 
1616
#undef FLD
1617
}
1618
  NEXT (vpc);
1619
 
1620
  CASE (sem, INSN_MULHI) : /* mulhi $src1,$src2 */
1621
{
1622
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1623
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1624
#define FLD(f) abuf->fields.sfmt_st_plus.f
1625
  int UNUSED written = 0;
1626
  IADDR UNUSED pc = abuf->addr;
1627
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1628
 
1629
  {
1630
    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 16), 16);
1631
    SET_H_ACCUM (opval);
1632
    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1633
  }
1634
 
1635
#undef FLD
1636
}
1637
  NEXT (vpc);
1638
 
1639
  CASE (sem, INSN_MULLO) : /* mullo $src1,$src2 */
1640
{
1641
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1642
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1643
#define FLD(f) abuf->fields.sfmt_st_plus.f
1644
  int UNUSED written = 0;
1645
  IADDR UNUSED pc = abuf->addr;
1646
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1647
 
1648
  {
1649
    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 16), 16);
1650
    SET_H_ACCUM (opval);
1651
    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1652
  }
1653
 
1654
#undef FLD
1655
}
1656
  NEXT (vpc);
1657
 
1658
  CASE (sem, INSN_MULWHI) : /* mulwhi $src1,$src2 */
1659
{
1660
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1661
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1662
#define FLD(f) abuf->fields.sfmt_st_plus.f
1663
  int UNUSED written = 0;
1664
  IADDR UNUSED pc = abuf->addr;
1665
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1666
 
1667
  {
1668
    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 8), 8);
1669
    SET_H_ACCUM (opval);
1670
    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1671
  }
1672
 
1673
#undef FLD
1674
}
1675
  NEXT (vpc);
1676
 
1677
  CASE (sem, INSN_MULWLO) : /* mulwlo $src1,$src2 */
1678
{
1679
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1680
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1681
#define FLD(f) abuf->fields.sfmt_st_plus.f
1682
  int UNUSED written = 0;
1683
  IADDR UNUSED pc = abuf->addr;
1684
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1685
 
1686
  {
1687
    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 8), 8);
1688
    SET_H_ACCUM (opval);
1689
    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1690
  }
1691
 
1692
#undef FLD
1693
}
1694
  NEXT (vpc);
1695
 
1696
  CASE (sem, INSN_MV) : /* mv $dr,$sr */
1697
{
1698
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1699
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1700
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1701
  int UNUSED written = 0;
1702
  IADDR UNUSED pc = abuf->addr;
1703
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1704
 
1705
  {
1706
    SI opval = * FLD (i_sr);
1707
    * FLD (i_dr) = opval;
1708
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1709
  }
1710
 
1711
#undef FLD
1712
}
1713
  NEXT (vpc);
1714
 
1715
  CASE (sem, INSN_MVFACHI) : /* mvfachi $dr */
1716
{
1717
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1718
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1719
#define FLD(f) abuf->fields.sfmt_seth.f
1720
  int UNUSED written = 0;
1721
  IADDR UNUSED pc = abuf->addr;
1722
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1723
 
1724
  {
1725
    SI opval = TRUNCDISI (SRADI (GET_H_ACCUM (), 32));
1726
    * FLD (i_dr) = opval;
1727
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1728
  }
1729
 
1730
#undef FLD
1731
}
1732
  NEXT (vpc);
1733
 
1734
  CASE (sem, INSN_MVFACLO) : /* mvfaclo $dr */
1735
{
1736
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1737
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1738
#define FLD(f) abuf->fields.sfmt_seth.f
1739
  int UNUSED written = 0;
1740
  IADDR UNUSED pc = abuf->addr;
1741
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1742
 
1743
  {
1744
    SI opval = TRUNCDISI (GET_H_ACCUM ());
1745
    * FLD (i_dr) = opval;
1746
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1747
  }
1748
 
1749
#undef FLD
1750
}
1751
  NEXT (vpc);
1752
 
1753
  CASE (sem, INSN_MVFACMI) : /* mvfacmi $dr */
1754
{
1755
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1756
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1757
#define FLD(f) abuf->fields.sfmt_seth.f
1758
  int UNUSED written = 0;
1759
  IADDR UNUSED pc = abuf->addr;
1760
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1761
 
1762
  {
1763
    SI opval = TRUNCDISI (SRADI (GET_H_ACCUM (), 16));
1764
    * FLD (i_dr) = opval;
1765
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1766
  }
1767
 
1768
#undef FLD
1769
}
1770
  NEXT (vpc);
1771
 
1772
  CASE (sem, INSN_MVFC) : /* mvfc $dr,$scr */
1773
{
1774
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1775
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1776
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1777
  int UNUSED written = 0;
1778
  IADDR UNUSED pc = abuf->addr;
1779
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1780
 
1781
  {
1782
    SI opval = GET_H_CR (FLD (f_r2));
1783
    * FLD (i_dr) = opval;
1784
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1785
  }
1786
 
1787
#undef FLD
1788
}
1789
  NEXT (vpc);
1790
 
1791
  CASE (sem, INSN_MVTACHI) : /* mvtachi $src1 */
1792
{
1793
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1794
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1795
#define FLD(f) abuf->fields.sfmt_st_plus.f
1796
  int UNUSED written = 0;
1797
  IADDR UNUSED pc = abuf->addr;
1798
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1799
 
1800
  {
1801
    DI opval = ORDI (ANDDI (GET_H_ACCUM (), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32));
1802
    SET_H_ACCUM (opval);
1803
    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1804
  }
1805
 
1806
#undef FLD
1807
}
1808
  NEXT (vpc);
1809
 
1810
  CASE (sem, INSN_MVTACLO) : /* mvtaclo $src1 */
1811
{
1812
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1813
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1814
#define FLD(f) abuf->fields.sfmt_st_plus.f
1815
  int UNUSED written = 0;
1816
  IADDR UNUSED pc = abuf->addr;
1817
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1818
 
1819
  {
1820
    DI opval = ORDI (ANDDI (GET_H_ACCUM (), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (i_src1)));
1821
    SET_H_ACCUM (opval);
1822
    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1823
  }
1824
 
1825
#undef FLD
1826
}
1827
  NEXT (vpc);
1828
 
1829
  CASE (sem, INSN_MVTC) : /* mvtc $sr,$dcr */
1830
{
1831
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1832
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1833
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1834
  int UNUSED written = 0;
1835
  IADDR UNUSED pc = abuf->addr;
1836
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1837
 
1838
  {
1839
    USI opval = * FLD (i_sr);
1840
    SET_H_CR (FLD (f_r1), opval);
1841
    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
1842
  }
1843
 
1844
#undef FLD
1845
}
1846
  NEXT (vpc);
1847
 
1848
  CASE (sem, INSN_NEG) : /* neg $dr,$sr */
1849
{
1850
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1851
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1852
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1853
  int UNUSED written = 0;
1854
  IADDR UNUSED pc = abuf->addr;
1855
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1856
 
1857
  {
1858
    SI opval = NEGSI (* FLD (i_sr));
1859
    * FLD (i_dr) = opval;
1860
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1861
  }
1862
 
1863
#undef FLD
1864
}
1865
  NEXT (vpc);
1866
 
1867
  CASE (sem, INSN_NOP) : /* nop */
1868
{
1869
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1870
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1871
#define FLD(f) abuf->fields.fmt_empty.f
1872
  int UNUSED written = 0;
1873
  IADDR UNUSED pc = abuf->addr;
1874
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1875
 
1876
PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
1877
 
1878
#undef FLD
1879
}
1880
  NEXT (vpc);
1881
 
1882
  CASE (sem, INSN_NOT) : /* not $dr,$sr */
1883
{
1884
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1885
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1886
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1887
  int UNUSED written = 0;
1888
  IADDR UNUSED pc = abuf->addr;
1889
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1890
 
1891
  {
1892
    SI opval = INVSI (* FLD (i_sr));
1893
    * FLD (i_dr) = opval;
1894
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1895
  }
1896
 
1897
#undef FLD
1898
}
1899
  NEXT (vpc);
1900
 
1901
  CASE (sem, INSN_RAC) : /* rac */
1902
{
1903
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1904
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1905
#define FLD(f) abuf->fields.fmt_empty.f
1906
  int UNUSED written = 0;
1907
  IADDR UNUSED pc = abuf->addr;
1908
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1909
 
1910
{
1911
  DI tmp_tmp1;
1912
  tmp_tmp1 = SLLDI (GET_H_ACCUM (), 1);
1913
  tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768));
1914
  {
1915
    DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000)));
1916
    SET_H_ACCUM (opval);
1917
    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1918
  }
1919
}
1920
 
1921
#undef FLD
1922
}
1923
  NEXT (vpc);
1924
 
1925
  CASE (sem, INSN_RACH) : /* rach */
1926
{
1927
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1928
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1929
#define FLD(f) abuf->fields.fmt_empty.f
1930
  int UNUSED written = 0;
1931
  IADDR UNUSED pc = abuf->addr;
1932
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1933
 
1934
{
1935
  DI tmp_tmp1;
1936
  tmp_tmp1 = ANDDI (GET_H_ACCUM (), MAKEDI (16777215, 0xffffffff));
1937
if (ANDIF (GEDI (tmp_tmp1, MAKEDI (16383, 0x80000000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) {
1938
  tmp_tmp1 = MAKEDI (16383, 0x80000000);
1939
} else {
1940
if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760832, 0)))) {
1941
  tmp_tmp1 = MAKEDI (16760832, 0);
1942
} else {
1943
  tmp_tmp1 = ANDDI (ADDDI (GET_H_ACCUM (), MAKEDI (0, 1073741824)), MAKEDI (0xffffffff, 0x80000000));
1944
}
1945
}
1946
  tmp_tmp1 = SLLDI (tmp_tmp1, 1);
1947
  {
1948
    DI opval = SRADI (SLLDI (tmp_tmp1, 7), 7);
1949
    SET_H_ACCUM (opval);
1950
    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1951
  }
1952
}
1953
 
1954
#undef FLD
1955
}
1956
  NEXT (vpc);
1957
 
1958
  CASE (sem, INSN_RTE) : /* rte */
1959
{
1960
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1961
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1962
#define FLD(f) abuf->fields.fmt_empty.f
1963
  int UNUSED written = 0;
1964
  IADDR UNUSED pc = abuf->addr;
1965
  SEM_BRANCH_INIT
1966
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1967
 
1968
{
1969
  {
1970
    USI opval = ANDSI (GET_H_CR (((UINT) 6)), -4);
1971
    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
1972
    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1973
  }
1974
  {
1975
    USI opval = GET_H_CR (((UINT) 14));
1976
    SET_H_CR (((UINT) 6), opval);
1977
    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
1978
  }
1979
  {
1980
    UQI opval = CPU (h_bpsw);
1981
    SET_H_PSW (opval);
1982
    TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
1983
  }
1984
  {
1985
    UQI opval = CPU (h_bbpsw);
1986
    CPU (h_bpsw) = opval;
1987
    TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
1988
  }
1989
}
1990
 
1991
  SEM_BRANCH_FINI (vpc);
1992
#undef FLD
1993
}
1994
  NEXT (vpc);
1995
 
1996
  CASE (sem, INSN_SETH) : /* seth $dr,$hash$hi16 */
1997
{
1998
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1999
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2000
#define FLD(f) abuf->fields.sfmt_seth.f
2001
  int UNUSED written = 0;
2002
  IADDR UNUSED pc = abuf->addr;
2003
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2004
 
2005
  {
2006
    SI opval = SLLSI (FLD (f_hi16), 16);
2007
    * FLD (i_dr) = opval;
2008
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2009
  }
2010
 
2011
#undef FLD
2012
}
2013
  NEXT (vpc);
2014
 
2015
  CASE (sem, INSN_SLL) : /* sll $dr,$sr */
2016
{
2017
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2018
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2019
#define FLD(f) abuf->fields.sfmt_add.f
2020
  int UNUSED written = 0;
2021
  IADDR UNUSED pc = abuf->addr;
2022
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2023
 
2024
  {
2025
    SI opval = SLLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
2026
    * FLD (i_dr) = opval;
2027
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2028
  }
2029
 
2030
#undef FLD
2031
}
2032
  NEXT (vpc);
2033
 
2034
  CASE (sem, INSN_SLL3) : /* sll3 $dr,$sr,$simm16 */
2035
{
2036
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2037
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2038
#define FLD(f) abuf->fields.sfmt_add3.f
2039
  int UNUSED written = 0;
2040
  IADDR UNUSED pc = abuf->addr;
2041
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2042
 
2043
  {
2044
    SI opval = SLLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
2045
    * FLD (i_dr) = opval;
2046
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2047
  }
2048
 
2049
#undef FLD
2050
}
2051
  NEXT (vpc);
2052
 
2053
  CASE (sem, INSN_SLLI) : /* slli $dr,$uimm5 */
2054
{
2055
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2056
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2057
#define FLD(f) abuf->fields.sfmt_slli.f
2058
  int UNUSED written = 0;
2059
  IADDR UNUSED pc = abuf->addr;
2060
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2061
 
2062
  {
2063
    SI opval = SLLSI (* FLD (i_dr), FLD (f_uimm5));
2064
    * FLD (i_dr) = opval;
2065
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2066
  }
2067
 
2068
#undef FLD
2069
}
2070
  NEXT (vpc);
2071
 
2072
  CASE (sem, INSN_SRA) : /* sra $dr,$sr */
2073
{
2074
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2075
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2076
#define FLD(f) abuf->fields.sfmt_add.f
2077
  int UNUSED written = 0;
2078
  IADDR UNUSED pc = abuf->addr;
2079
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2080
 
2081
  {
2082
    SI opval = SRASI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
2083
    * FLD (i_dr) = opval;
2084
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2085
  }
2086
 
2087
#undef FLD
2088
}
2089
  NEXT (vpc);
2090
 
2091
  CASE (sem, INSN_SRA3) : /* sra3 $dr,$sr,$simm16 */
2092
{
2093
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2094
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2095
#define FLD(f) abuf->fields.sfmt_add3.f
2096
  int UNUSED written = 0;
2097
  IADDR UNUSED pc = abuf->addr;
2098
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2099
 
2100
  {
2101
    SI opval = SRASI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
2102
    * FLD (i_dr) = opval;
2103
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2104
  }
2105
 
2106
#undef FLD
2107
}
2108
  NEXT (vpc);
2109
 
2110
  CASE (sem, INSN_SRAI) : /* srai $dr,$uimm5 */
2111
{
2112
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2113
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2114
#define FLD(f) abuf->fields.sfmt_slli.f
2115
  int UNUSED written = 0;
2116
  IADDR UNUSED pc = abuf->addr;
2117
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2118
 
2119
  {
2120
    SI opval = SRASI (* FLD (i_dr), FLD (f_uimm5));
2121
    * FLD (i_dr) = opval;
2122
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2123
  }
2124
 
2125
#undef FLD
2126
}
2127
  NEXT (vpc);
2128
 
2129
  CASE (sem, INSN_SRL) : /* srl $dr,$sr */
2130
{
2131
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2132
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2133
#define FLD(f) abuf->fields.sfmt_add.f
2134
  int UNUSED written = 0;
2135
  IADDR UNUSED pc = abuf->addr;
2136
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2137
 
2138
  {
2139
    SI opval = SRLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
2140
    * FLD (i_dr) = opval;
2141
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2142
  }
2143
 
2144
#undef FLD
2145
}
2146
  NEXT (vpc);
2147
 
2148
  CASE (sem, INSN_SRL3) : /* srl3 $dr,$sr,$simm16 */
2149
{
2150
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2151
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2152
#define FLD(f) abuf->fields.sfmt_add3.f
2153
  int UNUSED written = 0;
2154
  IADDR UNUSED pc = abuf->addr;
2155
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2156
 
2157
  {
2158
    SI opval = SRLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
2159
    * FLD (i_dr) = opval;
2160
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2161
  }
2162
 
2163
#undef FLD
2164
}
2165
  NEXT (vpc);
2166
 
2167
  CASE (sem, INSN_SRLI) : /* srli $dr,$uimm5 */
2168
{
2169
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2170
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2171
#define FLD(f) abuf->fields.sfmt_slli.f
2172
  int UNUSED written = 0;
2173
  IADDR UNUSED pc = abuf->addr;
2174
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2175
 
2176
  {
2177
    SI opval = SRLSI (* FLD (i_dr), FLD (f_uimm5));
2178
    * FLD (i_dr) = opval;
2179
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2180
  }
2181
 
2182
#undef FLD
2183
}
2184
  NEXT (vpc);
2185
 
2186
  CASE (sem, INSN_ST) : /* st $src1,@$src2 */
2187
{
2188
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2189
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2190
#define FLD(f) abuf->fields.sfmt_st_plus.f
2191
  int UNUSED written = 0;
2192
  IADDR UNUSED pc = abuf->addr;
2193
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2194
 
2195
  {
2196
    SI opval = * FLD (i_src1);
2197
    SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
2198
    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2199
  }
2200
 
2201
#undef FLD
2202
}
2203
  NEXT (vpc);
2204
 
2205
  CASE (sem, INSN_ST_D) : /* st $src1,@($slo16,$src2) */
2206
{
2207
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2208
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2209
#define FLD(f) abuf->fields.sfmt_st_d.f
2210
  int UNUSED written = 0;
2211
  IADDR UNUSED pc = abuf->addr;
2212
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2213
 
2214
  {
2215
    SI opval = * FLD (i_src1);
2216
    SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
2217
    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2218
  }
2219
 
2220
#undef FLD
2221
}
2222
  NEXT (vpc);
2223
 
2224
  CASE (sem, INSN_STB) : /* stb $src1,@$src2 */
2225
{
2226
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2227
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2228
#define FLD(f) abuf->fields.sfmt_st_plus.f
2229
  int UNUSED written = 0;
2230
  IADDR UNUSED pc = abuf->addr;
2231
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2232
 
2233
  {
2234
    QI opval = * FLD (i_src1);
2235
    SETMEMQI (current_cpu, pc, * FLD (i_src2), opval);
2236
    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2237
  }
2238
 
2239
#undef FLD
2240
}
2241
  NEXT (vpc);
2242
 
2243
  CASE (sem, INSN_STB_D) : /* stb $src1,@($slo16,$src2) */
2244
{
2245
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2246
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2247
#define FLD(f) abuf->fields.sfmt_st_d.f
2248
  int UNUSED written = 0;
2249
  IADDR UNUSED pc = abuf->addr;
2250
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2251
 
2252
  {
2253
    QI opval = * FLD (i_src1);
2254
    SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
2255
    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2256
  }
2257
 
2258
#undef FLD
2259
}
2260
  NEXT (vpc);
2261
 
2262
  CASE (sem, INSN_STH) : /* sth $src1,@$src2 */
2263
{
2264
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2265
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2266
#define FLD(f) abuf->fields.sfmt_st_plus.f
2267
  int UNUSED written = 0;
2268
  IADDR UNUSED pc = abuf->addr;
2269
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2270
 
2271
  {
2272
    HI opval = * FLD (i_src1);
2273
    SETMEMHI (current_cpu, pc, * FLD (i_src2), opval);
2274
    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2275
  }
2276
 
2277
#undef FLD
2278
}
2279
  NEXT (vpc);
2280
 
2281
  CASE (sem, INSN_STH_D) : /* sth $src1,@($slo16,$src2) */
2282
{
2283
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2284
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2285
#define FLD(f) abuf->fields.sfmt_st_d.f
2286
  int UNUSED written = 0;
2287
  IADDR UNUSED pc = abuf->addr;
2288
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2289
 
2290
  {
2291
    HI opval = * FLD (i_src1);
2292
    SETMEMHI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
2293
    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2294
  }
2295
 
2296
#undef FLD
2297
}
2298
  NEXT (vpc);
2299
 
2300
  CASE (sem, INSN_ST_PLUS) : /* st $src1,@+$src2 */
2301
{
2302
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2303
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2304
#define FLD(f) abuf->fields.sfmt_st_plus.f
2305
  int UNUSED written = 0;
2306
  IADDR UNUSED pc = abuf->addr;
2307
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2308
 
2309
{
2310
  SI tmp_new_src2;
2311
  tmp_new_src2 = ADDSI (* FLD (i_src2), 4);
2312
  {
2313
    SI opval = * FLD (i_src1);
2314
    SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
2315
    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2316
  }
2317
  {
2318
    SI opval = tmp_new_src2;
2319
    * FLD (i_src2) = opval;
2320
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2321
  }
2322
}
2323
 
2324
#undef FLD
2325
}
2326
  NEXT (vpc);
2327
 
2328
  CASE (sem, INSN_ST_MINUS) : /* st $src1,@-$src2 */
2329
{
2330
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2331
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2332
#define FLD(f) abuf->fields.sfmt_st_plus.f
2333
  int UNUSED written = 0;
2334
  IADDR UNUSED pc = abuf->addr;
2335
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2336
 
2337
{
2338
  SI tmp_new_src2;
2339
  tmp_new_src2 = SUBSI (* FLD (i_src2), 4);
2340
  {
2341
    SI opval = * FLD (i_src1);
2342
    SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
2343
    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2344
  }
2345
  {
2346
    SI opval = tmp_new_src2;
2347
    * FLD (i_src2) = opval;
2348
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2349
  }
2350
}
2351
 
2352
#undef FLD
2353
}
2354
  NEXT (vpc);
2355
 
2356
  CASE (sem, INSN_SUB) : /* sub $dr,$sr */
2357
{
2358
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2359
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2360
#define FLD(f) abuf->fields.sfmt_add.f
2361
  int UNUSED written = 0;
2362
  IADDR UNUSED pc = abuf->addr;
2363
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2364
 
2365
  {
2366
    SI opval = SUBSI (* FLD (i_dr), * FLD (i_sr));
2367
    * FLD (i_dr) = opval;
2368
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2369
  }
2370
 
2371
#undef FLD
2372
}
2373
  NEXT (vpc);
2374
 
2375
  CASE (sem, INSN_SUBV) : /* subv $dr,$sr */
2376
{
2377
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2378
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2379
#define FLD(f) abuf->fields.sfmt_add.f
2380
  int UNUSED written = 0;
2381
  IADDR UNUSED pc = abuf->addr;
2382
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2383
 
2384
{
2385
  SI temp0;BI temp1;
2386
  temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr));
2387
  temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0);
2388
  {
2389
    SI opval = temp0;
2390
    * FLD (i_dr) = opval;
2391
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2392
  }
2393
  {
2394
    BI opval = temp1;
2395
    CPU (h_cond) = opval;
2396
    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
2397
  }
2398
}
2399
 
2400
#undef FLD
2401
}
2402
  NEXT (vpc);
2403
 
2404
  CASE (sem, INSN_SUBX) : /* subx $dr,$sr */
2405
{
2406
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2407
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2408
#define FLD(f) abuf->fields.sfmt_add.f
2409
  int UNUSED written = 0;
2410
  IADDR UNUSED pc = abuf->addr;
2411
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2412
 
2413
{
2414
  SI temp0;BI temp1;
2415
  temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
2416
  temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
2417
  {
2418
    SI opval = temp0;
2419
    * FLD (i_dr) = opval;
2420
    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2421
  }
2422
  {
2423
    BI opval = temp1;
2424
    CPU (h_cond) = opval;
2425
    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
2426
  }
2427
}
2428
 
2429
#undef FLD
2430
}
2431
  NEXT (vpc);
2432
 
2433
  CASE (sem, INSN_TRAP) : /* trap $uimm4 */
2434
{
2435
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2436
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2437
#define FLD(f) abuf->fields.sfmt_trap.f
2438
  int UNUSED written = 0;
2439
  IADDR UNUSED pc = abuf->addr;
2440
  SEM_BRANCH_INIT
2441
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2442
 
2443
{
2444
  {
2445
    USI opval = GET_H_CR (((UINT) 6));
2446
    SET_H_CR (((UINT) 14), opval);
2447
    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
2448
  }
2449
  {
2450
    USI opval = ADDSI (pc, 4);
2451
    SET_H_CR (((UINT) 6), opval);
2452
    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
2453
  }
2454
  {
2455
    UQI opval = CPU (h_bpsw);
2456
    CPU (h_bbpsw) = opval;
2457
    TRACE_RESULT (current_cpu, abuf, "bbpsw", 'x', opval);
2458
  }
2459
  {
2460
    UQI opval = GET_H_PSW ();
2461
    CPU (h_bpsw) = opval;
2462
    TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
2463
  }
2464
  {
2465
    UQI opval = ANDQI (GET_H_PSW (), 128);
2466
    SET_H_PSW (opval);
2467
    TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
2468
  }
2469
  {
2470
    SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4));
2471
    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
2472
    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
2473
  }
2474
}
2475
 
2476
  SEM_BRANCH_FINI (vpc);
2477
#undef FLD
2478
}
2479
  NEXT (vpc);
2480
 
2481
  CASE (sem, INSN_UNLOCK) : /* unlock $src1,@$src2 */
2482
{
2483
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2484
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2485
#define FLD(f) abuf->fields.sfmt_st_plus.f
2486
  int UNUSED written = 0;
2487
  IADDR UNUSED pc = abuf->addr;
2488
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2489
 
2490
{
2491
if (CPU (h_lock)) {
2492
  {
2493
    SI opval = * FLD (i_src1);
2494
    SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
2495
    written |= (1 << 4);
2496
    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2497
  }
2498
}
2499
  {
2500
    BI opval = 0;
2501
    CPU (h_lock) = opval;
2502
    TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
2503
  }
2504
}
2505
 
2506
  abuf->written = written;
2507
#undef FLD
2508
}
2509
  NEXT (vpc);
2510
 
2511
  CASE (sem, INSN_CLRPSW) : /* clrpsw $uimm8 */
2512
{
2513
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2514
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2515
#define FLD(f) abuf->fields.sfmt_clrpsw.f
2516
  int UNUSED written = 0;
2517
  IADDR UNUSED pc = abuf->addr;
2518
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2519
 
2520
  {
2521
    SI opval = ANDSI (GET_H_CR (((UINT) 0)), ORSI (INVBI (FLD (f_uimm8)), 65280));
2522
    SET_H_CR (((UINT) 0), opval);
2523
    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
2524
  }
2525
 
2526
#undef FLD
2527
}
2528
  NEXT (vpc);
2529
 
2530
  CASE (sem, INSN_SETPSW) : /* setpsw $uimm8 */
2531
{
2532
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2533
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2534
#define FLD(f) abuf->fields.sfmt_clrpsw.f
2535
  int UNUSED written = 0;
2536
  IADDR UNUSED pc = abuf->addr;
2537
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2538
 
2539
  {
2540
    SI opval = FLD (f_uimm8);
2541
    SET_H_CR (((UINT) 0), opval);
2542
    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
2543
  }
2544
 
2545
#undef FLD
2546
}
2547
  NEXT (vpc);
2548
 
2549
  CASE (sem, INSN_BSET) : /* bset $uimm3,@($slo16,$sr) */
2550
{
2551
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2552
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2553
#define FLD(f) abuf->fields.sfmt_bset.f
2554
  int UNUSED written = 0;
2555
  IADDR UNUSED pc = abuf->addr;
2556
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2557
 
2558
  {
2559
    QI opval = ORQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), SLLSI (1, SUBSI (7, FLD (f_uimm3))));
2560
    SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval);
2561
    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2562
  }
2563
 
2564
#undef FLD
2565
}
2566
  NEXT (vpc);
2567
 
2568
  CASE (sem, INSN_BCLR) : /* bclr $uimm3,@($slo16,$sr) */
2569
{
2570
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2571
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2572
#define FLD(f) abuf->fields.sfmt_bset.f
2573
  int UNUSED written = 0;
2574
  IADDR UNUSED pc = abuf->addr;
2575
  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2576
 
2577
  {
2578
    QI opval = ANDQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), INVQI (SLLSI (1, SUBSI (7, FLD (f_uimm3)))));
2579
    SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval);
2580
    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2581
  }
2582
 
2583
#undef FLD
2584
}
2585
  NEXT (vpc);
2586
 
2587
  CASE (sem, INSN_BTST) : /* btst $uimm3,$sr */
2588
{
2589
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2590
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2591
#define FLD(f) abuf->fields.sfmt_bset.f
2592
  int UNUSED written = 0;
2593
  IADDR UNUSED pc = abuf->addr;
2594
  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2595
 
2596
  {
2597
    BI opval = ANDQI (SRLSI (* FLD (i_sr), SUBSI (7, FLD (f_uimm3))), 1);
2598
    CPU (h_cond) = opval;
2599
    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
2600
  }
2601
 
2602
#undef FLD
2603
}
2604
  NEXT (vpc);
2605
 
2606
 
2607
    }
2608
  ENDSWITCH (sem) /* End of semantic switch.  */
2609
 
2610
  /* At this point `vpc' contains the next insn to execute.  */
2611
}
2612
 
2613
#undef DEFINE_SWITCH
2614
#endif /* DEFINE_SWITCH */

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